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| Features * High Performance, Low Power AVR(R)32 UC 32-Bit Microcontroller - Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set - Read-Modify-Write Instructions and Atomic Bit Manipulation - Performing 1.49DMIPS/MHz * Up to 91DMIPS Running at 66MHz from Flash (1 Wait-State) * Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) - Memory Protection Unit Multi-Layer Bus System - High-Performance Data Transfers on Separate Buses for Increased Performance - 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication - 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash - 256KBytes, 128KBytes, 64KBytes versions - Single-Cycle Flash Access up to 36MHz - Prefetch Buffer Optimizing Instruction Execution at Maximum Speed - 4 ms Page Programming Time and 8ms Full-Chip Erase Time - 100,000 Write Cycles, 15-year Data Retention Capability - Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM - 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus - 64KBytes on the Multi-Layer Bus System Interrupt Controller - Autovectored Low Latency Interrupt Service with Programmable Priority System Functions - Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator - Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), - Watchdog Timer, Real-Time Clock Timer External Memories - Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash - Up to 66 MHz External Storage device support - MultiMediaCard (MMC), Secure-Digital (SD), SDIO V1.1 - CE-ATA, FastSD, SmartMedia, Compact Flash - Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro - IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S and AT32UC3A364S - 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications - Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) - High-Speed USB (480Mbit/s) Device/MiniHost with On-The-Go (OTG) - Flexible End-Point Configuration and Management with Dedicated DMA Channels - On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - Independent Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces * * AVR(R)32 32-Bit Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 * * * Preliminary * * * * * * * 32072A-AVR32-03/09 AT32UC3A3 - Support for Hardware Handshaking, RS485 Interfaces and Modem Line * Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals * One Synchronous Serial Protocol Controller - Supports I2S and Generic Frame-Based Protocols * Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible * On-Chip Debug System (JTAG interface) - Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace * 110 General Purpose Input/Output (GPIOs) - Standard or High Speed mode - Toggle capability: up to 66MHz * 144-pin TBGA and LQFP * Single 3.3V Power Supply 2 32072A-AVR32-03/09 AT32UC3A3 1. Description The AT32UC3A3 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3 incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. Additionally, a flexible Synchronous Serial Controller (SSC) and an USB are available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The High-Speed (480 MBit/s) USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The On-The-Go (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. AT32UC3A3 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072A-AVR32-03/09 AT32UC3A3 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBG VBUS DH+,DL+ DH-,DLID VBOF NEXUS CLASS 2+ OCD UC CPU MEMORY PROTECTION UNIT MEMORY INTERFACE TCK TDO TDI TMS JTAG INTERFACE LOCAL BUS INTERFACE FAST GPIO INSTR INTERFACE PBB DATA INTERFACE 64 KB SRAM FLASH CONTROLLER USB HS INTERFACE DMA S M M M M M S S 512/256/ 128/64 KB FLASH DMACA M S EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) HIGH SPEED BUS MATRIX DATA[15..0] ADDR[23..0] NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDCS1 SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE AES GENERAL PURPOSE IOs 32KB RAM 32KB RAM DMA S S HRAM S S CONFIGURATION S REGISTERS BUS M PB HSB-PB BRIDGE B HS B HSB HSB-PB BRIDGE A PB PBA PERIPHERAL DMA CONTROLLER CLK CMD[1..0] PA PB PC PX DATA[15..0] DMA PDC USART1 GENERAL PURPOSE IOs MULTIMEDIA CARD & MEMORY STICK INTERFACE RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS EXTINT[7..0] KPS[7..0] NMI_N PDC EXTERNAL INTERRUPT CONTROLLER PDC INTERRUPT CONTROLLER PA PB PC PX USART0 USART2 RXD USART3 TXD CLK REAL TIME COUNTER PDC SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER SCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA WATCHDOG TIMER 115 kHz RCOSC XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 PDC POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER PDC PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 TWO-WIRE INTERFACE 0/1 SCL SDA ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC PDC AD[7..0] ADVREF DATA[1..0] DATAN[1..0] RESET_N GCLK[3..0] A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 4 32072A-AVR32-03/09 AT32UC3A3 3. Configuration Summary The table below lists all AT32UC3A3 memory and package configurations: Table 3-1. Device AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 Memory and Package Configurations Flash 256KB 256KB 128KB 128KB 64KB 64KB SRAM 128KB 128KB 128KB 128KB 128KB 128KB AES Yes No Yes No Yes No Package 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 5 32072A-AVR32-03/09 AT32UC3A3 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 4-1. TBGA144 Pinout (top view) 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 Table 4-1. 1 A B C D E F G H J K L M PX40 PX10 PX09 PX08 PX38 PX39 PX00 PX01 PX04 PX03 PX11 PX22 BGA144 Package Pinout A1..M8 2 PB00 PB11 PX35 PX37 VDDIO PX07 PX05 VDDIO PX02 PX44 GNDIO PX41 3 PA28 PA31 GNDIO PX36 PX54 PX06 PX59 PX58 PX34 GNDIO PX45 PX42 4 PA27 PB02 PB01 PX47 PX53 PX49 PX50 PX57 PX56 PX46 PX20 PX14 5 PB03 VDDIO PX16 PX19 VDDIO PX48 PX51 VDDIO PX55 PC00 VDDIO PX21 6 PA29 PB04 PX13 PX12 PX15 GNDIO GNDIO PC01 PA14 PX17 PX18 PX23 7 PC02 PC03 PA30 PB10 PB09 GNDIO GNDIO PA17 PA15 PX52 PX43 PX24 8 PC04 VDDIO PB08 PA02 VDDIN PA06 PA23 VDDIO PA19 PA18 ONREG PX25 9 PC05 USB_ VBIAS DPFS PA26 PA25 PA04 PA24 PA21 PA20 PX27 PX26 PX32 10 DPHS DMFS GNDCORE PA11 PA07 PA05 PA03 PA22 TMS GNDIO PX28 PX31 11 DMHS GNDPLL PA08 PB07 VDDCORE PA13 PA00 VDDANA TDO PX29 GNDANA PX30 12 USB_VBUS PA09 PA10 PB06 PA12 PA16 PA01 PB05 RESET_N TCK TDI PX33 6 32072A-AVR32-03/09 AT32UC3A3 Figure 4-2. LQFP144 Pinout 108 109 73 72 144 1 Table 4-2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 37 36 Package Pinout USB_VBUS VDDIO USB_VBIAS GNDIO DMHS DPHS GNDIO DMFS DPFS VDDIO PB08 PC05 PC04 PA30 PA02 PB10 PB09 PC02 PC03 GNDIO VDDIO PB04 PA29 PB03 PB02 PA27 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 PX10 PX35 PX47 PX15 PX48 PX53 PX49 PX36 PX37 PX54 GNDIO VDDIO PX09 PX08 PX38 PX39 PX06 PX07 PX00 PX59 PX58 PX05 PX01 PX04 PX34 PX02 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PX20 PX46 PX50 PX57 PX51 PX56 PX55 PX21 VDDIO GNDIO PX17 PX18 PX23 PX24 PX52 PX43 PX27 PX26 PX28 PX25 PX32 PX29 PX33 PX30 PX31 PC00 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 PA21 PA22 PA23 PA24 PA20 PA19 PA18 PA17 GNDANA VDDANA PA25 PA26 PB05 PA00 PA01 PA05 PA03 PA04 PA06 PA16 PA13 VDDIO GNDIO PA12 PA07 PB06 7 32072A-AVR32-03/09 AT32UC3A3 Table 4-2. 27 28 29 30 31 32 33 34 35 36 Package Pinout PB01 PA28 PA31 PB00 PB11 PX16 PX13 PX12 PX19 PX40 63 64 65 66 67 68 69 70 71 72 PX03 VDDIO GNDIO PX44 PX11 PX14 PX42 PX45 PX41 PX22 99 100 101 102 103 104 105 106 107 108 PC01 PA14 PA15 GNDIO VDDIO TMS TDO RESET_N TCK TDI 135 136 137 138 139 140 141 142 143 144 PB07 PA11 PA08 PA10 PA09 GNDCORE VDDCORE VDDIN ONREG GNDPLL 4.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C, or D. The following table define how the I/O lines on the peripherals A, B, C, or D are multiplexed by the GPIO. Table 4-3. BGA144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 J6 J7 F12 H7 K8 J8 GPIO Controller Function Multiplexing QFP144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 Function A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] Function B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 DAC - DATAN[0] DAC - DATA[0] EIC - EXTINT[6] USB USB_VBOF USB - USB_ID SPI0 - NPCS[2] SPI0 - NPCS[1] TWIMS0 TWALM SPI1 - SCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO Function C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] DAC - DATA[0] DAC - DATAN[0] USB - USB_ID USB - USB_VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] ] Function D 8 32072A-AVR32-03/09 AT32UC3A3 Table 4-3. GPIO Controller Function Multiplexing SSC RX_FRAME_SYN C EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 TWALM USART2 - CTS SSC - RX_DATA SSC RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD DAC - DATA[1] DAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYN C J9 H9 H10 G8 G9 E9 D9 A4 A3 A6 C7 B3 A2 C4 B4 A5 B6 H12 D12 D11 C8 E7 113 109 110 111 112 119 120 26 28 23 14 29 30 27 25 24 22 121 134 135 11 17 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 EIC - EXTINT[8] ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - USB_ID USB USB_VBOF SPI1 - SCK SPI1 - MISO SPI1 - NPCS[0] ADC - AD[4] USB - USB_ID USB - USB_VBOF DAC - DATA[1] DAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS USART3 - CTS TC0 - CLK0 DMACA DMAACK[0] DMACA DMARQ[0] ADC - TRIGGER EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] MSI - SCLK MSI - BS MSI - DATA[0] MSI - DATA[1] MSI - DATA[2] MSI - DATA[3] MSI - INS D7 16 PB10 GPIO 42 SPI1 - MOSI EBI - NCS[5] B2 K5 H6 A7 B7 A8 A9 G1 H1 31 98 99 18 19 13 12 55 59 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 GPIO 43 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 USART1 - RXD PM - GCLK[1] EBI - DATA[10] EBI - DATA[9] USART0 - RXD USART0 - TXD USART1 - RI USART1 - DTR 9 32072A-AVR32-03/09 AT32UC3A3 Table 4-3. J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 M4 E6 C5 K6 L6 D5 L4 M5 M1 M6 M7 M8 GPIO Controller Function Multiplexing 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 85 86 92 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 70 GPIO 71 GPIO 72 GPIO 73 GPIO 74 GPIO 75 GPIO 76 EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] USART3 - RTS USART3 - CTS DMACA DMARQ[1] DMACA DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS TC0 - A0 TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYNC SSC - RX_CLOCK PM - GCLK[0] L9 K9 L10 K11 M11 M10 M9 M12 J3 C2 D3 D2 90 89 91 94 96 97 93 95 61 38 44 45 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 GPIO 77 GPIO 78 GPIO 79 GPIO 80 GPIO 81 GPIO 82 GPIO 83 GPIO 84 GPIO 85 GPIO 86 GPIO 87 GPIO 88 EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EIC - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SCK SPI1 - NPCS[0] PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] 10 32072A-AVR32-03/09 AT32UC3A3 Table 4-3. E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 K7 E4 E3 J5 J4 H4 H3 G3 GPIO Controller Function Multiplexing 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 GPIO 89 GPIO 90 GPIO 91 GPIO 92 GPIO 93 GPIO 94 GPIO 95 GPIO 96 GPIO 97 GPIO 98 GPIO 99 GPIO 100 GPIO 101 GPIO 102 GPIO 103 GPIO 104 GPIO 105 GPIO 106 GPIO 107 GPIO 108 GPIO 109 GPIO 110 EBI - DATA[12] EBI - DATA[11] EBI - SDCS EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] ADC - TRIGGER USB USB_VBOF USB - USB_ID TC1 - B2 DMACA DMAACK[0] DMACA DMARQ[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] MCI - DATA[14] MCI - DATA[13] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] USART1 - RI USART1 - DTR SPI1 - NPCS[1] SPI1 - NPCS[2] USART1 - DCD USART1 - DSR 4.2.1 Oscillator Pinout Table 4-4. pin A7 A8 K5 B7 A9 H6 Oscillator Pinout pin 18 13 98 19 12 99 Pad PC02 PC04 PC00 PC03 PC05 PC01 Oscillator pin xin0 xin1 xin32 xout0 xout1 xout32 11 32072A-AVR32-03/09 AT32UC3A3 4.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-5. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN ONREG I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator ON/OFF Power Power Power Power Control Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL's 1 3.0 to 3.6V 3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6 V VDDCORE GNDANA GNDIO GNDCORE GNDPLL Voltage Regulator Output for Digital Supply Analog Ground I/O Ground DIgital Ground PLL Ground 1.65 to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low 12 32072A-AVR32-03/09 AT32UC3A3 Table 4-5. Signal Name GCLK[2:0] RESET_N Signal Description List Function Generic Clock Pins Reset Pin Type Output Input DMA Controller - DMACA (optional) Low Active Level Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Module - EIM EXTINT[7:0] KPS0 - KPS7 NMI_N External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIO port A Parallel I/O Controller GPIO port B Parallel I/O Controller GPIO port C Parallel I/O Controller GPIO port X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Output Output Output Output Output I/O Output Output Output Output Input Output Output Low Low Low Low Low Low Low Low Low Low 13 32072A-AVR32-03/09 AT32UC3A3 Table 4-5. Signal Name RAS SDA10 SDCK SDCKE SDCS SDWE Signal Description List Function Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Write Enable Type Output Output Output Output Output Output MultiMedia Card Interface - MCI Low Low Active Level Low Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0 MISO MOSI NPCS[3:0] SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC Low RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 B0 B1 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B I/O I/O I/O I/O I/O 14 32072A-AVR32-03/09 AT32UC3A3 Table 4-5. Signal Name B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD RXDN TXD TXDN Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Inverted Receive Data Transmit Data Inverted Transmit Data Output Input Input Output Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB FSDM FSDP HSDM USB Full Speed Data USB Full Speed Data + USB High Speed Data Analog Analog Analog Low Low I/O Input Only USART1 Only USART1 Only USART1 Only USART1 15 32072A-AVR32-03/09 AT32UC3A3 Table 4-5. Signal Name HSDP USB_VBIAS USB_VBUS Signal Description List Function USB High Speed Data + USB VBIAS reference USB VBUS for OTG feature Type Analog Analog Output Connect to the ground through a 6810 ohms (+/- 0.5%) resistor Active Level Comments 4.3.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 4.3.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 4.3.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 4.3.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column "Reset State" of the I/O Controller multiplexing tables. 16 32072A-AVR32-03/09 AT32UC3A3 4.4 4.4.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: * * * * VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pins GNDCORE are common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pin for VDDIO is GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 4.4.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: * One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. * One external 2.2F (or 3.3F) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (100nF NPO and 4.7F X7R). 3.3V CIN2 CIN1 VDDIN ONREG 1.8V Regulator 1.8V COUT2 COUT1 VDDCORE ONREG input must be tied to VDDIN. 17 32072A-AVR32-03/09 AT32UC3A3 5. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 5.1 Features * 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density - DSP extention with saturating arithmetic, and a wide variety of multiply instructions * 3-stage pipeline allows one instruction per clock cycle for most instructions - Byte, halfword, word and double word memory access - Multiple interrupt priority levels * MPU allows for operating systems with memory protection - - - - - 5.2 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core's low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 18 32072A-AVR32-03/09 AT32UC3A3 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 5.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 5-1 on page 20 displays the contents of AVR32UC. 19 32072A-AVR32-03/09 AT32UC3A3 Figure 5-1. Interrupt controller interface Overview of the AVR32UC CPU Reset interface OCD interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master High Speed Bus 5.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 5-2 on page 21 shows an overview of the AVR32UC pipeline stages. CPU Local Bus Data RAM interface CPU Local Bus master 20 32072A-AVR32-03/09 AT32UC3A3 Figure 5-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regf ile Read A LU Regf ile w rite A LU unit Pref etch unit Decode unit Load-store unit LS 5.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 5.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 5.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 5.3.5 21 32072A-AVR32-03/09 AT32UC3A3 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 5-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported alignment Word Word 5.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: * All SIMD instructions * All coprocessor instructions if no coprocessors are present * retj, incjosp, popjc, pushjc * tlbr, tlbs, tlbw * cache 5.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 3. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 22 32072A-AVR32-03/09 AT32UC3A3 5.4 5.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 5-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 5.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 5-4 on page 23 and Figure 5-5 on page 24. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 5-4. Bit 31 The Status Register High Halfword Bit 16 SS LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved Secure State 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 23 32072A-AVR32-03/09 AT32UC3A3 Figure 5-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 5.4.3 5.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 5-2 on page 24. Table 5-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 5.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 24 32072A-AVR32-03/09 AT32UC3A3 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 5.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 5-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 JAVA_LV1 JAVA_LV2 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 25 32072A-AVR32-03/09 AT32UC3A3 Table 5-3. Reg # 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 System Registers (Continued) Address 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 360 364 Name JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 26 32072A-AVR32-03/09 AT32UC3A3 Table 5-3. Reg # 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 System Registers (Continued) Address 368 372 376 380 384 388 392 396 400 404 408 412 416 420 424 428 432 436 440 444 448-764 768-1020 Name MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR Reserved IMPL Function MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Secure State Status Register Secure State Address Flash Register Secure State Address RAM Register Secure State Address 0 Register Secure State Address 1 Register Secure State Stack Pointer System Register Secure State Stack Pointer Application Register Secure State Return Address Register Secure State Return Status Register Reserved for future use IMPLEMENTATION DEFINED 5.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 5-4 on page 30. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception 27 32072A-AVR32-03/09 AT32UC3A3 code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 5.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 5.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source's responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 5-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 5.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of 28 32072A-AVR32-03/09 AT32UC3A3 code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 5.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 5.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 5-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 5-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 29 32072A-AVR32-03/09 AT32UC3A3 Table 5-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x8000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction 30 32072A-AVR32-03/09 AT32UC3A3 6. Memories 6.1 Embedded Memories * Internal High-Speed Flash - 256KBytes (AT32UC3A3256/S) - 128Kbytes (AT32UC3A3128/S) - 64Kbytes (AT32UC3A364/S) * 0 wait state access at up to 36MHz in worst case conditions * 1 wait state access at up to 66MHz in Physical Memory Map The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 6-1. Device AT32UC3A3 Physical Memory Map Size Start Address 0x00000000 0x80000000 0xC0000000 0xC8000000 0xCC000000 0xD8000000 0xDC000000 0xD0000000 0xE0000000 0xFF000000 AT32UC3A325 6 64KByte 256KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte 32KByte Size AT32UC3A312 8 64KByte 128KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte 32KByte Size AT32UC3A36 4 64KByte 64KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte 32KByte Embedded CPU SRAM Embedded Flash EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS4 EBI SRAM CS5 EBI SRAM CS1 /SDRAM CS0 USB Data Embedded System SRAM 0 31 32072A-AVR32-03/09 AT32UC3A3 Table 6-1. Device AT32UC3A3 Physical Memory Map Size Start Address 0xFF008000 0xFFFF0000 0xFFFE0000 AT32UC3A325 6 32KByte 64KByte 64KByte Size AT32UC3A312 8 32KByte 64KByte 64KByte Size AT32UC3A36 4 32KByte 64KByte 64KByte Embedded System SRAM 1 HSB-PB Bridge A HSB-PB Bridge B 6.3 Peripheral Address Map Peripheral Address Mapping Address 0xFF100000 Table 6-2. Peripheral Name DMACA DMA Controller - DMACA Bus 0xFF200000 RESERVED 0xFFFD0000 AES 0xFFFE0000 Advanced Encryption Standard - AES USB 0xFFFE1000 USB 2.0 OTG Interface - USB HMATRIX 0xFFFE1400 HSB Matrix - HMATRIX FLASHC 0xFFFE1C00 Flash Controller - FLASHC SMC 0xFFFE2000 Static Memory Controller - SMC SDRAMC 0xFFFE2400 SDRAM Controller - SDRAMC Error code corrector Hamming and Reed Solomon ECCHRS Bus Monitor module - BUSMON ECCHRS 0xFFFE2800 BUSMON 0xFFFE4000 MCI 0xFFFE8000 Mulitmedia Card Interface - MCI MSI 0xFFFF0000 Memory Stick Interface - MSI PDMA 0xFFFF0800 Peripheral DMA Controller - PDMA INTC Interrupt controller - INTC 32 32072A-AVR32-03/09 AT32UC3A3 Table 6-2. Peripheral Address Mapping 0xFFFF0C00 PM 0xFFFF0D00 Power Manager - PM RTC 0xFFFF0D30 Real Time Counter - RTC WDT 0xFFFF0D80 Watchdog Timer - WDT EIC 0xFFFF1000 External Interrupt Controller - EIC GPIO 0xFFFF1400 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI0 USART0 0xFFFF1800 USART1 0xFFFF1C00 USART2 0xFFFF2000 USART3 0xFFFF2400 SPI0 0xFFFF2800 SPI1 0xFFFF2C00 Serial Peripheral Interface - SPI1 TWIM0 0xFFFF3000 Two-wire Master Interface - TWIM0 TWIM1 0xFFFF3400 Two-wire Master Interface - TWIM1 SSC 0xFFFF3800 Synchronous Serial Controller - SSC TC0 0xFFFF3C00 Timer/Counter - TC0 ADC 0xFFFF4000 Analog to Digital Converter - ADC DAC 0xFFFF4400 Audio Bitstream DAC - DAC TC1 0xFFFF4800 Timer/Counter - TC1 RESERVED 33 32072A-AVR32-03/09 AT32UC3A3 Table 6-2. Peripheral Address Mapping 0xFFFF4c00 RESERVED 0xFFFF5000 TWIS0 0xFFFF5400 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 6.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 6-3. Port A Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) B Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 34 32072A-AVR32-03/09 AT32UC3A3 7. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3. The behavior after power-up is controlled by the Power Manager. For specific details, refer to Section 8. "Power Manager (PM)" on page 36. 7.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system receives a clock with the same frequency as the internal RC Oscillator. 7.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 35 32072A-AVR32-03/09 AT32UC3A3 8. Power Manager (PM) Rev: 2.3.1.0 8.1 Features * * * * * * * * * * * * * Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 4MHZ-16MHz Supports 2 PLLs 48-150MHz Supports 32KHz ultra-low power oscillator Integrated low-power RC oscillator On-the fly frequency change of CPU, HSB, PBA, and PBB clocks Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Generic clocks with wide frequency range provided Automatic identification of reset sources Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control and calibration registers 8.2 Overview The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32KHz oscillator is used to generate the real-time counter clock for high accuracy real-time measurements. The PM also contains a low-power RC oscillator with fast start-up time, which can be used to clock the digital logic. The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules. The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into three clock domains, one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB bus.The three clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the-fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals. Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurrence of interrupts. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 36 32072A-AVR32-03/09 AT32UC3A3 8.3 Block Diagram Figure 8-1. Power Manager Block Diagram Synchronous clocks CPU, HSB, PBA, PBB RCOSC Synchronous Clock Generator PLL0 Oscillator 0 Oscillator 1 PLL1 G eneric Clock Generator Generic clocks 32 KHz Oscillator OSC/PLL Control signals 32 KHz clock for RTC RC Oscillator Slow clock Oscillator and PLL Control Voltage Regulator Startup Counter Interrupts Sleep Controller Sleep instruction fuses Calibration Registers Brown-Out Detector Power-O n Detector Other reset sources External Reset Pad Reset Controller resets 37 32072A-AVR32-03/09 AT32UC3A3 8.4 8.4.1 Product Dependencies I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the GPIO controller. 8.4.2 Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first. 8.5 8.5.1 Functional Description Slow Clock The slow clock is generated from an internal RC oscillator which is always running, except in Static mode. The slow clock can be used for the main clock in the device, as described in Section 8.5.5. The slow clock is also used for the Watchdog Timer and measuring various delays in the Power Manager. The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running. The RC oscillator operates at approximately 115 kHz, and can be calibrated to a narrow range by the RCOSCCAL fuses. Software can also change RC oscillator calibration through the use of the RCCR register. Please see the Electrical Characteristics section for details. RC oscillator can also be used as the RTC clock when crystal accuracy is not required. 8.5.2 Oscillator 0 and 1 Operation The two main oscillators are designed to be used with an external 450 kHz to 16 MHz crystal and two biasing capacitors, as shown in Figure 8-2 on page 39. Oscillator 0 can be used for the main clock in the device, as described in Section 8.5.5. Both oscillators can be used as source for the generic clocks, as described in Section 8.5.8. The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O. The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode (external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are automatically switched off in certain sleep modes to reduce power consumption, as described in Section 8.5.7. After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscillators may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRLn register. The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in Section 8.6.7. 38 32072A-AVR32-03/09 AT32UC3A3 Figure 8-2. Oscillator Connections C2 XO U T XIN C1 8.5.3 32 KHz Oscillator Operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode. While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O. The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY. As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset. 8.5.4 PLL Operation The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency. When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable. 39 32072A-AVR32-03/09 AT32UC3A3 Figure 8-3. PLL with Control Logic and Filters PLLMUL Output Divider Mask PLL clock Osc0 clock Osc1 clock 0 1 Input Divider PLL LOCK PLLOSC PLLDIV PLLEN PLLOPT 8.5.4.1 Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV fields must be written with the multiplication and division factors, respectively, creating the PLL frequency: fPLL = 2*(PLLMUL+1)/(PLLDIV+1) * fOSC The PLLn.PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits. 8.5.5 Synchronous Clocks The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as fCPU fPBA,B,. The synchronous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in Section 8.5.7. Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules. 40 32072A-AVR32-03/09 AT32UC3A3 Figure 8-4. Synchronous Clock Generation Sleep instruction Sleep Controller 0 Slow clock Osc0 clock PLL0 clock Main clock Mask CPUMASK CPU clocks AHB clocks APBAclocks APBB clocks Prescaler 1 CPUDIV M CSEL CPUSEL 8.5.5.1 Selecting PLL or oscillator for the main clock The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default, the main clock will be connected to the slow clock. The user can connect the main clock to Oscillator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain. Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: f CPU = f main 2 ( CPUSEL + 1 ) 8.5.5.2 Similarly, the clock for the PBA, and PBB can be divided by writing their respective fields. To ensure correct operation, frequencies must be selected so that fCPU fPBA,B. Also, frequencies must never exceed the specified maximum frequency for each clock domain. CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep 41 32072A-AVR32-03/09 AT32UC3A3 one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant. 8.5.5.3 Clock ready flag There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER.CKRDY is written to 1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang. Peripheral Clock Masking By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0. When a module is not clocked, it will cease operation, and its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to 1. A module may be connected to several clock domains, in which case it will have several mask bits. Table 8-6 on page 52 contains a list of implemented maskable clocks. 8.5.6.1 Cautionary note The OCD clock must never be switched off if the user wishes to debug the device with a JTAG debugger. Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the internal RAM will cause a problem if the stack is mapped there. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 8.5.6.2 Mask ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the MSKRDY bit in IER. 8.5.6 8.5.7 Sleep Modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument. 42 32072A-AVR32-03/09 AT32UC3A3 8.5.7.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings of the mask registers. Oscillators and PLLs can also be switched off to save power. Some of these modules have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked. 8.5.7.2 Supported sleep modes The following sleep modes are supported. These are detailed in Table 8-1 on page 43. *Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt. *Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupt from PB modules. *Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt. *Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt, or external reset pin. *DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference and BOD is turned off. *Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage reference BOD detector is turned off. Table 8-1. Index 0 1 2 3 4 5 Sleep Modes Sleep Mode Idle Frozen Standby Stop DeepStop Static CPU Stop Stop Stop Stop Stop Stop HSB Run Stop Stop Stop Stop Stop PBA,B GCLK Run Run Stop Stop Stop Stop Osc0,1 PLL0,1 Run Run Run Stop Stop Stop Osc32 Run Run Run Run Run Stop RCOsc Run Run Run Run Run Stop BOD & Bandgap On On On On Off Off Voltage Regulator Full power Full power Full power Low power Low power Low power The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 8.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions. 43 32072A-AVR32-03/09 AT32UC3A3 Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction. The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary. When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete. 8.5.8 Generic Clocks Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies. Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 256. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller. Figure 8-5. Generic Clock Generation Sleep Controller 0 Osc0 clock Osc1 clock PLL0 clock PLL1 clock 0 Mask Divider 1 Generic Clock 1 PLLSEL OSCSEL DIVEN DIV CEN 8.5.8.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits. The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: f GCLK = f SRC ( 2 x ( DIV + 1 ) ) 44 32072A-AVR32-03/09 AT32UC3A3 8.5.8.2 Disabling a generic clock The generic clock can be disabled by writing CEN to 0 or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as 1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock. When the clock is disabled, both the prescaler and output are reset. 8.5.8.3 Changing clock frequency When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition. Generic clock implementation The generic clocks are allocated to different functions as shown in Table 8-2 on page 45. Table 8-2. Generic Clock Allocation Function GCLK0 pin GCLK1 pin GCLK2 pin GCLK3 pin GLCK_USBB 8.5.8.4 Clock number 0 1 2 3 4 8.5.9 Divided PB Clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules. The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx clocks are stopped. 8.5.10 Debug Operation The OCD clock must never be switched off if the user wishes to debug the device with a JTAG debugger. During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use "debug qualified" PBx clocks. This is described in the documentation for the relevant modules. The divided PBx clocks are always debug qualified clocks. Debug qualified PBx clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system. 45 32072A-AVR32-03/09 AT32UC3A3 8.5.11 Reset Controller The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated. Table 8-4 on page 47 lists these and other reset sources supported by the Reset Controller. Figure 8-6. Reset Controller Block Diagram R C_RC AU SE RESET_N P o w e r-O n D e te c to r B ro w n o u t D e te c to r NTAE OCD W a tc h d o g R e s e t CPU, HSB, PBA, PBB R eset C o n tro lle r O C D , R T C /W D T C lo c k G e n e ra to In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details. Table 8-3. Reset source Reset Description Description Supply voltage below the power-on reset detector threshold voltage RESET_N pin asserted Supply voltage below the brownout reset detector threshold voltage Caused by an illegal CPU access to external memory while in Supervisor mode See watchdog timer documentation. See On-Chip Debug documentation Power-on Reset External Reset Brownout Reset CPU Error Watchdog Timer OCD 46 32072A-AVR32-03/09 AT32UC3A3 When a reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip. Table 8-4 on page 47 lists parts of the device that are reset, depending on the reset source. Table 8-4. Effect of the Different Reset Events Power-On Reset CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register GPLP registers Watchdog control register Voltage calibration register RC Oscillator Calibration register BOD control register Bandgap control register Clock control registers Osc0/Osc1 and control registers PLL0/PLL1 and control registers OCD system and OCD registers Y Y Y Y Y Y Y Y Y Y Y Y Y External Reset Y N N N Y N N Y Y Y Y Y Y Watchdog Reset Y N N N N N N N N Y Y Y N BOD Reset Y N N N Y N N N N Y Y Y Y CPU Error Reset Y N N N Y N N N N Y Y Y Y OCD Reset Y N N N Y N N N N Y Y Y N The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken. 8.5.11.1 Power-On detector The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details. Brown-Out detector The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit POSCR.BODET bit. Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. See Electrical Characteristics chapter for parametric details. 47 8.5.11.2 32072A-AVR32-03/09 AT32UC3A3 8.5.11.3 External reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. Calibration Registers The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibrations registers. Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to these registers is protected by a "key". First, a write to the register must be made with the field "KEY" equal to 0x55 then a second write must be issued with the "KEY" field equal to 0xAA. 8.5.12 48 32072A-AVR32-03/09 AT32UC3A3 8.6 User Interface Table 8-5. Offset 0x000 0x0004 0x008 0x00C 0x010 0x014 0x020 0x024 0x028 0x02C 0x030 0x040 0x044 0x048 0x04C 00050 0x054 0x060 0x0C0 0x0C4 0x0C8 0x0D0 0x200 PM Register Memory Map Register Register Name MCCTRL CKSEL CPUMASK HSBMASK PBAMASK PBBMASK PLL0 PLL1 OSCCTRL0 OSCCTRL1 OSCCTRL32 IER IDR IMR ISR ICR POSCSR GCCTRL RCCR BGCR VREGCR BOD GPLP Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00000000 0x00000000 0x00000003 0x00000FFF 0x001FFFFF 0x000003FF 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Factory settings Factory settings Factory settings BOD fuses in Flash 0x00000000 Main Clock Control Clock Select CPU Mask HSB Mask PBA Mask PBB Mask PLL0 Control PLL1 Control Oscillator 0 Control Register Oscillator 1 Control Register Oscillator 32 Control Register PM Interrupt Enable Register PM Interrupt Disable Register PM Interrupt Mask Register PM Interrupt Status Register PM Interrupt Clear Register Power and Oscillators Status Register Generic Clock Control RC Oscillator Calibration Register Bandgap Calibration Register Linear Regulator Calibration Register BOD Level Register General Purpose Low-Power register 49 32072A-AVR32-03/09 AT32UC3A3 8.6.1 Name: Main Clock Control Register MCCTRL Read/Write 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 OSC1EN 2 OSC0EN 1 MCSEL 0 * OSC1EN: Oscillator 1 Enable 1: Oscillator 1 is enabled 0: Oscillator 1 is disabled * OSC0EN: Oscillator 0 Enable 1: Oscillator 0 is enabled 0: Oscillator 0 is disabled * MCSEL: Main Clock Select This field contains the clock selected as the main clock. MCSEL 0b00 0b01 0b10 0b11 Selected Clock Slow Clock Oscillator 0 PLL 0 Reserved 50 32072A-AVR32-03/09 AT32UC3A3 8.6.2 Name: Clock Select Register CKSEL Read/Write 0x04 0x00000000 30 29 28 27 26 25 PBBSEL 24 Access Type: Offset: Reset Value: 31 PBBDIV 23 PBADIV 22 - 21 - 20 - 19 - 18 17 PBASEL 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CPUDIV 6 - 5 - 4 - 3 - 2 1 CPUSEL 0 * PBBDIV: PBB Division Enable PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1). * PBADIV, PBASEL: PBA Division and Clock Select PBADIV = 0: PBA clock equals main clock. PBADIV = 1: PBA clock equals main clock divided by 2(PBASEL+1). * CPUDIV, CPUSEL: CPU/HSB Division and Clock Select CPUDIV = 0: CPU/HSB clock equals main clock. CPUDIV = 1: CPU/HSB clock equals main clock divided by 2(CPUSEL+1). Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high. 51 32072A-AVR32-03/09 AT32UC3A3 8.6.3 Name: Clock Mask Registers CPU/HSB/PBA/PBBMASK Read/Write 0x08-0x14 0x00000000 30 29 28 MASK[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 MASK[23:16] 19 18 17 16 15 14 13 12 MASK[15:8] 11 10 9 8 7 6 5 4 MASK[7:0] 3 2 1 0 * MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 8-6 on page 52. Table 8-6. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Maskable module clocks in AT32UC3A3. HSBMASK FLASHC PBA bridge PBB bridge USBB PDCA EBI PBC bridge DMACA BUSMON HRAMC0 HRAMC1 PBAMASK INTC GPIO PDCA PM/RTC/EIM ADC SPI0 SPI1 TWIM0 TWIM1 TWIS0 TWIS1 USART0 USART1 USART2 USART3 SSC PBBMASK HMATRIX USBB FLASHC SMC SDRAMC HECC MCI BUSMON MSI AES - CPUMASK OCD(1) - 52 32072A-AVR32-03/09 AT32UC3A3 Table 8-6. Bit 16 17 18 19 20 31: 21 Maskable module clocks in AT32UC3A3. HSBMASK PBAMASK TC0 TC1 DAC JTAGM AWM PBBMASK - CPUMASK - Note: 1. This bit must be one if the user wishes to debug the device with a JTAG debugger. 53 32072A-AVR32-03/09 AT32UC3A3 8.6.4 Name: PLL Control Registers PLL0,1 Read/Write 0x20-0x24 0x00000000 30 29 28 27 PLLCOUNT 26 25 24 Access Type: Offset: Reset Value: 31 PLLTEST 23 22 21 20 PLLMUL 19 18 17 16 15 14 13 12 PLLDIV 11 10 9 8 7 - 6 - 5 - 4 3 PLLOPT 2 1 PLLOSC 0 PLLEN * PLLTEST: PLL Test Reserved for internal use. Always write to 0. * PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode. * PLLMUL: PLL Multiply Factor * PLLDIV: PLL Division Factor These fields determine the ratio of the PLL output frequency to the source oscillator frequency: f PLL = 2 x f osc x ( PLLMUL + 1 ) ( PLLDIV + 1 ) fNote that the PLLMUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined. * PLLOPT: PLL Option Select the operating range for the PLL. PLLOPT[0]: Select the VCO frequency range PLLOPT[1]: Enable the extra output divider PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time) Description PLLOPT[0]: VCO frequency 0 1 PLLOPT[1]: Output divider 0 1 fout = fvco fout = fvco/2 160MHz 32072A-AVR32-03/09 AT32UC3A3 Description PLLOPT[2] 0 1 Wide Bandwidth Mode enabled Wide Bandwidth Mode disabled * PLLOSC: PLL Oscillator Select 0: Oscillator 0 is the source for the PLL. 1: Oscillator 1 is the source for the PLL. * PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. 55 32072A-AVR32-03/09 AT32UC3A3 8.6.5 Name: Oscillator 0/1 Control Registers OSCCTRL0,1 Read/Write 0x28-0x2C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 9 STARTUP 8 7 - 6 - 5 - 4 - 3 - 2 1 MODE 0 * STARTUP: Oscillator Startup Time Select startup time for the oscillator. STARTUP 0 1 2 3 4 5 6 7 Number of RC oscillator clock cycle 0 64 128 2048 4096 8192 16384 Reserved Approximative Equivalent time (RCOsc = 115 kHz) 0 560 us 1.1 ms 18 ms 36 ms 71 ms 142 ms Reserved * MODE: Oscillator Mode Choose between crystal, or external clock 0: External clock connected on XIN, XOUT can be used as an I/O (no crystal) 1: Crystal is connected to XIN/XOUT - Oscillator is used with automatic gain control 2 to 7: Reserved 56 32072A-AVR32-03/09 AT32UC3A3 8.6.6 Name: 32 KHz Oscillator Control Register OSCCTRL32 Read/Write 0x30 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 STARTUP 16 15 - 14 - 13 - 12 - 11 - 10 9 MODE 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 OSC32EN * STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator STARTUP 0 1 2 3 4 5 6 7 Number of RC oscillator clock cycle 0 128 8192 16384 65536 131072 262144 524288 Approximative Equivalent time (RCOsc = 115 kHz) 0 1.1 ms 72.3 ms 143 ms 570 ms 1.1 s 2.3 s 4.6 s Note: This register is only reset by Power-On Reset * MODE: Oscillator Mode Choose between crystal, or external clock 0: External clock connected on XIN32, XOUT32 can be used as a I/O (no crystal) 1: Crystal is connected to XIN32/XOUT32 - Oscillator is used with automatic gain control 2 to 7: Reserved * OSC32EN: Enable the 32 KHz oscillator 0: 32 KHz Oscillator is disabled 1: 32 KHz Oscillator is enabled 57 32072A-AVR32-03/09 AT32UC3A3 8.6.7 Name: Interrupt Enable Register IER Write-only 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 Writing a one to a bit in this register will set the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 58 32072A-AVR32-03/09 AT32UC3A3 8.6.8 Name: Interrupt Disable Register IDR Write-only 0x44 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 Writing a one to a bit in this register will clear the corresponding bit in IMR. Writing a zero to a bit in this register has no effect. 59 32072A-AVR32-03/09 AT32UC3A3 8.6.9 Name: Interrupt Mask Register IMR Read-only 0x48 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 60 32072A-AVR32-03/09 AT32UC3A3 8.6.10 Name: Interrupt Status Register ISR Read-only 0x4C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 * BODDET: Brown out detection This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected: BOD has detected that power supply is going below BOD reference value. This bit is cleared when the corresponding bit in ICR is written to one. * OSC32RDY: 32 KHz oscillator Ready This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected: The 32 KHz oscillator is stable and ready to be used as clock source. This bit is cleared when the corresponding bit in ICR is written to one. * OSC1RDY: Oscillator 1 Ready This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used as clock source. This bit is cleared when the corresponding bit in ICR is written to one. * OSC0RDY: Oscillator 0 Ready This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used as clock source. This bit is cleared when the corresponding bit in ICR is written to one. * MSKRDY: Mask Ready This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected: Clocks are now masked according to the (CPU/HSB/PBA/PBB)_MASK registers. This bit is cleared when the corresponding bit in ICR is written to one. * CKRDY: Clock Ready 0: The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register. Note: Writing a one to ICR.CKRDY has no effect. * LOCK1: PLL1 locked This bit is set when a 0 to 1 transition on the POSCSR.LOCK1 bit is detected: PLL 1 is locked and ready to be selected as clock source. This bit is cleared when the corresponding bit in ICR is written to one. 61 32072A-AVR32-03/09 AT32UC3A3 * LOCK0: PLL0 locked This bit is set when a 0 to 1 transition on the POSCSR.LOCK0 bit is detected: PLL 0 is locked and ready to be selected as clock source. This bit is cleared when the corresponding bit in ICR is written to one. 62 32072A-AVR32-03/09 AT32UC3A3 8.6.11 Name: Interrupt Clear Register ICR Write-only 0x50 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 63 32072A-AVR32-03/09 AT32UC3A3 8.6.12 Name: Power and Oscillators Status Register POSCCR Read-only 0x54 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BODDET 15 - 14 - 13 - 12 - 11 - 10 - 9 OSC32RDY 8 OSC1RDY 7 OSC0RDY 6 MSKRDY 5 CKRDY 4 - 3 - 2 - 1 LOCK1 0 LOCK0 * BODDET: Brown out detection 0: No BOD event 1: BOD has detected that power supply is going below BOD reference value. * OSC32RDY: 32 KHz oscillator Ready 0: The 32 KHz oscillator is not enabled or not ready. 1: The 32 KHz oscillator is stable and ready to be used as clock source. * OSC1RDY: OSC1 ready 0: Oscillator 1 not enabled or not ready. 1: Oscillator 1 is stable and ready to be used as clock source. * OSC0RDY: OSC0 ready 0: Oscillator 0 not enabled or not ready. 1: Oscillator 0 is stable and ready to be used as clock source. * MSKRDY: Mask ready 0: Mask register has been changed, masking in progress. 1: Clock are masked according to xxx_MASK * CKRDY: 0: The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register. * LOCK1: PLL 1 locked 0:PLL 1 is unlocked 1:PLL 1 is locked, and ready to be selected as clock source. * LOCK0: PLL 0 locked 0: PLL 0 is unlocked 1: PLL 0 is locked, and ready to be selected as clock source. 64 32072A-AVR32-03/09 AT32UC3A3 8.6.13 Name: Generic Clock Control Register GCCTRL Read/Write 0x60 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 DIV[7:0] 11 10 9 8 7 - 6 - 5 - 4 DIVEN 3 - 2 CEN 1 PLLSEL 0 OSCSEL There is one GCCTRL register per generic clock in the design. * DIV: Division Factor * DIVEN: Divide Enable 0: The generic clock equals the undivided source clock. 1: The generic clock equals the source clock divided by 2*(DIV+1). * CEN: Clock Enable 0: Clock is stopped. 1: Clock is running. * PLLSEL: PLL Select 0: Oscillator is source for the generic clock. 1: PLL is source for the generic clock. * OSCSEL: Oscillator Select 0: Oscillator (or PLL) 0 is source for the generic clock. 1: Oscillator (or PLL) 1 is source for the generic clock. 65 32072A-AVR32-03/09 AT32UC3A3 8.6.14 Name: Reset Cause Register RCAUSE Read-only 0x140 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 JTAGHARD 8 OCDRST 7 CPUERR 6 - 5 - 4 JTAG 3 WDT 2 EXT 1 BOD 0 POR * JTAGHARD: JTAG Hard Reset The chip was reset by setting the bit RC_OCD in the JTAG reset register or by using the JTAG HALT instruction. * OCDRST: OCD Reset The CPU was reset because the RES strobe in the OCD Development Control register has been written to one. * CPUERR: CPU Error The CPU was reset because it had detected an illegal access. * JTAG: JTAG reset The CPU was reset by setting the bit RC_CPU in the JTAG reset register. * WDT: Watchdog Reset The CPU was reset because of a watchdog timeout. * EXT: External Reset Pin The CPU was reset due to the RESET pin being asserted. * BOD: Brown-out Reset The CPU was reset due to the supply voltage being lower than the brown-out threshold level. * POR Power-on Reset The CPU was reset due to the supply voltage being lower than the power-on threshold level. 66 32072A-AVR32-03/09 AT32UC3A3 8.6.15 Name: BOD Control Register BOD Read/Write 0xD0 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 FCD 15 - 14 - 13 - 12 - 11 - 10 - 9 CTRL 8 7 - 6 HYST 5 4 3 LEVEL 2 1 0 * KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. * FCD: BOD Fuse calibration done Set to 1 when CTRL, HYST and LEVEL fields has been updated by the Flash fuses after power-on reset or Flash fuses update If one, the CTRL, HYST and LEVEL values will not be updated again by Flash fuses Can be cleared to allow subsequent overwriting of the value by Flash fuses * CTRL: BOD Control 0: BOD is off 1: BOD is enabled and can reset the chip 2: BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register. 3: BOD is off * HYST: BOD Hysteresis 0: No hysteresis 1: Hysteresis On * LEVEL: BOD Level This field sets the triggering threshold of the BOD. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. 67 32072A-AVR32-03/09 AT32UC3A3 8.6.16 Name: RC Oscillator Calibration Register RCCR Read/Write 0xC0 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 FCD 15 - 14 - 13 - 12 - 11 - 10 - 9 CALIB 8 7 6 5 4 CALIB 3 2 1 0 * KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. * FCD: Flash Calibration Done Set to 1 when CTRL, HYST, and LEVEL fields have been updated by the Flash fuses after power-on reset, or after Flash fuses are reprogrammed. The CTRL, HYST and LEVEL values will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. * CALIB: Calibration Value Calibration Value for the RC oscillator. 68 32072A-AVR32-03/09 AT32UC3A3 8.6.17 Name: Bandgap Calibration Register BGCR Read/Write 0xC4 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 FCD 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 CALIB 0 * KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. * FCD: Flash Calibration Done Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. * CALIB: Calibration value Calibration value for Bandgap. See Electrical Characteristics for voltage values. 69 32072A-AVR32-03/09 AT32UC3A3 8.6.18 Name: PM Voltage Regulator Calibration Register VREGCR Read/Write 0xC8 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 FCD 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 CALIB 0 * KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect. Calibration value for Voltage Regulator. See Electrical Characteristics for voltage values. * FCD: Flash Calibration Done Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. * CALIB: Calibration value 70 32072A-AVR32-03/09 AT32UC3A3 8.6.19 Name: General Purpose Low-power Register GPLP Read/Write 0x200 0x00000000 30 29 28 GPLP 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 GPLP 19 18 17 16 15 14 13 12 GPLP 11 10 9 8 7 6 5 4 GPLP 3 2 1 0 These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these registers untouched. 71 32072A-AVR32-03/09 AT32UC3A3 9. Real Time Counter (RTC) Rev: 2.3.1.1 9.1 Features * 32-bit real-time counter with 16-bit prescaler * Clocked from RC oscillator or 32KHz oscillator * Long delays * * * * - Max timeout 272years High resolution: Max count frequency 16KHz Extremely low power consumption Available in all sleep modes except Static Interrupt on wrap 9.2 Overview The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from the system RC oscillator or the 32KHz crystal oscillator. Any tapping of the prescaler can be selected as clock source for the RTC, enabling both high resolution and long timeouts. The prescaler cannot be written directly, but can be cleared by the user. The RTC can generate an interrupt when the counter wraps around the value stored in the top register (TOP), producing accurate periodic interrupts. 9.3 Block Diagram Real Time Counter Block Diagram Figure 9-1. CTRL CLK32 32 kHz RC OSC 1 TOP EN PSEL 16-bit Prescaler 0 32-bit counter TOPI IRQ VAL 9.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 72 32072A-AVR32-03/09 AT32UC3A3 9.4.1 Power Management The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode. Clocks The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever this module is active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (fRC). The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be enabled before use. Please refer to the Power Manager chapter for details. The clock for the RTC bus interface (CLK_RTC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the RTC before disabling the clock, to avoid freezing the RTC in an undefined state. 9.4.3 Interrupts The RTC interrupt request line is connected to the interrupt controller. Using the RTC interrupt requires the interrupt controller to be programmed first. 9.4.4 Debug Operation The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 9.4.2 9.5 9.5.1 9.5.1.1 Functional Description RTC Operation Source clock The RTC is enabled by writing a one to the Enable bit in the Control Register (CTRL.EN). The 16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or written, but it can be reset by writing a one to the Prescaler Clear bit in CTRL register (CTRL.PCLR). The 32KHz Oscillator Select bit in CTRL register (CTRL.CLK32) selects either the RC oscillator or the 32KHz oscillator as clock source for the prescaler. The Prescale Select field in CTRL register (CTRL.PSEL) selects the prescaler tapping, selecting the source clock for the RTC: f RTC = 2 - ( PSEL + 1 ) x ( f RC or 32 KHz ) 9.5.1.2 Counter operation When enabled, the RTC will increment until it reaches TOP, and then wraps to 0x0. The status bit TOPI in Interrupt Status Register (ISR) is set to one when this occurs. From 0x0 the counter will count TOP+1 cycles of the source clock before it wraps back to 0x0. The RTC count value can be read from or written to the Value register (VAL). Due to synchronization, continuous reading of the VAL register with the lowest prescaler setting will skip every other value. 73 32072A-AVR32-03/09 AT32UC3A3 9.5.1.3 RTC interrupt The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Register (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the interrupt is enabled. If enabled, an interrupt will be generated if the TOPI bit in the Interrupt Status Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in the Interrupt Clear Register (ICR.TOPI). The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes. 9.5.1.4 RTC wakeup The RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI bit is set. In this case, the CPU will continue executing from the instruction following the sleep instruction. This direct RTC wake-up is enabled by writing a one to the Wake Enable bit in the CTRL register (CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction will have no effect. The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be configured independently of the RTC interrupt. 9.5.1.5 Busy bit Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until the CTRL.BUSY bit goes low again. 74 32072A-AVR32-03/09 AT32UC3A3 9.6 User Interface RTC Register Memory Map Register Control Register Value Register Top Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Register Name CTRL VAL TOP IER IDR IMR ISR ICR Access Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Write-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 9-1. Offset 0x00 0x04 0x08 0x10 0x14 0x18 0x1C 0x20 75 32072A-AVR32-03/09 AT32UC3A3 9.6.1 Name: Control Register CTRL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 BUSY 27 19 11 26 18 10 PSEL 25 17 9 24 16 CLKEN 8 3 CLK32 2 WAKEN 1 PCLR 0 EN * CLKEN: Clock Enable 1: The clock is enabled. 0: The clock is disabled. PSEL: Prescale Select Selects prescaler bit PSEL as source clock for the RTC. BUSY: RTC Busy This bit is set when the RTC is busy and will discard writes to TOP, VAL, and CTRL. This bit is cleared when the RTC accepts writes to TOP, VAL, and CTRL. CLK32: 32 KHz Oscillator Select 1: The RTC uses the 32 KHz oscillator as clock source. 0: The RTC uses the RC oscillator as clock source. WAKEN: Wakeup Enable 1: The RTC wakes up the CPU from sleep modes. 0: The RTC does not wake up the CPU from sleep modes. PCLR: Prescaler Clear Writing a one to this bit clears the prescaler. Writing a zero to this bit has no effect. This bit always reads as zero. EN: Enable 1: The RTC is enabled. 0: The RTC is disabled. * * * * * * 76 32072A-AVR32-03/09 AT32UC3A3 9.6.2 Name: Value Register VAL Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 VAL[31:24] 27 26 25 24 23 22 21 20 VAL[23:16] 19 18 17 16 15 14 13 12 VAL[15:8] 11 10 9 8 7 6 5 4 VAL[7:0] 3 2 1 0 * VAL[31:0]: RTC Value This value is incremented on every rising edge of the source clock. 77 32072A-AVR32-03/09 AT32UC3A3 9.6.3 Name: Top Register TOP Read/Write 0x08 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 VAL[31:24] 27 26 25 24 23 22 21 20 VAL[23:16] 19 18 17 16 15 14 13 12 VAL[15:8] 11 10 9 8 7 6 5 4 VAL[7:0] 3 2 1 0 * VAL[31:0]: RTC Top Value VAL wraps at this value. 78 32072A-AVR32-03/09 AT32UC3A3 9.6.4 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 79 32072A-AVR32-03/09 AT32UC3A3 9.6.5 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 80 32072A-AVR32-03/09 AT32UC3A3 9.6.6 Name: Interrupt Mask Register IMR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 TOPI 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 81 32072A-AVR32-03/09 AT32UC3A3 9.6.7 Name: Interrupt Status Register ISR Read-only 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 TOPI * TOPI: Top Interrupt This bit is set when VAL has wrapped at its top value. This bit is cleared when the corresponding bit in ICR is written to one. 82 32072A-AVR32-03/09 AT32UC3A3 9.6.8 Name: Interrupt Clear Register ICR Write-only 0x20 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 TOPI Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 83 32072A-AVR32-03/09 AT32UC3A3 10. Watchdog Timer (WDT) Rev: 2.3.1.1 10.1 Features * Watchdog timer counter with 32-bit prescaler * Clocked from the system RC oscillator (RCSYS) 10.2 Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked from the RC oscillator. The watchdog timer must be periodically reset by software within the time-out period, otherwise, the device is reset and starts executing from the boot vector. This allows the device to recover from a condition that has caused the system to be unstable. 10.3 Block Diagram Figure 10-1. WDT Block Diagram CLR RCSYS 32-bit Prescaler Watchdog Detector Watchdog Reset EN CTRL 10.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes, and it is not possible to enter Static mode. Clocks The WDT can use the system RC oscillator (RCSYS) as clock source. This oscillator is always enabled whenever these modules are active. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator (fRC). 10.4.2 10.4.3 Debug Operation The WDT prescaler is frozen during debug operation, unless the On-Chip Debug (OCD) system keeps peripherals running in debug operation. 84 32072A-AVR32-03/09 AT32UC3A3 10.5 Functional Description The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field (PSEL) in the CTRL register selects the watchdog time-out period: TWDT = 2(PSEL+1) / fRC The next time-out period will begin as soon as the watchdog reset has occurred and count down during the reset sequence. Care must be taken when selecting the PSEL field value so that the time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset the chip before any code has been run. To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause the write operation to be ignored, and the CTRL register value will not change. The Clear register (CLR) must be written with any value with regular intervals shorter than the watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start executing from the boot vector. When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result in entering Shutdown mode, leaving the WDT operational. 85 32072A-AVR32-03/09 AT32UC3A3 10.6 User Interface WDT Register Memory Map Register Control Register Clear Register Register Name CTRL CLR Access Read/Write Write-only Reset 0x00000000 0x00000000 Table 10-1. Offset 0x00 0x04 86 32072A-AVR32-03/09 AT32UC3A3 10.6.1 Name: Control Register CTRL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 15 7 - 22 14 6 - 21 13 5 - 20 12 19 11 18 10 PSEL 17 9 16 8 4 - 3 - 2 - 1 - 0 EN * KEY: Write protection key This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero. * PSEL: Prescale Select PSEL is used as watchdog timeout period. * EN: WDT Enable 1: WDT is enabled. 0: WDT is disabled. 87 32072A-AVR32-03/09 AT32UC3A3 10.6.2 Name: Clear Register CLR Write-only 0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 CLR[31:24] 27 26 25 24 23 22 21 20 CLR[23:16] 19 18 17 16 15 14 13 12 CLR[15:8] 11 10 9 8 7 6 5 4 CLR[7:0] 3 2 1 0 * CLR: Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a watchdog reset. This field always reads as zero. 88 32072A-AVR32-03/09 AT32UC3A3 11. Interrupt Controller (INTC) Rev: 1.0.1.4 11.1 Features * Autovectored low latency interrupt service with programmable priority - 4 priority levels for regular, maskable interrupts - One Non-Maskable Interrupt * Up to 64 groups of interrupts with up to 32 interrupt requests in each 11.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI). The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register (IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and an autovector to each group, and the IRRs are used to identify the active interrupt request within each group. If a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the group that has a pending interrupt of the corresponding priority level. If several groups have an pending interrupt of the same level, the group with the lowest number takes priority. 11.3 Block Diagram Figure 11-1 on page 89 gives an overview of the INTC. The grey boxes represent registers that can be accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure. Figure 11-1. Block Diagram of the Interrupt Controller Interrupt Controller NMIREQ CPU SREG Masks I[3-0]M GM Masks OR IRRn IREQ63 IREQ34 IREQ33 IREQ32 GrpReqN ValReqN IPRn INT_level, offset INTLEVEL Request Masking OR IRR1 GrpReq1 Prioritizer ValReq1 IPR1 INT_level, offset AUTOVECTOR IREQ31 IREQ2 IREQ1 IREQ0 OR IRR0 IRR Registers GrpReq0 ValReq0 IPR0 INT_level, offset IPR Registers ICR Registers 89 32072A-AVR32-03/09 AT32UC3A3 11.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 11.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the INTC, the INTC will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. 11.4.3 Debug Operation When an external debugger forces the CPU into debug mode, the INTC continues normal operation. 11.4.2 11.5 Functional Description All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that is active. If several IREQs within the same group is active, the interrupt service routine must prioritize between them. All of the input lines in each group are logically-ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group. The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt level mask bit is set. The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically gets the highest priority of any pending interrupt. If several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the highest number is selected. The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are transmitted to the CPU for interrupt handling and context switching. The CPU doesn't need to know which interrupt is requesting handling, but only the level and the offset of the handler address. The IRR registers contain the interrupt request lines of the groups and can be read via user interface registers for checking which interrupts of the group are actually active. 11.5.1 Non-Maskable Interrupts A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vector address defined by the AVR32 architecture, so AUTOVECTOR is undefined when INTLEVEL indicates that an NMI is pending. 90 32072A-AVR32-03/09 AT32UC3A3 11.5.2 CPU Response When the CPU receives an interrupt request it checks if any other exceptions are pending. If no exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt handling, the corresponding interrupt mask bit is set automatically for this and lower levels in status register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M, I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking bits I1M and I0M are set in status register. The handler address is calculated by adding AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The CPU will then jump to the calculated address and start executing the interrupt handler. Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be passed through the interrupt controller. Setting of the same level mask bit prevents also multiple requests of the same interrupt to happen. It is the responsibility of the handler software to clear the interrupt request that caused the interrupt before returning from the interrupt handler. If the conditions that caused the interrupt are not cleared, the interrupt request remains active. 11.5.3 Clearing an Interrupt Request Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal. The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 11.6 . User Interface INTC Register Memory Map Register Interrupt Priority Register 0 Interrupt Priority Register 1 ... Interrupt Priority Register 63 Interrupt Request Register 0 Interrupt Request Register 1 ... Interrupt Request Register 63 Interrupt Cause Register 3 Interrupt Cause Register 2 Interrupt Cause Register 1 Interrupt Cause Register 0 Register Name IPR0 IPR1 ... IPR63 IRR0 IRR1 ... IRR63 ICR3 ICR2 ICR1 ICR0 Access Read/Write Read/Write ... Read/Write Read-only Read-only ... Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 ... 0x00000000 N/A N/A ... N/A N/A N/A N/A N/A Table 11-1. Offset 0x000 0x004 ... 0x0FC 0x100 0x104 ... 0x1FC 0x200 0x204 0x208 0x20C 91 32072A-AVR32-03/09 AT32UC3A3 11.6.1 Interrupt Priority Registers Register Name: IPR0...IPR63 Access Type: Offset: Reset Value: Read/Write 0x000 - 0x0FC 0x00000000 29 21 13 28 20 12 27 19 26 18 25 17 9 24 16 8 31 30 INTLEVEL[1:0] 23 15 7 22 14 6 11 10 AUTOVECTOR[13:8] 2 5 4 3 AUTOVECTOR[7:0] 1 0 * INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt handler of the corresponding group: 00: INT0. 01: INT1. 10: INT2. 11: INT3. * AUTOVECTOR: Autovector Address Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment. 92 32072A-AVR32-03/09 AT32UC3A3 11.6.2 Name: Interrupt Request Registers IRR0...IRR63 Read-only 0x0FF - 0x1FC N/A 30 IRR[32*x+30] 22 IRR[32*x+22] 14 IRR[32*x+14] 6 IRR[32*x+6] 29 IRR[32*x+29] 21 IRR[32*x+21] 13 IRR[32*x+13] 5 IRR[32*x+5] 28 IRR[32*x+28] 20 IRR[32*x+20] 12 IRR[32*x+12] 4 IRR[32*x+4] 27 IRR[32*x+27] 19 IRR[32*x+19] 11 IRR[32*x+11] 3 IRR[32*x+3] 26 IRR[32*x+26] 18 IRR[32*x+18] 10 IRR[32*x+10] 2 IRR[32*x+2] 25 IRR[32*x+25] 17 IRR[32*x+17] 9 IRR[32*x+9] 1 IRR[32*x+1] 24 IRR[32*x+24] 16 IRR[32*x+16] 8 IRR[32*x+8] 0 IRR[32*x+0] Access Type: Offset: Reset Value: 31 IRR[32*x+31] 23 IRR[32*x+23] 15 IRR[32*x+15] 7 IRR[32*x+7] * IRR: Interrupt Request line This bit is cleared when no interrupt request is pending on this input request line. This bit is set when an interrupt request is pending on this input request line. The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only. 93 32072A-AVR32-03/09 AT32UC3A3 11.6.3 Interrupt Cause Registers Register Name: ICR0...ICR3 Access Type: Offset: Reset Value: 31 23 15 7 - Read-only 0x200 - 0x20C N/A 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 CAUSE 26 18 10 2 25 17 9 1 24 16 8 0 * CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending. 94 32072A-AVR32-03/09 AT32UC3A3 0.1 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantics of the different interrupt requests. The interrupt request signals are connected to the INTC as follows. Table 0-1. Group 0 Interrupt Request Signal Map Line 0 0 1 2 3 4 Module Stiletto CPU with optional MPU and optional OCD External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller Real Time Counter Power Manager General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller Signal SYSBLOCK COMPARE EIC 0 EIC 1 EIC 2 EIC 3 EIC 4 EIC 5 EIC 6 EIC 7 RTC PM GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 1 5 6 7 8 9 0 1 2 3 4 5 6 2 7 8 9 10 11 12 13 95 32072A-AVR32-03/09 AT32UC3A3 Table 0-1. Interrupt Request Signal Map 0 1 2 3 3 4 5 6 7 4 5 6 7 8 9 10 11 12 13 0 0 0 0 0 0 0 0 0 0 0 14 1 2 15 0 0 16 1 2 17 18 19 20 21 0 0 0 0 0 Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Flash Controller Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Serial Peripheral Interface Serial Peripheral Interface Two-wire Master Interface Two-wire Master Interface Synchronous Serial Controller Timer/Counter Timer/Counter Timer/Counter Analog to Digital Converter Timer/Counter Timer/Counter Timer/Counter USB 2.0 OTG Interface SDRAM Controller Audio Bitstream DAC Mulitmedia Card Interface Advanced Encryption Standard PDCA 4 PDCA 5 PDCA 6 PDCA 7 FLASHC USART0 USART1 USART2 USART3 SPI0 SPI1 TWIM0 TWIM1 SSC TC00 TC01 TC02 ADC TC10 TC11 TC12 USBB SDRAMC DAC MCI AES Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller PDCA 0 PDCA 1 PDCA 2 PDCA 3 96 32072A-AVR32-03/09 AT32UC3A3 Table 0-1. Interrupt Request Signal Map 0 1 22 2 3 4 26 27 28 29 0 0 0 0 DMA Controller DMA Controller DMA Controller DMA Controller DMA Controller Memory Stick Interface Two-wire Slave Interface Two-wire Slave Interface Error code corrector Hamming and Reed Solomon DMACA BLOCK DMACA DSTT DMACA ERR DMACA SRCT DMACA TFR MSI TWIS0 TWIS1 RS4 97 32072A-AVR32-03/09 AT32UC3A3 98 32072A-AVR32-03/09 AT32UC3A3 12. External Interrupt Controller (EIC) Rev: 2.3.1.0 12.1 Features * * * * * * * * Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Maskable NMI interrupt Keypad scan support 12.2 Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each external interrupt has its own interrupt request and can be individually masked. Each external interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can also be configured to be asynchronous in order to wake up the part from sleep modes where the CLK_SYNC clock has been disabled. A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode. The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode, code execution starts from the instruction following the sleep instruction. The External Interrupt Controller has support for keypad scanning for keypads laid out in rows and columns. Columns are driven by a separate set of scanning outputs, while rows are sensed by the external interrupt lines. The pressed key will trigger an interrupt, which can be identified through the user registers of the module. 99 32072A-AVR32-03/09 AT32UC3A3 12.3 Block Diagram Figure 12-1. EIC Block Diagram LEVEL MODE EDGE ASYNC EN D IS P o la r it y c o n tro l A s y n c h ro n u s d e te c to r LEVEL MODE EDGE IC R CTRL IE R ID R E n a b le E X T IN T n NMI CTRL F IL T E R IN T n M ask IR Q n F ilt e r E d g e /L e v e l D e te c to r IS R IM R CLK_SYNC CLK_RCSYS W ake d e te c t E IC _ W A K E P r e s c a le r S h if t e r P IN SCANm PRESC EN SCAN 12.4 I/O Lines Description Table 12-1. Pin Name NMI EXTINTn SCANm I/O Lines Description Pin Description Non-Maskable Interrupt External Interrupt Type Input Input Output Keypad scan pin m 12.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) are multiplexed with I/O lines. To generate an external interrupt from an external source the source pin must be configured as an input pins by the I/O Controller. It is also possible to trigger the interrupt by driving these pins from registers in the I/O Controller, or another peripheral output connected to the same pin. 12.5.2 Power Management All interrupts are available in all sleep modes as long as the EIC module is powered. However, in sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous mode. 100 32072A-AVR32-03/09 AT32UC3A3 12.5.3 Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system RC oscillator is not running. This clock is referred to as CLK_SYNC. Refer to the Module Configuration section at the end of this chapter for details. The Keypad scan function operates on the system RC oscillator clock CLK_RCSYS. 12.5.4 Interrupts The external interrupt request lines are connected to the interrupt controller. Using the external interrupts requires the interrupt controller to be programmed first. Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed. 12.5.5 Debug Operation The EIC is frozen during debug operation, unless the OCD system keeps peripherals running during debug operation. 12.6 12.6.1 Functional Description External Interrupts The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set up by the CPU before the interrupts are enabled. Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt n has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts. If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn. If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a high level on EXTINTn. Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers, the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a one is written to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is disabled. Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external interrupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propa- 101 32072A-AVR32-03/09 AT32UC3A3 gate to the interrupt controller. However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR. 12.6.2 Synchronization and Filtering of External Interrupts In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The synchronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the interrupt controller by two cycles of CLK_SYNC, see Figure 12-2 on page 102 and Figure 12-3 on page 102 for examples (FILTER off). It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register. This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see Figure 12-2 on page 102 and Figure 12-3 on page 102 for examples (FILTER on). Figure 12-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 12-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 102 32072A-AVR32-03/09 AT32UC3A3 12.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 12.6.1 should be followed, accessing the NMI bit instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled by accessing the registers in the EIC. 12.6.4 Asynchronous Interrupts Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC register. This will route the interrupt signal through the asynchronous path of the module. All edge interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is configured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted as low level, and a one in EDGE.INTn will be interpreted as high level. EIC_WAKE will be set immediately after the source triggers the interrupt, while the corresponding bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of CLK_SYNC. Please refere to Figure 12-4 on page 103 for details. When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 12-4. Timing Diagram, Asynchronous Interrupts CLK_SYNC CLK_SYNC EXTINTn/NMI EXTINTn/NMI ISR.INTn: rising EDGE or high LEVEL EIC_WAKE: rising EDGE or high LEVEL ISR.INTn: rising EDGE or high LEVEL EIC_WAKE: rising EDGE or high LEVEL 12.6.5 Wakeup The external interrupts can be used to wake up the part from sleep modes. The wakeup can be interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next instruction after the sleep instruction. 103 32072A-AVR32-03/09 AT32UC3A3 12.6.6 Keypad scan support The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed. The rows should be connected to the external interrupt pins with pull-ups enabled in the I/O Controller. These external interrupts should be enabled as low level or falling edge interrupts. The columns should be connected to the available scan pins. The I/O Controller must be configured to let the required scan pins be controlled by the EIC. Unused external interrupt or scan pins can be left controlled by the I/O Controller or other peripherals. The Keypad Scan function is enabled by writing SCAN.EN to 1, which starts the keypad scan counter. The SCAN outputs are tri-stated, except SCAN[0], which is driven to zero. After 2(SCAN.PRESC+1) RC clock cycles this pattern is left shifted, so that SCAN[1] is driven to zero while the other outputs are tri-stated. This sequence repeats infinitely, wrapping from the most significant SCAN pin to SCAN[0]. When a key is pressed, the pulled-up row is driven to zero by the column, and an external interrupt triggers. The scanning stops, and the software can then identify the key pressed by the interrupt status register and the SCAN.PINS value. The scanning stops whenever there is an active interrupt request from the EIC to the CPU. When the CPU clears the interrupt flags, scanning resumes. 104 32072A-AVR32-03/09 AT32UC3A3 12.7 User Interface EIC Register Memory Map Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Mode Register Edge Register Level Register Filter Register Test Register Asynchronous Register Scan Register Enable Register Disable Register Control Register Register Name IER IDR IMR ISR ICR MODE EDGE LEVEL FILTER TEST ASYNC SCAN EN DIS CTRL Access Write-only Write-only Read-only Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 12-2. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x2C 0x030 0x034 0x038 105 32072A-AVR32-03/09 AT32UC3A3 12.7.1 Name: Interrupt Enable Register IER Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. * NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. 106 32072A-AVR32-03/09 AT32UC3A3 12.7.2 Name: Interrupt Disable Register IDR Write-only 0x004 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. * NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 107 32072A-AVR32-03/09 AT32UC3A3 12.7.3 Name: Interrupt Mask Register IMR Read-only 0x008 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is disabled. 1: The Non-Maskable Interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 108 32072A-AVR32-03/09 AT32UC3A3 12.7.4 Name: Interrupt Status Register ISR Read-only 0x00C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in ICR. * NMI: Non-Maskable Interrupt 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in ICR. 109 32072A-AVR32-03/09 AT32UC3A3 12.7.5 Name: Interrupt Clear Register ICR Write-only 0x010 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR. * NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR. 110 32072A-AVR32-03/09 AT32UC3A3 12.7.6 Name: Mode Register MODE Read/Write 0x014 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The external interrupt is edge triggered. 1: The external interrupt is level triggered. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is edge triggered. 1: The Non-Maskable Interrupt is level triggered. 111 32072A-AVR32-03/09 AT32UC3A3 12.7.7 Name: Edge Register EDGE Read/Write 0x018 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The external interrupt triggers on falling edge. 1: The external interrupt triggers on rising edge. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt triggers on falling edge. 1: The Non-Maskable Interrupt triggers on rising edge. 112 32072A-AVR32-03/09 AT32UC3A3 12.7.8 Name: Level Register LEVEL Read/Write 0x01C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The external interrupt triggers on low level. 1: The external interrupt triggers on high level. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt triggers on low level. 1: The Non-Maskable Interrupt triggers on high level. 113 32072A-AVR32-03/09 AT32UC3A3 12.7.9 Name: Access Type: Offset: Reset Value: Filter Register FILTER Read/Write 0x020 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The external interrupt is not filtered. 1: The external interrupt is filtered. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is not filtered. 1: The Non-Maskable Interrupt is filtered. 114 32072A-AVR32-03/09 AT32UC3A3 12.7.10 Name: Access Type: Offset: Reset Value: Test Register TEST Read/Write 0x024 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * TESTEN: Test Enable 0: This bit disables external interrupt test mode. 1: This bit enables external interrupt test mode. * INTn: External Interrupt n If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored. * NMI: Non-Maskable Interrupt If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored. 115 32072A-AVR32-03/09 AT32UC3A3 12.7.11 Name: Access Type: Offset: Reset Value: Asynchronous Register ASYNC Read/Write 0x028 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The external interrupt is synchronized to CLK_SYNC. 1: The external interrupt is asynchronous. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is synchronized to CLK_SYNC 1: The Non-Maskable Interrupt is asynchronous. 116 32072A-AVR32-03/09 AT32UC3A3 12.7.12 Name: Scan Register SCAN Read/Write 0x2C 0x0000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 25 PIN[2:0] 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 11 10 PRESC[4:0] 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 EN * EN 0: Keypad scanning is disabled 1: Keypad scanning is enabled * PRESC Prescale select for the keypad scan rate: Scan rate = 2(SCAN:PRESC+1) TRC The RC clock period can be found in the Electrical Characteristics section. * PIN The index of the currently active scan pin. Writing to this bitfield has no effect. 117 32072A-AVR32-03/09 AT32UC3A3 12.7.13 Name: Access Type: Offset: Reset Value: Enable Register EN Write-only 0x030 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will enable the corresponding external interrupt. * NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will enable the Non-Maskable Interrupt. 118 32072A-AVR32-03/09 AT32UC3A3 12.7.14 Name: Access Type: Offset: Reset Value: Disable Register DIS Write-only 0x034 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will disable the corresponding external interrupt. * NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will disable the Non-Maskable Interrupt. 119 32072A-AVR32-03/09 AT32UC3A3 12.7.15 Name: Access Type: Offset: Reset Value: Control Register CTRL Read-only 0x038 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NMI 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 INT0 * INTn: External Interrupt n 0: The corresponding external interrupt is disabled. 1: The corresponding external interrupt is enabled. * NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is disabled. 1: The Non-Maskable Interrupt is enabled. 120 32072A-AVR32-03/09 AT32UC3A3 13. Flash Controller (FLASHC) Rev: 2.1.0.4 13.1 Features * Controls flash block with dual read ports allowing staggered reads. * Supports 0 and 1 wait state bus access. * Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle. * 32-bit HSB interface for reads from flash array and writes to page buffer. * 32-bit PB interface for issuing commands to and configuration of the controller. * 16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16) pages. Regions can be individually protected or unprotected. Additional protection of the Boot Loader pages. Supports reads and writes of general-purpose NVM bits. Supports reads and writes of additional NVM pages. Supports device protection through a security bit. Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing flash and clearing security bit. * Interface to Power Manager for power-down of flash-blocks in sleep mode. * * * * * * * 13.2 Overview The flash controller (FLASHC) interfaces a flash block with the 32-bit internal High-Speed Bus (HSB). Performance for uncached systems with high clock-frequency and one wait state is increased by placing words with sequential addresses in alternating flash subblocks. Having one read interface per subblock allows them to be read in parallel. While data from one flash subblock is being output on the bus, the sequential address is being read from the other flash subblock and will be ready in the next clock cycle. The controller also manages the programming, erasing, locking and unlocking sequences with dedicated commands. 13.3 13.3.1 Product dependencies Power Manager The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB) and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power manager. Bot h clocks are turned on by default, but the user has t o ensure that CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that CLK_FLASHC_PB is not turned off before accessing the FLASHC configuration and control registers. Interrupt Controller The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using FLASHC interrupts requires the interrupt controller to be programmed first. 13.3.2 121 32072A-AVR32-03/09 AT32UC3A3 13.4 13.4.1 Functional description Bus interfaces The FLASHC has two bus interfaces, one HSB interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control to and reading status from the controller. 13.4.2 Memory organization To maximize performance for high clock-frequency systems, FLASHC interfaces to a flash block with two read ports. The flash block has several parameters, given by the design of the flash block. Refer to the "Memories" chapter for the device-specific values of the parameters. * p pages (FLASH_P) * w words in each page and in the page buffer (FLASH_W) * pw words in total (FLASH_PW) * f general-purpose fuse bits (FLASH_F) * 1 security fuse bit * 1 User Page 13.4.3 User page The User page is an additional page, outside the regular flash array, that can be used to store various data, like calibration data and serial numbers. This page is not erased by regular chip erase. The User page can only be written and erased by proprietary commands. Read accesses to the User page is performed just as any other read access to the flash. The address map of the User page is given in Figure 13-1. 13.4.4 Read operations The FLASHC provides two different read modes: * 0 wait state (0ws) for clock frequencies < (access time of the flash plus the bus delay) * 1 wait state (1ws) for clock frequencies < (access time of the flash plus the bus delay)/2 Higher clock frequencies that would require more wait states are not supported by the flash controller. The programmer can select the wait states required by writing to the FWS field in the Flash Control Register (FCR). It is the responsibility of the programmer to select a number of wait states compatible with the clock frequency and timing characteristics of the flash block. In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle. In 1ws mode, both flash read ports are active. One read port reading the addressed word, and the other reading the next sequential word. If the clock frequency allows, the user should use 0ws mode, because this gives the lowest power consumption for low-frequency systems as only one flash read port is read. Using 1ws mode has a power/performance ratio approaching 0ws mode as the clock frequency approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the power, but also give twice the performance. 122 32072A-AVR32-03/09 AT32UC3A3 The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Figure 13-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table 13-1. Memory type Main array User User row addresses Start address, byte sized 0 2^23 = 8388608 Size pw words = 4pw bytes 128 words = 512 bytes Figure 13-1. Memory map for the Flash memories A ll a d d r e s s e s a r e w o r d a d d r e s s e s 2^21+128 2^21 U nused U ser page pw p w -1 0 F la s h w it h e x tra p a g e 13.4.5 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND'ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR). The QPR command is useful to check that a page is in an erased state. The QPR instruction is much faster than performing the erased-page check using a regular software subroutine. Write page buffer operations The internal memory area reserved for the embedded flash can also be written through a writeonly page buffer. The page buffer is addressed only by the address bits required to address w words (since the page buffer is word addressable) and thus wrap around within the internal memory area address space and appear to be repeated within it. When writing to the page buffer, the PAGEN field in the Flash Command register (FCMD) is updated with the page number corresponding to page address of the latest word written into the page buffer. 123 13.4.6 32072A-AVR32-03/09 Flash data array Unused AT32UC3A3 The page buffer is also used for writes to the User page. Write operations can be prevented by programming the Memory Protection Unit of the CPU. Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption. Page buffer write operations are performed with 4 wait states. Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing 0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer with the Clear Page Buffer command. The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. Example: Writing a word into word address 130 of a flash with 128 words in the page buffer. PAGEN will be updated with the value 1, and the word will be written into word 2 in the page buffer. 13.4.7 Writing words to a page that is not completely erased This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed. The procedure is as follows: 1. Clear page buffer 2. Write to the page buffer the result of the logical bitwise AND operation between the contents of the flash page and the new data to write. Only words that were in an erased state can be changed from the original page. 3. Write Page. 13.5 Flash commands The FLASHC offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. See chapter 13.8.2 for a complete list of commands. To run a command, the field FCMD.CMD has to be written with the command number. As soon as FCMD is written, the FRDY bit is automatically cleared. Once the current command is complete, the FRDY bit is automatically set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is activated. All flash commands except for Quick Page Read (QPR) will generate an interrupt request upon completion if FRDY is set. After a command has been written to FCMD, the programming algorithm should wait until the command has been executed before attempting to read instructions or data from the flash or writing to the page buffer, as the flash will be busy. The waiting can be performed either by polling the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as DMA controllers are performing endless burst transfers from the flash. Also, make sure that the CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will result in an access pattern with IDLE HSB cycles. 124 32072A-AVR32-03/09 AT32UC3A3 All the commands are protected by the same keyword, which has to be written in the eight highest bits of FCMD. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is set in FSR. This bit is automatically cleared by a read access to FSR. Writing a command to FCMD while another command is being executed has no effect on the flash memory; however, the PROGE bit is set in FSR. This bit is automatically cleared by a read access to FSR. If the current command writes or erases a page in a locked region, or a page protected by the BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE bit is set in FSR . This bit is automatically cleared by a read access to FSR. 13.5.1 Write/erase page operation Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the Erase Page command. The User page can be written and erased using the mechanisms described in this chapter. After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space of the flash. This address space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to this address space, and the BOOTPROT[2:0] fuses. Data to be written are stored in an internal buffer called page buffer. The page buffer contains w words. The page buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. Writing of 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption. Data must be written to the page buffer before the programming command is written to FCMD. The sequence is as follows: * Reset the page buffer with the Clear Page Buffer command. * Fill the page buffer with the desired contents, using only 32-bit access. * Programming starts as soon as the programming key and the programming command are written to the Flash Command Register. The FCMD.PAGEN field must contain the address of the page to write. PAGEN is automatically updated when writing to the page buffer, but can also be written to directly. The FRDY bit in FSR is automatically cleared when the page write operation starts. * When programming is completed, the bit FRDY in FSR is set. If an interrupt was enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is set. Two errors can be detected in FSR after a programming sequence: * Programming Error: A bad keyword and/or an invalid command have been written in FCMD. * Lock Error: The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start. 13.5.2 Erase All operation The entire memory is erased if the Erase All command (EA) is written to FCMD. Erase All erases all bits in the flash array. The User page is not erased. All flash memory locations, the generalpurpose fuse bits, and the security bit are erased (reset to 0xFF) after an Erase All. 125 32072A-AVR32-03/09 AT32UC3A3 The EA command also ensures that all volatile memories, such as register file and RAMs, are erased before the security bit is erased. Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are programmed with a region size of 0. Thus, if at least one region is locked, the bit LOCKE in FSR is set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt line rises. When the command is complete, the bit FRDY bit in FSR is set. If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash controller is set. Two errors can be detected in FSR after issuing the command: * Programming Error: A bad keyword and/or an invalid command have been written in FCMD. * Lock Error: At least one lock region to be erased is protected, or BOOTPROT is different from 0. The erase command has been refused and no page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding lock regions. 13.5.3 Region lock bits The flash block has p pages, and these pages are grouped into 16 lock regions, each region containing p/16 pages. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, the device may have some regions locked. These locked regions are reserved for a boot or default application. Locked regions can be unlocked to be erased and then programmed with another application or other data. To lock or unlock a region, the commands Lock Region Containing Page (LP) and Unlock Region Containing Page (UP) are provided. Writing one of these commands, together with the number of the page whose region should be locked/unlocked, performs the desired operation. One error can be detected in FSR after issuing the command: * Programming Error: A bad keyword and/or an invalid command have been written in FCMD. The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that lock bits can also be set/cleared using the commands for writing/erasing general-purpose fuse bits, see chapter 13.6. The general-purpose bit being in an erased (1) state means that the region is unlocked. The lowermost pages in the Flash can additionally be protected by the BOOTPROT fuses, see Section 13.6. 13.6 General-purpose fuse bits Each flash block has a number of general-purpose fuse bits that the application programmer can use freely. The fuse bits can be written and erased using dedicated commands, and read 126 32072A-AVR32-03/09 AT32UC3A3 through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 13-2. GeneralPurpose fuse number 15:0 General-purpose fuses with special functions Name LOCK Usage Region lock bits. External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared. The address range corresponding to external memories is device-specific, and not known to the flash controller. This fuse bit is simply routed out of the CPU or bus system, the flash controller does not treat this fuse in any special way, except that it can not be altered when the security bit is set. If the security bit is set, only an external JTAG Chip Erase can clear EPFL. No internal commands can alter EPFL if the security bit is set. When the fuse is erased (i.e. "1"), the CPU can execute instructions fetched from external memories. When the fuse is programmed (i.e. "0"), instructions can not be executed from external memories. Used to select one of eight different boot loader sizes. Pages included in the bootlegger area can not be erased or programmed except by a JTAG chip erase. BOOTPROT can only be changed when the security bit is cleared. If the security bit is set, only an external JTAG Chip Erase can clear BOOTPROT, and thereby allow the pages protected by BOOTPROT to be programmed. No internal commands can alter BOOTPROT or the pages protected by BOOTPROT if the security bit is set. 16 EPFL 19:17 BOOTPROT The BOOTPROT fuses protects the following address space for the Boot Loader: Table 13-3. BOOTPROT 7 6 5 4 3 2 1 0 Boot Loader area specified by BOOTPROT Pages protected by BOOTPROT None 0-1 0-3 0-7 0-15 0-31 0-63 0-127 Size of protected memory 0 1kByte 2kByte 4kByte 8kByte 16kByte 32kByte 64kByte 127 32072A-AVR32-03/09 AT32UC3A3 To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit. The PFB command is issued with a parameter in the PAGEN field: * PAGEN[2:0] - byte to write * PAGEN[10:3] - Fuse value to write All General-Purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) command. An EAGP command is not allowed if the flash is locked by the security bit. Two errors can be detected in FSR after issuing these commands: * Programming Error: A bad keyword and/or an invalid command have been written in FCMD. * Lock Error: A write or erase of any of the special-function fuse bits in Table 13-3 was attempted while the flash is locked by the security bit. The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see Section 13.5.3. 13.7 Security bit The security bit allows the entire chip to be locked from external JTAG or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through the JTAG Chip Erase command. Once the Security bit is set, the following Flash controller commands will be unavailable and return a lock error if attempted: * Write General-Purpose Fuse Bit (WGPB) to BOOTPROT or EPFL fuses * Erase General-Purpose Fuse Bit (EGPB) to BOOTPROT or EPFL fuses * Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2 * Erase All General-Purpose Fuses (EAGPF) One error can be detected in FSR after issuing the command: * Programming Error: A bad keyword and/or an invalid command have been written in FCMD. 128 32072A-AVR32-03/09 AT32UC3A3 13.8 User Interface FLASHC Register Memory Map Register Flash Control Register Flash Command Register Flash Status Register Flash General Purpose Fuse Register Hi Flash General Purpose Fuse Register Lo Name FCR FCMD FSR FGPFRHI FGPFRLO Access R/W R/W R/W R R Reset 0 0 0 (*) NA (*) NA (*) Table 13-4. Offset 0x0 0x4 0x8 0xc 0x10 (*) The value of the Lock bits is dependent of their programmed state. All other bits in FSR are 0. All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to. Any bits in these registers not mapped to a fuse read 0. 129 32072A-AVR32-03/09 AT32UC3A3 13.8.1 Flash Control Register Name: FCR Access Type: Read/Write Offset: 0x00 Reset value: 0x00000000 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 FWS 5 - 4 - 3 PROGE 2 LOCKE 1 - 0 FRDY * FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt. * LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt. 1: Lock Error generates an interrupt. * PROGE: Programming Error Interrupt Enable 0: Programming Error does not generate an interrupt. 1: Programming Error generates an interrupt. * FWS: Flash Wait State 0: The flash is read with 0 wait states. 1: The flash is read with 1 wait state. 130 32072A-AVR32-03/09 AT32UC3A3 13.8.2 Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to be set. 31 30 29 28 KEY 27 26 25 24 23 22 21 20 PAGEN [15:8] 19 18 17 16 15 14 13 12 PAGEN [7:0] 11 10 9 8 7 - 6 - 5 4 3 CMD 2 1 0 * CMD: Command This field defines the flash command. Issuing any unused command will cause the Programming Error bit to be set, and the corresponding interrupt to be requested if FCR.PROGE is set. Table 13-5. Command No operation Write Page Erase Page Set of commands Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic NOP WP EP CPB LP UP EA WGPB EGPB SSB PGPFB EAGPF QPR WUP EUP Clear Page Buffer Lock region containing given Page Unlock region containing given Page Erase All Write General-Purpose Fuse Bit Erase General-Purpose Fuse Bit Set Security Bit Program GP Fuse Byte Erase All GPFuses Quick Page Read Write User Page Erase User Page 131 32072A-AVR32-03/09 AT32UC3A3 Table 13-5. Command Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable Set of commands Value 15 16 17 Mnemonic QPRUP HSEN HSDIS * PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits representing valid page numbers can be written, all other bits in PAGEN are always 0. As an example, in a flash with 1024 pages (page 0 - page 1023), bits 15:10 will always be 0. Table 13-6. Command No operation Write Page Semantic of PAGEN field in different commands PAGEN description Not used The number of the page to write Not used Page number whose region should be locked Page number whose region should be unlocked Not used GPFUSE # GPFUSE # Not used WriteData[7:0], ByteAddress[2:0] Not used Page number Not used Not used Not used Not used Not used Clear Page Buffer Lock region containing given Page Unlock region containing given Page Erase All Write General-Purpose Fuse Bit Erase General-Purpose Fuse Bit Set Security Bit Program GP Fuse Byte Erase All GP Fuses Quick Page Read Write User Page Erase User Page Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable * KEY: Write protection key This field should be written with the value 0xA5 to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. This field always reads as 0. 132 32072A-AVR32-03/09 AT32UC3A3 13.8.3 Flash Status Register Name: FSR Access Type: Read/Write Offset: 0x08 Reset value: 0x00000000 31 LOCK15 30 LOCK14 29 LOCK13 28 LOCK12 27 LOCK11 26 LOCK10 25 LOCK9 24 LOCK8 23 LOCK7 22 LOCK6 21 LOCK5 20 LOCK4 19 LOCK3 18 LOCK2 17 LOCK1 16 LOCK0 15 14 FSZ 13 12 - 11 - 10 - 9 - 8 - 7 - 6 HSEN 5 QPRR 4 SECURITY 3 PROGE 2 LOCKE 1 - 0 FRDY * FRDY: Flash Ready Status 0: The flash controller is busy and the application must wait before running a new command. 1: The flash controller is ready to run a new command. * LOCKE: Lock Error Status Automatically cleared when FSR is read. 0: No programming of at least one locked lock region has happened since the last read of FSR. 1: Programming of at least one locked lock region has happened since the last read of FSR. * PROGE: Programming Error Status Automatically cleared when FSR is read. 0: No invalid commands and no bad keywords were written in FCMD. 1: An invalid command and/or a bad keyword was/were written in FCMD. * SECURITY: Security Bit Status 0: The security bit is inactive. 1: The security bit is active. * QPRR: Quick Page Read Result 0: The result is zero, i.e. the page is not erased. 1: The result is one, i.e. the page is erased. * HSEN: High Speed Mode Enable 0: High Speed Mode disabled. 1: High Speed Mode enabled. 133 32072A-AVR32-03/09 AT32UC3A3 * FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 13-7. FSZ 0 1 2 3 4 5 6 7 Flash size Flash Size 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 384 Kbytes 512 Kbytes 768 Kbytes 1024 Kbytes * LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked. 134 32072A-AVR32-03/09 AT32UC3A3 13.8.4 Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read Offset: 0x0C Reset value: N/A 31 GPF63 30 GPF62 29 GPF61 28 GPF60 27 GPF59 26 GPF58 25 GPF57 24 GPF56 23 GPF55 22 GPF54 21 GPF53 20 GPF52 19 GPF51 18 GPF50 17 GPF49 16 GPF48 15 GPF47 14 GPF46 13 GPF45 12 GPF44 11 GPF43 10 GPF42 9 GPF41 8 GPF40 7 GPF39 6 GPF38 5 GPF37 4 GPF36 3 GPF35 2 GPF34 1 GPF33 0 GPF32 This register is only used in systems with more than 32 GP fuses. * GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 135 32072A-AVR32-03/09 AT32UC3A3 13.8.5 Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read Offset: 0x10 Reset value: N/A 31 GPF31 30 GPF30 29 GPF29 28 GPF28 27 GPF27 26 GPF26 25 GPF25 24 GPF24 23 GPF23 22 GPF22 21 GPF21 20 GPF20 19 GPF19 18 GPF18 17 GPF17 16 GPF16 15 GPF15 14 GPF14 13 GPF13 12 GPF12 11 GPF11 10 GPF10 9 GPF09 8 GPF08 7 GPF07 6 GPF06 5 GPF05 4 GPF04 3 GPF03 2 GPF02 1 GPF01 0 GPF00 * GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 136 32072A-AVR32-03/09 AT32UC3A3 13.9 Fuses Settings The flash block contains 64 general purpose fuses. These 64 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO) and in the Flash General Purpose Fuse Register High (FGPFRHI) of the Flash Controller (FLASHC). Some of the FGPFRLO fuses have defined meanings outside the FLASHC and are described in this section. The general purpose fuses are set by a JTAG chip erase. 13.9.1 Flash General Purpose Fuse Register Low (FGPFRLO) FGPFRLO Register Description 30 GPF30 22 29 GPF29 21 20 28 BODEN 19 27 26 BODHYST 18 BOOTPROT 12 LOCK[15:8] 7 6 5 4 LOCK[7:0] * BODEN: Brown Out Detector Enable 3 2 1 0 11 10 9 25 24 Table 13-8. 31 GPF31 23 BODLEVEL[5:4] 17 16 EPFL 8 BODLEVEL[3:0] 15 14 13 Table 13-9. BODEN 0x0 0x1 0x2 0x3 BODEN Field Description Description Brown Out Detector (BOD) disabled BOD enabled, BOD reset enabled BOD enabled, BOD reset disabled BOD disabled * BODHYST: Brown Out Detector Hystersis 0: The BOD hysteresis is disabled 1: The BOD hysteresis is enabled * BODLEVEL: Brown Out Detector Trigger Level This controls the voltage trigger level for the Brown out detector. For value description refer to Electrical Characteristics chapter. If the BODLEVEL is set higher than VDDCORE and enabled by fuses, the part will be in constant reset. To recover from this situation, apply an external voltage on VDDCORE that is higher than the BOD Trigger level and disable the BOD. * LOCK, EPFL, BOOTPROT These are Flash controller fuses and are described in the FLASHC chapter. 137 32072A-AVR32-03/09 AT32UC3A3 13.9.2 Default Fuse Value The devices are shipped with the FGPFRLO register value: 0xFFF7FFFF: * GPF31 fuse set to 0b1. This fuse is used by the pre-programmed USB bootloader. * GPF30 fuse set to 0b1. This fuse is used by the pre-programmed USB bootloader. * GPF29 fuse set to 0b1. * BODEN fuses set to 0b11. BOD is disabled. * BODHYST fuse set to 0b1. The BOD hystersis is enabled. * BODLEVEL fuses set to 0b111111. This is the minimum voltage trigger level for BOD. * BOOTPROT fuses set to 0b011. The bootloader protected size is 8KBytes. * EPFL fuse set to 0b1. External privileged fetch is not locked. * LOCK fuses set to 0b1111111111111111. No region locked. See also the AT32UC3A3 Bootloader user guide document. After the JTAG chip erase command, the FGPFRLO register value is 0xFFFFFFFF. 13.10 Module configuration The specific configuration for the FLASHC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 13-10. Module Configuration Feature Flash size Number of pages Page size FLASH 256Kbytes 512 512 bytes Table 13-11. Module Clock Name Module name FLASHC Clock name CLK_FLASHC_HSB Clock name CLK_FLASHC_PB 138 32072A-AVR32-03/09 AT32UC3A3 14. HSB Bus Matrix (HMATRIX) Rev: 2.3.0.2 14.1 Features * * * * * * * User Interface on peripheral bus Configurable Number of Masters (Up to sixteen) Configurable Number of Slaves (Up to sixteen) One Decoder for Each Master Three Different Memory Mappings for Each Master (Internal and External boot, Remap) One Remap Function for Each Master Programmable Arbitration for Each Slave - Round-Robin - Fixed Priority Programmable Default Master for Each Slave - No Default Master - Last Accessed Default Master - Fixed Default Master One Cycle Latency for the First Access of a Burst Zero Cycle Latency for Default Master One Special Function Register for Each Slave (Not dedicated) * * * * 14.2 Overview The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16 Special Function Registers (SFR) that allow the Bus Matrix to support application specific features. 14.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 14.3.1 Clocks The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined state. 14.4 14.4.1 Functional Description Memory Mapping The Bus Matrix provides one decoder for every HSB Master Interface. The decoder offers each HSB Master several memory mappings. In fact, depending on the product, each memory area 139 32072A-AVR32-03/09 AT32UC3A3 may be assigned to several slaves. Booting at the same address while using different HSB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides Master Remap Control Register (MRCR) that performs remap action for every master independently. 14.4.2 Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. 14.4.2.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. 14.4.2.2 Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. 14.4.2.3 Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 14.4.3 Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per HSB slave is provided, thus arbitrating each slave differently. The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for each slave: 1. Round-Robin Arbitration (default) 2. Fixed Priority Arbitration This choice is made via the field ARBT of the Slave Configuration Registers (SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. 140 32072A-AVR32-03/09 AT32UC3A3 When a re-arbitration must be done, specific conditions apply. See Section 14.4.3.1 "Arbitration Rules" on page 141. 14.4.3.1 Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section "*" on page 141. 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See Section "*" on page 141. * Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2. One beat bursts: Predicted end of burst is generated at each single transfer inside the INCP transfer. 3. Four beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR transfer. 4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer. 5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MCFG). * Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer. 141 32072A-AVR32-03/09 AT32UC3A3 14.4.3.2 Round-Robin Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner. There are three round-robin algorithms implemented: 1. Round-Robin arbitration without default master 2. Round-Robin arbitration with last default master 3. Round-Robin arbitration with fixed default master * Round-Robin Arbitration without Default Master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. * Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. * Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses. 14.4.3.3 Fixed Priority Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master requests are active at the same time, the master with the highest priority number is serviced first. If two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (PRAS and PRBS). 14.4.4 Slave and Master assignation The index number assigned to Bus Matrix slaves and masters are described in Memories chapter. 142 32072A-AVR32-03/09 AT32UC3A3 14.5 User Interface HMATRICX Register Memory Map Register Master Configuration Register 0 Master Configuration Register 1 Master Configuration Register 2 Master Configuration Register 3 Master Configuration Register 4 Master Configuration Register 5 Master Configuration Register 6 Master Configuration Register 7 Master Configuration Register 8 Master Configuration Register 9 Master Configuration Register 10 Master Configuration Register 11 Master Configuration Register 12 Master Configuration Register 13 Master Configuration Register 14 Master Configuration Register 15 Slave Configuration Register 0 Slave Configuration Register 1 Slave Configuration Register 2 Slave Configuration Register 3 Slave Configuration Register 4 Slave Configuration Register 5 Slave Configuration Register 6 Slave Configuration Register 7 Slave Configuration Register 8 Slave Configuration Register 9 Slave Configuration Register 10 Slave Configuration Register 11 Slave Configuration Register 12 Slave Configuration Register 13 Slave Configuration Register 14 Slave Configuration Register 15 Priority Register A for Slave 0 Priority Register B for Slave 0 Priority Register A for Slave 1 Name MCFG0 MCFG1 MCFG2 MCFG3 MCFG4 MCFG5 MCFG6 MCFG7 MCFG8 MCFG9 MCFG10 MCFG11 MCFG12 MCFG13 MCFG14 MCFG15 SCFG0 SCFG1 SCFG2 SCFG3 SCFG4 SCFG5 SCFG6 SCFG7 SCFG8 SCFG9 SCFG10 SCFG11 SCFG12 SCFG13 SCFG14 SCFG15 PRAS0 PRBS0 PRAS1 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000000 0x00000000 0x00000000 Table 14-1. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 143 32072A-AVR32-03/09 AT32UC3A3 Table 14-1. Offset 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 HMATRICX Register Memory Map (Continued) Register Priority Register B for Slave 1 Priority Register A for Slave 2 Priority Register B for Slave 2 Priority Register A for Slave 3 Priority Register B for Slave 3 Priority Register A for Slave 4 Priority Register B for Slave 4 Priority Register A for Slave 5 Priority Register B for Slave 5 Priority Register A for Slave 6 Priority Register B for Slave 6 Priority Register A for Slave 7 Priority Register B for Slave 7 Priority Register A for Slave 8 Priority Register B for Slave 8 Priority Register A for Slave 9 Priority Register B for Slave 9 Priority Register A for Slave 10 Priority Register B for Slave 10 Priority Register A for Slave 11 Priority Register B for Slave 11 Priority Register A for Slave 12 Priority Register B for Slave 12 Priority Register A for Slave 13 Priority Register B for Slave 13 Priority Register A for Slave 14 Priority Register B for Slave 14 Priority Register A for Slave 15 Priority Register B for Slave 15 Master Remap Control Register Special Function Register 0 Special Function Register 1 Special Function Register 2 Special Function Register 3 Special Function Register 4 Special Function Register 5 Name PRBS1 PRAS2 PRBS2 PRAS3 PRBS3 PRAS4 PRBS4 PRAS5 PRBS5 PRAS6 PRBS6 PRAS7 PRBS7 PRAS8 PRBS8 PRAS9 PRBS9 PRAS10 PRBS10 PRAS11 PRBS11 PRAS12 PRBS12 PRAS13 PRBS13 PRAS14 PRBS14 PRAS15 PRBS15 MRCR SFR0 SFR1 SFR2 SFR3 SFR4 SFR5 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - - - - - - 144 32072A-AVR32-03/09 AT32UC3A3 Table 14-1. Offset 0x0128 0x012C 0x0130 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C HMATRICX Register Memory Map (Continued) Register Special Function Register 6 Special Function Register 7 Special Function Register 8 Special Function Register 9 Special Function Register 10 Special Function Register 11 Special Function Register 12 Special Function Register 13 Special Function Register 14 Special Function Register 15 Name SFR6 SFR7 SFR8 SFR9 SFR10 SFR11 SFR12 SFR13 SFR14 SFR15 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value - - - - - - - - - - 145 32072A-AVR32-03/09 AT32UC3A3 14.5.1 Name: Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 - Master Configuration Registers MCFG0...MCFG15 Read/Write 0x00 - 0x3C 0x00000002 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 ULBT 24 - 16 - 8 - 0 * ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst. 2: Four Beat Burst The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. 3: Eight Beat Burst The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. 4: Sixteen Beat Burst The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. 146 32072A-AVR32-03/09 AT32UC3A3 14.5.2 Name: Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 Slave Configuration Registers SCFG0...SCFG15 Read/Write 0x40 - 0x7C 0x00000010 30 - 22 - 14 - 6 13 - 5 29 - 21 28 - 20 27 - 19 26 - 18 25 - 17 24 ARBT 16 FIXED_DEFMSTR 12 - 4 SLOT_CYCLE 11 - 3 10 - 2 DEFMSTR_TYPE 9 - 1 8 - 0 * ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration * FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. * DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one cycle latency when the fixed master tries to access the slave again. * SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave. This limit has been placed to avoid locking a very slow slave when very long bursts are used. This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. 147 32072A-AVR32-03/09 AT32UC3A3 14.5.3 Bus Matrix Priority Registers A For Slaves PRAS0...PRAS15 Read/Write 0x00000000 30 M7PR 23 22 M5PR 15 14 M3PR 7 6 M1PR 5 4 3 2 M0PR 13 12 11 10 M2PR 1 0 21 20 19 18 M4PR 9 8 29 28 27 26 M6PR 17 16 25 24 Register Name: Access Type: Offset: Reset Value: 31 * MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 148 32072A-AVR32-03/09 AT32UC3A3 14.5.4 Name: Access Type: Offset: Reset Value: 31 Priority Registers B For Slaves PRBS0...PRBS15 Read/Write 0x00000000 30 M15PR 23 22 M13PR 15 14 M11PR 7 6 M9PR 5 4 3 2 M8PR 13 12 11 10 M10PR 1 0 21 20 19 18 M12PR 9 8 29 28 27 26 M14PR 17 16 25 24 * MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 149 32072A-AVR32-03/09 AT32UC3A3 14.5.5 Name: Access Type: Offset: Reset Value: 31 - 23 - 15 RCB15 7 RCB7 Master Remap Control Register MRCR Read/Write 0x100 0x00000000 30 - 22 - 14 RCB14 6 RCB6 29 - 21 - 13 RCB13 5 RCB5 28 - 20 - 12 RCB12 4 RCB4 27 - 19 - 11 RCB11 3 RCB3 26 - 18 - 10 RCB10 2 RCB2 25 - 17 - 9 RCB9 1 RCB1 24 - 16 - 8 RCB8 0 RCB0 * RCB: Remap Command Bit for Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 150 32072A-AVR32-03/09 AT32UC3A3 14.5.6 Name: Access Type: Offset: Reset Value: 31 Special Function Registers SFR0...SFR15 Read/Write 0x110 - 0x115 30 29 28 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 * SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 151 32072A-AVR32-03/09 AT32UC3A3 14.6 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface. Table 14-2. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 High Speed Bus masters CPU Data CPU Instruction CPU SAB PDCA DMACA Master 1 DMACA Master 2 USBB DMA Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX SCFG4 register is associated with the Embedded CPU SRAM Slave Interface. Table 14-3. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 Slave 8 Slave 9 High Speed Bus slaves Internal Flash HSB-PB Bridge A HSB-PB Bridge B AES Embedded CPU SRAM USBB DPRAM EBI DMACA Slave Embedded System SRAM 0 Embedded System SRAM 1 152 32072A-AVR32-03/09 AT32UC3A3 Figure 14-1. HMATRIX Master / Slave Connections HMATRIX SLAVES Embedded System SRAM 0 8 Embedded System SRAM 1 9 Internal Flash USB DPRAM External Bus Interface 6 Embedded CPU SRAM HSB-PB Bridge A HSB-PB Bridge B 0 1 2 3 4 5 CPU Data 0 CPU Instruction 1 HMATRIX MASTERS CPU SAB 2 PDCA 3 DMACA Master 0 DMACA Master 1 USBB DMA 4 5 6 DMACA Slave 7 AES 153 32072A-AVR32-03/09 AT32UC3A3 15. External Bus Interface (EBI) Rev.: 1.7.0.0 15.1 Features * Optimized for application memory space support * Integrates three external memory controllers: - Static Memory Controller (SMC) - SDRAM Controller (SDRAMC) - Error Corrected Code (ECCHRS) controller * Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support - NAND Flash support: 8-bit as well as 16-bit devices are supported - CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. * Optimized external bus:16-bit data bus - Up to 24-bit Address Bus, Up to 8-Mbytes Addressable - Optimized pin multiplexing to reduce latencies on external memories * Up to 6 Chip Selects, Configurable Assignment: - Static Memory Controller on Chip Select 0 - SDRAM Controller or Static Memory Controller on Chip Select 1 - Static Memory Controller on Chip Select 2, Optional NAND Flash support - Static Memory Controller on Chip Select 3, Optional NAND Flash support - Static Memory Controller on Chip Select 4, Optional CompactFlashTM support - Static Memory Controller on Chip Select 5, Optional CompactFlashTM support 15.2 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an AVR32 device. The Static Memory, SDRAM and ECCHRS Controllers are all featured external memory controllers on the EBI. These external memory controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM. The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. Data transfers are performed through a 16-bit, an address bus of up to 23 bits, up to six chip select lines (NCS[5:0]), and several control pins that are generally multiplexed between the different external memory controllers. 154 32072A-AVR32-03/09 AT32UC3A3 15.3 Block Diagram Figure 15-1. EBI Block Diagram INTC SDRAMC_irq RS4_irq HMATRIX HSB SDRAM Controller EBI DATA[15:0] NWE1 NWE0 Static Memory Controller NRD NCS[5:0] ADDR[23:0] SDCS CAS ECCHRS Controller MUX Logic I/O Controller RAS SDA10 SFR registers NAND Flash SmartMedia Logic SDWE SDCK SDCKE NANDOE NANDWE Compact FLash Logic Address Decoders Chip Select Assignor CFRNW CFCE1 CFCE2 HSB-PB Bridge NWAIT Peripheral Bus 155 32072A-AVR32-03/09 AT32UC3A3 15.4 I/O Lines Description Table 15-1. EBI I/O Lines Description Alternate Name Active Level Pin Name Pin Description EBI common lines Type DATA[15:0] Data Bus SMC dedicated lines I/O ADDR[1] ADDR[12] ADDR[15] ADDR[23:18] NCS[0] NWAIT SMC Address Bus Line 1 SMC Address Bus Line 12 SMC Address Bus Line 15 SMC Address Bus Line [23:18] SMC Chip Select Line 0 SMC External Wait Signal SDRAMC dedicated lines Output Output Output Output Output Input Low Low SDCK SDCKE SDCS SDWE SDA10 RAS - CAS SDCS1 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line 1 SDRAM Write Enable SDRAM Address Bus Line 10 Row and Column Signal CompactFlash dedicated lines Output Output Output Output Output Output High Low Low Low Low CFCE1 CFCE2 CFRNW CompactFlash Chip Enable CompactFlash Read Not Write Signal NAND Flash/SmartMedia dedicated lines Output Output Low NANDOE NANDWE NAND Flash Output Enable NAND Flash Write Enable SMC/SDRAMC shared lines Output Output Low Low NCS[1] ADDR[0] ADDR[11:2] ADDR[14:13] ADDR[16] NCS[1] SDCS0 DQM0 ADDR[0]-NBS0 ADDR[9:0] ADDR[11:2] ADDR[9:0] ADDR[14:13] BA0 ADDR[16] SMC Chip Select Line 1 SDRAMC Chip Select Line 0 SDRAMC DQM1 SMC Address Bus Line 0 or Byte Select 1 SDRAMC Address Bus Lines [9:0] SMC Address Bus Lines [11:2] SDRAMC Address Bus Lines [12:11] SMC Address Bus Lines [14:13] SDRAMC Bank 0 SMC Address Bus Line 16 Output Output Output Output Output Low 156 32072A-AVR32-03/09 AT32UC3A3 Pin Name ADDR[17] Alternate Name BA1 ADDR[17] Pin Description SDRAMC Bank 1 SMCAddress Bus Line 17 SMC/CompactFlash shared lines NRD NWE0 NCS[4] NCS[5] NRD CFNOE NWE0-NWE CFNWE NCS[4] CFCS[0] NCS[5] CFCS[1] SMC Read Signal CompactFlash CFNOE SMC Write Enable10 or Write enable CompactFlash CFNWE SMC Chip Select Line 4 CompactFlash Chip Select Line 0 SMC Chip Select Line 5 CompactFlash Chip Select Line 1 Output Output Output Output Low Low Low Low Type Output Active Level SMC/NAND Flash/SmartMedia shared lines NCS[2] NCS[2] NANDCS[0] NCS[3] NANDCS[1] SMC Chip Select Line 2 NANDFlash/SmartMedia Chip Select Line 0 SMC Chip Select Line 3 NANDFlash/SmartMedia Chip Select Line 1 Output Low NCS[3] Output Low SDRAMC/SMC/CompactFlash shared lines NWE1 DQM1/ NWE1-NBS1/ CFNIORD SDRAMC DQM1 SMC Write Enable1 or Byte Select 1 CompactFlash CFNIORD Output 15.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 15.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O Controller lines. The user must first configure the I/O Controller to assign the EBI pins to their peripheral functions. 15.5.2 Power Management To prevent bus errors EBI operation must be terminated before entering sleep mode. Clocks A number of clocks can be selected as source for the EBI. The selected clock must be enabled by the Power Manager. The following clock sources are available: * CLK_EBI * CLK_SDRAMC * CLK_SMC 15.5.3 157 32072A-AVR32-03/09 AT32UC3A3 * CLK_ECCHRS Refer to Table 15-2 on page 158 to configure those clocks. Table 15-2. EBI Clocks Configuration Type of the Interfaced Device Clocks name Clocks type SDRAM X X X X X X SRAM, PROM, EPROM, EEPROM, Flash X NandFlash SmartMedia X CompactFlash X CLK_EBI CLK_SDRAMC CLK_SMC CLK_ECCHRS HSB PB PB PB 15.5.4 Interrupts The EBI interface has two interrupt lines connected to the Interrupt Controller: * SDRAMC_IRQ: Interrupt signal coming from the SDRAMC * RS4_IRQ: Interrupt signal coming from the ECCHRS Handling the EBI interrupt requires configuring the interrupt controller before configuring the EBI. 15.5.5 HMATRIX The EBI interface is connected to the HMATRIX Special Function Register 6 (SFR6). The user must first write to this HMATRIX.SFR6 to configure the EBI correctly. Table 15-3. SFR6 Bit Number [31:6] EBI Special Function Register Fields Description Bit name Reserved 0 = Chip Select 5 (NCS[5]) is connected to a Static Memory device. For each access to the NCS[5] memory space, all related pins act as SMC pins Description 5 CS5A 1 = Chip Select 5 (NCS[5]) is connected to a CompactFlash device. For each access to the NCS[5] memory space, all related pins act as CompactFlash pins 0 = Chip Select 4 (NCS[4]) is connected to a Static Memory device. For each access to the NCS[4] memory space, all related pins act as SMC pins 4 CS4A 1 = Chip Select 4 (NCS[4]) is connected to a CompactFlash device. For each access to the NCS[4] memory space, all related pins act as CompactFlash pins 0 = Chip Select 3 (NCS[3]) is connected to a Static Memory device. For each access to the NCS[3] memory space, all related pins act as SMC pins 3 CS3A 1 = Chip Select 3 (NCS[3]) is connected to a NandFlash or a SmartMedia device. For each access to the NCS[3] memory space, all related pins act as NandFlash or SmartMedia pins 158 32072A-AVR32-03/09 AT32UC3A3 Table 15-3. SFR6 Bit Number EBI Special Function Register Fields Description Bit name Description 0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each access to the NCS[2] memory space, all related pins act as SMC pins 2 CS2A 1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia device. For each access to the NCS[2] memory space, all related pins act as NandFlash or SmartMedia pins 0 = Chip Select 1 (NCS[1]) is connected to a Static Memory device. For each access to the NCS[1] memory space, all related pins act as SMC pins 1 = Chip Select 1 (NCS[1]) is connected to a SDRAM device. For each access to the NCS[1] memory space, all related pins act as SDRAM pins Reserved 1 CS1A 0 15.6 Functional Description The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: * The Static Memory Controller (SMC) * The SDRAM Controller (SDRAMC) * The ECCHRS Controller (ECCHRS) * A chip select assignment feature that assigns an HSB address space to the external devices * A multiplex controller circuit that shares the pins between the different memory controllers * Programmable CompactFlash support logic * Programmable SmartMedia and NAND Flash support logic 15.6.1 Bus Multiplexing The EBI offers a complete set of control signals that share the 16-bit data lines, the address lines of up to 24 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the other external memory controller accesses. 15.6.2 Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller Section. SDRAM Controller Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic. For information on the SDRAM Controller, refer to the SDRAM Section. 15.6.3 15.6.4 ECCHRS Controller For information on the ECCHRS Controller, refer to the ECCHRS Section. 159 32072A-AVR32-03/09 AT32UC3A3 15.6.5 CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space. Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value enables this logic. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS[4] and/or NCS[5]. All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOWR, _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 15.6.5.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS[4] and/or NCS[5] address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. The different modes are accessed through a specific memory mapping as illustrated on Figure 15-2 on page 160. ADDR[23:21] bits of the transfer address are used to select the desired mode as described in Table 15-4 on page 160. Figure 15-2. CompactFlash Memory Mapping True IDE Alternate Mode Space Offset 0x00E0 0000 True IDE Mode Space Offset 0x00C0 0000 CF Address Space Offset 0x0080 0000 Common Memory Mode Space Offset 0x0040 0000 Attribute Memory Mode Space Offset 0x0000 0000 Note: The ADDR[22] I/O line is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). I/O Mode Space Table 15-4. CompactFlash Mode Selection Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode Alternate True IDE Mode ADDR[23:21] 000 010 100 110 111 160 32072A-AVR32-03/09 AT32UC3A3 15.6.5.2 CFCE1 and CFCE2 signals To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the DATA[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address space must be written as shown in Table 15-5 on page 161 to enable the required access type. NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the SMC Section. Table 15-5. Mode Attribute Memory CFCE1 and CFCE2 Truth Table CFCE2 NBS1 CFCE1 NBS0 DBW 16 bits Comment Access to Even Byte on DATA[7:0] Access to Even Byte on DATA[7:0] Access to Odd Byte on DATA[15:8] Access to Odd Byte on DATA[7:0] Access to Even Byte on DATA[7:0] Access to Odd Byte on DATA[15:8] Access to Odd Byte on DATA[7:0] SMC Access Mode Byte Select NBS1 Common Memory 1 NBS0 16bits Byte Select 0 8 bits NBS1 I/O Mode 1 NBS0 16 bits Byte Select 0 8 bits True IDE Mode Access to Even Byte on DATA[7:0] Access to Odd Byte on DATA[7:0] Access to Even Byte on DATA[7:0] Access to Odd Byte on DATA[15:8] Task File 1 0 8 bits Data Register 1 0 16 bits Byte Select Alternate True IDE Mode Control Register Alternate Status Read Drive Address Standby Mode or Address Space is not assigned to CF 0 1 Don't Care 8 bits Access to Even Byte on DATA[7:0] Access to Odd Byte on DATA[7:0] Don't Care 0 1 1 1 - - - 161 32072A-AVR32-03/09 AT32UC3A3 15.6.5.3 Read/Write signals In I/O mode and True IDE mode, the CompactFlash logic drives the read command signals of the SMC on CFNIORD signal, while the CFNOE and CFNWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFNOE and CFNWE signals, while the CFNIORD is deactivated. Figure 15-3 on page 162 demonstrates a schematic representation of this logic. Attribute memory mode, common memory mode and I/O mode are supported by writing the address setup and hold time on the NCS[4] (and/or NCS[5]) chip select to the appropriate values. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the SMC Section. Figure 15-3. CompactFlash Read/Write Control Signals EBI SMC A23 1 1 0 1 A22 NRD NWR0/NWE 1 0 1 CFNIORD Compact Flash Logic 0 1 CFNOE CFNWE Table 15-6. CompactFlash Mode Selection CFNOE NRD_NOE 1 0 CFNWE NWR0_NWE 1 1 CFNIORD 1 NRD_NOE NRD_NOE Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode 15.6.5.4 Multiplexing of CompactFlash signals on EBI pins Table 15-7 on page 163 and Table on page 163 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 15-7 on page 163 are strictly dedicated to the CompactFlash interface as soon as the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits is/are written. These pins must not be used to drive any other memory devices. The EBI pins in Table 15-8 on page 163 remain shared between all memory areas when the corresponding CompactFlash interface is enabled (CS4A = 1 and/or CS5A = 1). 162 32072A-AVR32-03/09 AT32UC3A3 Table 15-7. Pins Dedicated CompactFlash Interface Multiplexing CompactFlash Signals CS4A = 1 CS5A = 1 CS4A = 0 NCS[4] CFCS1 NCS[5] EBI Signals CS5A = 0 NCS[4] NCS[5] CFCS0 Table 15-8. Shared CompactFlash Interface Multiplexing Access to CompactFlash Device Pins NRD NWE0 NWE1 CFRNW CompactFlash Signals CFNOE CFNWE CFNIORD CFRNW 15.6.5.5 Application example Figure 15-4 on page 164 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS[4] signal. The CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the SMC Section. 163 32072A-AVR32-03/09 AT32UC3A3 Figure 15-4. CompactFlash Application Example EBI DATA[15:0] DIR /OE CFRNW NCS[4] CompactFlash Connector D[15:0] _CD1 Pxx _CD2 /OE ADDR[10:0] ADDR[22] A[10:0] _REG NRD NWE0 NWE1 ADDR[23] CFCE1 CFCE2 NWAIT _OE _WE _IORD _IOWR _CE1 _CE2 _WAIT 15.6.6 SmartMedia and NAND Flash Support The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS[2] (and/or NCS[3]) address space. Writing to the HMATRIX.SFR6.CS2A (and/or HMATRIX.SFR6.CS3A) bit the appropriate value enables the NAND Flash logic. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS[2] (and/or NCS[3]). The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS[2] (and/or NCS[3]) signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS[2] (and/or NCS[3]) address space. See Figure 15-5 on page 165 for more informations. For details on these waveforms, refer to the SMC Section. The SmartMedia device is connected the same way as the NAND Flash device. 164 32072A-AVR32-03/09 AT32UC3A3 Figure 15-5. NAND Flash Signal Multiplexing on EBI Pins EBI SMC NandFlash Logic NCS[2]/[3] NRD NANDOE NANDWE NWR0_NWE 15.6.6.1 NAND Flash signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to I/O Controller lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 15-6. NAND Flash Application Example DATA[7:0] ADDR[22] ADDR[21] AD[7:0] ALE CLE EBI NandFlash NANDOE NANDWE NOE NWE NCS[2/3] Or I/O line I/O line CE R/B Note: The External Bus Interfaces is also able to support 16-bits devices. 165 32072A-AVR32-03/09 AT32UC3A3 15.7 15.7.1 Application Example Hardware Interface Table 15-9. EBI Pins and External Static Devices Connections Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices SMC D[7:0] - A[0] A[1] A[23:2] CS OE WE - D[7:0] D[15:8] - A[0] A[22:1] CS OE WE WE (1) (1) Pins name Controller DATA[7:0] DATA[15:0 ADDR[0] ADDR[1] ADDR[23:2] NCS[0] - NCS[5] NRD NWE0 NWE1 16-bit Static Device D[7:0] D[15:8] NBS0(2) A[0] A[22:1] CS OE WE NBS1(2) Note: 1. NWE1 enables upper byte writes. NWE0 enables lower byte writes. 2. NBS1 enables upper byte writes. NBS0 enables lower byte writes. Table 15-10. EBI Pins and External Devices Connections Pins of the Interfaced Device SDRAM Pins name Controller DATA[7:0] DATA[15:8] ADDR[0] ADDR[1] ADDR[10:2] ADDR[11] SDA10 ADDR[12] ADDR[14:13] ADDR[15] ADDR[16] ADDR[17] ADDR[20:18] Compact Flash Compact Flash True IDE Mode SMC Smart Media or NAND Flash SDRAMC D[7:0] D[15:8] DQM0 - A[8:0] A[9] A[10] - A[12:11] - BA0 BA1 - D[7:0] D[15:8] A[0] A[1] A[10:2] - - - - - - - - D[7:0] D[15:8] A[0] A[1] A[10:2] - - - - - - - - AD[7:0] AD[15:8] - - - - - - - - - - - 166 32072A-AVR32-03/09 AT32UC3A3 Table 15-10. EBI Pins and External Devices Connections (Continued) Pins of the Interfaced Device SDRAM Pins name Controller ADDR[21] ADDR[22] NCS[0] NCS[1] NCS[2] NCS[3] NCS[4] NCS[5] NANDOE NANDWE NRD NWE0 NWE1 CFRNW CFCE1 CFCE2 SDCS SDCK SDCKE RAS CAS SDWE NWAIT Pxx (2) (2) Compact Flash Compact Flash True IDE Mode SMC Smart Media or NAND Flash SDRAMC - - - SDCS[0] - - - - - - - - DQM1 - - - SDCS[1] CLK CKE RAS CAS WE - - - - REG - - - - CFCS0 CFCS1 - - OE WE IOR CFRNW CE1 CE2 - - - - - - WAIT CD1 or CD2 - (1) (1) (1) - REG - - - - CFCS0 CFCS1 - - - WE IOR CFRNW CS0 CS1 - - - - - - WAIT CD1 or CD2 - (1) (1) (1) CLE(3) ALE(3) - - CE0 CE1 - - OE WE - - - - - - - - - - - - - - RDY Pxx Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any I/O Controller line. 3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see Section 15.6.6. 167 32072A-AVR32-03/09 AT32UC3A3 15.7.2 Connection Examples Figure 15-7 on page 168shows an example of connections between the EBI and external devices. Figure 15-7. EBI Connections to Memory Devices EBI DATA[15:0] RAS CAS SDCK SDCKE SDWE ADDR[0] NWE1 NRD NWE0 DATA[7:0] D[7:0] SDCK SDCKE SDWE RAS CAS ADDR[0] SDRAM 2Mx8 A[9:0] A[10] A[11] BA0 BA1 ADDR[11:2] SDA10 ADDR[13] ADDR[16] ADDR[17] DATA[15:8] D[7:0] SDCK SDCKE SDWE RAS CAS NWE1 SDRAM 2Mx8 A[9:0] A[10] A[11] BA0 BA1 ADDR[11:2] SDA10 ADDR[13] ADDR[16] ADDR[17] CS CLK CKE WE RAS CAS DQM CS CLK CKE WE RAS CAS DQM SDA10 ADDR[17:1] SDCS or NCS[1] NCS[0] SRAM 128Kx8 D[7:0] A[16:0] ADDR[17:1] DATA[15:8] DATA[7:0] SRAM 128Kx8 D[7:0] A[16:0] ADDR[17:1] NCS[0] NRD NWE0 CS OE WE NCS[0] NRD NWE1 CS OE WE 168 32072A-AVR32-03/09 AT32UC3A3 16. Static Memory Controller (SMC) Rev. 1.0.6.3 16.1 Features * * * * * * * * * * * * 6 chip selects available 64-Mbytes address space per chip select 8- or 16-bit data bus Word, halfword, byte transfers Byte write or byte select lines Programmable setup, pulse and hold time for read signals per chip select Programmable setup, pulse and hold time for write signals per chip select Programmable data float time per chip select Compliant with LCD module External wait request Automatic switch to slow clock mode Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes 16.2 Overview The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 chip selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8-16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes. 169 32072A-AVR32-03/09 AT32UC3A3 16.3 Block Diagram Figure 16-1. SMC Block Diagram NC S[5:0] SM C Chip Select NRD NW R 0/N W E A0/NBS0 NW R 1/NBS1 SM C A1/N W R 2/NBS2 EBI M ux Logic I/O Controller N CS[5:0] NR D NW E0 ADDR [0] N W E1 ADDR [1] HM atrix Power M anager CLK_SM C A[23:2] ADDR [23:2] D[15:0] N W AIT DATA[15:0] NW AIT User Interface Peripheral Bus 16.4 I/O Lines Description Table 16-1. Pin Name NCS[5:0] NRD NWR0/NWE A0/NBS0 NWR1/NBS1 A[25:2] D[15:0] NWAIT I/O Lines Description Pin Description Chip Select Lines Read Signal Write 0/Write Enable Signal Address Bit 0/Byte 0 Select Signal Write 1/Byte 1 Select Signal Address Bus Data Bus External Wait Signal Type Output Output Output Output Output Output Input/Output Input Low Active Level Low Low Low Low Low 16.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 170 32072A-AVR32-03/09 AT32UC3A3 16.5.1 I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multiplexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the I/O Controller. 16.5.2 Clocks The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SMC before disabling the clock, to avoid freezing the SMC in an undefined state. 16.6 16.6.1 Functional Description Application Example Figure 16-2. SMC Connections to Static Memory Devices D0-D15 A0/NBS0 NWR0/NWE NWR1/NBS1 D0-D7 128K x 8 SRAM D0-D7 CS A0-A16 A2-A18 D8-D15 128K x 8 SRAM D0-D7 CS A0-A16 A2-A18 NRD NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NWR0/NWE OE WE NRD NWR1/NBS1 OE WE Static Memory Controller A2-A25 16.6.2 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 16-3 on page 172). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory. 171 32072A-AVR32-03/09 AT32UC3A3 Figure 16-3. Memory Connections for Six External Devices NCS[0] - NCS[5] NRD SMC NWE A[25:0] D[15:0] NCS5 NCS4 NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] 8 or 16 D[15:0] or D[7:0] 16.6.3 16.6.3.1 Connection to External Devices Data bus width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the Data Bus Width field in the Mode Register (MODE.DBW) for the corresponding chip select. Figure 16-4 on page 172 shows how to connect a 512K x 8-bit memory on NCS2. Figure 16-5 on page 173 shows how to connect a 512K x 16-bit memory on NCS2. 16.6.3.2 Byte write or byte select access Each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the Byte Access Type bit in the MODE register (MODE.BAT) for the corresponding chip select. Figure 16-4. Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[7:0] A[18:2] A0 A1 Write Enable Output Enable Memory Enable 172 32072A-AVR32-03/09 AT32UC3A3 Figure 16-5. Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 SMC NBS0 NBS1 NWE NRD NCS[2] D[15:0] A[18:1] A[0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable *Byte write access The byte write access mode supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in byte write access mode. * For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. The byte write access mode is used to connect two 8-bit devices as a 16-bit memory. The byte write option is illustrated on Figure 16-6 on page 174. *Byte select access In this mode, read/write operations can be enabled/disabled at a byte level. One byte select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. * For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. The byte select access is used to connect one 16-bit device. 173 32072A-AVR32-03/09 AT32UC3A3 Figure 16-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[15:8] A[24:2] A[23:1] A[0] Write Enable Read Enable Memory Enable D[7:0] SMC A1 NWR0 NWR1 NRD NCS[3] D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable *Signal multiplexing Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To save I/Os at the external bus interface, control signals at the SMC interface are multiplexed. For 16-bit devices, bit A0 of address is unused. When byte select option is selected, NWR1 is unused. When byte write option is selected, NBS0 to NBS1 are unused. Table 16-3. Signal Name Device Type SMC Multiplexed Signal Translation 16-bit Bus 1 x 16-bit Byte Select NBS0 NWE NBS1 A1 NWR0 NWR1 A1 A1 2 x 8-bit Byte Write A0 NWE 8-bit Bus 1 x 8-bit Byte Access Type (BAT) NBS0_A0 NWE_NWR0 NBS1_NWR1 NBS2_NWR2_A1 16.6.4 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the address bus (A). NWE represents either the NWE 174 32072A-AVR32-03/09 AT32UC3A3 signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 16.6.4.1 Read waveforms The read cycle is shown on Figure 16-7 on page 175. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices Figure 16-7. Standard Read Cycle CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] NRDSETUP NRDPULSE NRDHOLD NCSRDSETUP NCSRDPULSE NRDCYCLE NCSRDHOLD *NRD waveform The NRD signal is characterized by a setup timing, a pulse width, and a hold timing. 1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD falling edge. 2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge. 3. NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. *NCS waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time. 175 32072A-AVR32-03/09 AT32UC3A3 1. NCSRDSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. *Read cycle The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRDCYCLE = NRDSETUP + NRDPULSE + NRDHOLD Similarly, NRDCYCLE = NCSRDSETUP + NCSRDPULSE + NCSRDHOLD All NRD and NCS timings are defined separately for each chip select as an integer number of CLK_SMC cycles. To ensure that the NRD and NCS timings are coherent, the user must define the total read cycle instead of the hold timing. NRDCYCLE implicitly defines the NRD hold time and NCS hold time as: NRDHOLD = NRDCYCLE - NRDSETUP - NRDPULSE And, NCSRDHOLD = NRDCYCLE - NCSRDSETUP - NCSRDPULSE *Null delay setup and hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 16-8 on page 177). 176 32072A-AVR32-03/09 AT32UC3A3 Figure 16-8. No Setup, No Hold on NRD, and NCS Read Signals CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS D[15:0] NRDSETUP NRDPULSE NRDPULSE NCSRDPULSE NCSRDPULSE NCSRDPULSE NRDCYCLE NRDCYCLE NRDCYCLE *Null Pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads to unpredictable behavior. 16.6.4.2 Read mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timi n g s t o k n o w w h i c h s ig n a l r i s e s f i r s t . T h e R e a d M o d e b it i n t h e M O D E r e g i s t e r (MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. *Read is controlled by NRD (MODE.READMODE = 1) Figure 16-9 on page 178 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to `Z' after the rising edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of CLK_SMC that generates the rising edge of NRD, whatever the programmed waveform of NCS may be. 177 32072A-AVR32-03/09 AT32UC3A3 Figure 16-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling *Read is controlled by NCS (MODE.READMODE = 0) Figure 16-10 on page 179 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the MODE.READMODE bit must be written to zero (read is controlled by NCS): the SMC internally samples the data on the rising edge of CML_SMC that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. 178 32072A-AVR32-03/09 AT32UC3A3 Figure 16-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling 16.6.4.3 Write waveforms The write protocol is similar to the read protocol. It is depicted in Figure 16-11 on page 180. The write cycle starts with the address setting on the memory address bus. *NWE waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWESETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge. 2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE rising edge. 3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3. 16.6.4.4 NCS waveforms The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined. 1. NCSWRSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. 179 32072A-AVR32-03/09 AT32UC3A3 Figure 16-11. Write Cycle CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE NCS NWESETUP NCSWRSETUP NWEPULSE NWEHOLD NCSWRPULSE NWECYCLE NCSWRHOLD *Write cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWECYCLE = NWESETUP + NWEPULSE + NWEHOLD Similarly, NWECYCLE = NCSWRSETUP + NCSWRPULSE + NCSWRHOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWEHOLD = NWECYCLE - NWESETUP - NWEPULSE And, NCSWRHOLD = NWECYCLE - NCSWRSETUP - NCSWRPULSE 180 32072A-AVR32-03/09 AT32UC3A3 *Null delay setup and hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 16-12 on page 181). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 16-12. Null Setup and Hold Values of NCS and NWE in Write Cycle CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE, NWE0, NWE1 NCS D[15:0] NWESETUP NWEPULSE NWEPULSE NCSWRSETUP NCSWRPULSE NCSWRPULSE NWECYCLE NWECYCLE NWECYCLE *Null pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads to unpredictable behavior. 16.6.4.5 Write mode The Write Mode bit in the MODE register (MODE.WRITEMODE) of the corresponding chip select indicates which signal controls the write operation. *Write is controlled by NWE (MODE.WRITEMODE = 1) Figure 16-13 on page 182 shows the waveforms of a write operation with MODE.WRITEMODE equal to one. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWESETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. 181 32072A-AVR32-03/09 AT32UC3A3 Figure 16-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] *Write is controlled by NCS (MODE.WRITEMODE = 0) Figure 16-14 on page 182 shows the waveforms of a write operation with MODE.WRITEMODE written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCSWRSETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 16-14. WRITEMODE = 0. The Write Operation Is Controlled by NCS CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 182 32072A-AVR32-03/09 AT32UC3A3 16.6.4.6 Coding timing parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type. The Setup register (SETUP) groups the definition of all setup parameters: * NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP. The Pulse register (PULSE) groups the definition of all pulse parameters: * NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE. The Cycle register (CYCLE) groups the definition of all cycle parameters: * NRDCYCLE, NWECYCLE. Table 16-4 on page 183 shows how the timing parameters are coded and their permitted range. Table 16-4. Coding and Range of Timing Parameters Permitted Range Coded Value setup [5:0] pulse [6:0] cycle [8:0] Number of Bits 6 7 9 Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] Coded Value 0 value 31 0 value 63 0 value 127 Effective Value 128 value 128+31 256 value 256+63 256 value 256+127 512 value 512+127 768 value 768+127 16.6.4.7 Usage restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals. For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true if the MODE.WRITEMODE bit is written to one. See Section 16.6.5.2. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 16.6.5 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 183 32072A-AVR32-03/09 AT32UC3A3 16.6.5.1 Chip select wait states The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the deactivation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to high level. Figure 16-15 on page 184 illustrates a chip select wait state between access on Chip Select 0 (NCS0) and Chip Select 2 (NCS2). Figure 16-15. Chip Select Wait State Between a Read Access on NCS0 and a Write Access on NCS2 CLK_SMC A[25:2] NBS1, , A1 NRD NWE NCS0 NCS2 NRDCYCLE D[15:0] NWECYCLE Read to Write Wait State Chip Select Wait State 16.6.5.2 Early read wait state In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid: * if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 16-16 on page 185). 184 32072A-AVR32-03/09 AT32UC3A3 * in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode (Figure 16-17 on page 186). The write operation must end with a NCS rising edge. Without an early read wait state, the write operation could not complete properly. * in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing (NWEHOLD = 0), the feedback of the write control signal is used to control address, data, chip select, and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. See Figure 16-18 on page 187. Figure 16-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE NRD No hold No setup D[15:0] Write cycle Early Read Wait state Read cycle 185 32072A-AVR32-03/09 AT32UC3A3 Figure 16-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No Setup. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE NRD No hold D[15:0] No setup Write cycle (WRITEMODE=0) Read cycle Early Read Wait State (READMODE=0 or READMODE=1) 186 32072A-AVR32-03/09 AT32UC3A3 Figure 16-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Internal write controlling signal external write controlling signal(NWE) No hold NRD Read setup=1 D[15:0] Write cycle (WRITEMODE = 1) Early Read Wait State Read cycle (READMODE=0 or READMODE=1) 16.6.5.3 Reload user configuration wait state The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called "reload user configuration wait state" is used by the SMC to load the new set of parameters to apply to next accesses. The reload configuration wait state is not applied in addition to the chip select wait state. If accesses before and after reprogramming the user interface are made to different devices (different chip selects), then one single chip select wait state is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. *User procedure To insert a reload configuration wait state, the SMC detects a write access to any MODE register of the user interface. If the user only modifies timing registers (SETUP, PULSE, CYCLE registers) in the user interface, he must validate the modification by writing the MODE register, even if no change was made on the mode parameters. 187 32072A-AVR32-03/09 AT32UC3A3 *Slow clock mode transition A reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see Section 16.6.8). 16.6.5.4 Read to write wait state Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 16-15 on page 184. 16.6.6 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: * before starting a read access to a different external memory. * before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the Data Float Time field of the MODE register (MODE.TDFCYCLES) for the corresponding chip select. The value of MODE.TDFCYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF will not slow down the execution of a program from internal memory. The data float wait states management depends on the MODE.READMODE bit and the TDF Optimization bit of the MODE register (MODE.TDFMODE) for the corresponding chip select. 16.6.6.1 Read mode Writing a one to the MODE.READMODE bit indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The data float period then begins after the rising edge of the NRD signal and lasts MODE.TDFCYCLES cycles of the CLK_SMC clock. When the read operation is controlled by the NCS signal (MODE.READMODE = 0), the MODE.TDFCYCLES field gives the number of CLK_SMC cycles during which the data bus remains busy after the rising edge of NCS. Figure 16-19 on page 189 illustrates the data float period in NRD-controlled mode (MODE.READMODE =1), assuming a data float period of two cycles (MODE.TDFCYCLES = 2). Figure 16-20 on page 189 shows the read operation when controlled by NCS (MODE.READMODE = 0) and the MODE.TDFCYCLES field equals to three. 188 32072A-AVR32-03/09 AT32UC3A3 Figure 16-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2) CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] TDF = 2 clock cycles NRD controlled read operation Figure 16-20. TDF Period in NCS Controlled Read Operation (TDFCYCLES = 3) CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NRD NCS tPACC D[15:0] TDF = 3 clock cycles NCS controlled read operation 189 32072A-AVR32-03/09 AT32UC3A3 16.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1) When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 16-21 on page 190 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRDHOLD = 4; READMODE = 1 (NRD controlled) NWESETUP = 3; WRITEMODE = 1 (NWE controlled) TDFCYCLES = 6; TDFMODE = 1 (optimization enabled). Figure 16-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins CLK_SMC A[25:2] NRD NRDHOLD = 4 NWE NWESETUP = 3 NCS0 TDFCYCLES = 6 D[15:0] Read access on NCS0 (NRD controlled) Read to Write Wait State Write access on NCS0 (NWE controlled) 16.6.6.3 TDF optimization disabled (MODE.TDFMODE = 0) When optimization is disabled, data float wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional data float wait states will be inserted. Figure 16-22 on page 191, Figure 16-23 on page 191 and Figure 16-24 on page 192 illustrate the cases: * read access followed by a read access on another chip select. * read access followed by a write access on another chip select. 190 32072A-AVR32-03/09 AT32UC3A3 * read access followed by a write access on the same chip select. with no TDF optimization. Figure 16-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Different Chip Selects. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Read2 controlling signal(NRD) D[15:0] Read1 hold = 1 Read2 setup = 1 TDFCYCLES = 6 5 TDF WAIT STATES Read1 cycle TDFCYCLES = 6 Chip Select Wait State Read 2 cycle TDFMODE=0 (optimization disabled) Figure 16-23. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access on Different Chip Selects. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Read1 hold = 1 Write2 setup = 1 Write2 controlling signal(NWE) TDFCYCLES = 4 D[15:0] Read1 cycle TDFCYCLES = 4 Read to Write Chip Select Wait State Wait State 2 TDF WAIT STATES Write 2 cycle TDFMODE=0 (optimization disabled) 191 32072A-AVR32-03/09 AT32UC3A3 Figure 16-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on the Same Chip Select. CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Read1 hold = 1 Write2 setup = 1 Write2 controlling signal(NWE) TDFCYCLES = 5 D[15:0] 4 TDF WAIT STATES Read1 cycle TDFCYCLES = 5 Read to Write Wait State Write 2 cycle TDFMODE=0 (optimization disabled) 16.6.7 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding chip select must be written to either two (frozen mode) or three (ready mode). When the MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 16.6.7.1 Restriction When one of the MODE.EXNWMODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode (Section 16.6.9), or in Slow Clock Mode (Section 16.6.8). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 16.6.7.2 Frozen mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 16-25 on page 193. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. 192 32072A-AVR32-03/09 AT32UC3A3 The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 16-26 on page 194. Figure 16-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2). CLK_SMC A[25:2] NBS0, NBS1, A0, A1 FROZEN STATE 4 NWE 6 NCS 5 4 3 2 2 2 2 0 3 2 1 1 1 1 0 D[15:0] NWAIT Internally synchronized NWAIT signal Write cycle EXNWMODE = 2 (Frozen) WRITEMODE = 1 (NWE controlled) NWEPULSE = 5 NCSWRPULSE = 7 193 32072A-AVR32-03/09 AT32UC3A3 Figure 16-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2). CLK_SMC A[25:2] NBS0, NBS1, A0, A1 FROZEN STATE NCS 4 3 2 2 2 1 0 2 1 NRD 0 5 5 5 4 3 2 1 0 1 0 NWAIT Internally synchronized NWAIT signal Read cycle EXNWMODE = 2 (Frozen) READMODE = 0 (NCS controlled) NRDPULSE = 2, NRDHOLD = 6 NCSRDPULSE = 5, NCSRDHOLD = 3 Assertion is ignored 194 32072A-AVR32-03/09 AT32UC3A3 16.6.7.3 Ready mode In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 16-27 on page 195 and Figure 16-28 on page 196. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 16-28 on page 196. Figure 16-27. NWAIT Assertion in Write Access: Ready Mode (MODE.EXNWMODE = 3). CLK _SM C A [2 5 :2 ] NBS0, NBS1, A0, A1 FRO ZEN STATE 4 NW E 6 NCS 5 4 3 2 1 1 1 0 3 2 1 0 0 0 D [1 5 :0 ] N W A IT In te rn a lly s y n c h ro n iz e d N W A IT s ig n a l W rite c y c le E X N W M O D E = 3 (R e a d y m o d e ) W R IT E M O D E = 1 (N W E _ c o n tro lle d ) NW EPULSE = 5 N CSW R PULSE = 7 195 32072A-AVR32-03/09 AT32UC3A3 Figure 16-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3). CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Wait STATE NCS 6 5 4 3 2 1 0 0 NRD 6 5 4 3 2 1 1 0 NWAIT Internally synchronized NWAIT signal Read cycle EXNWMODE = 3 (Ready mode) READMODE = 0 (NCS_controlled) NRDPULSE = 7 NCSRDPULSE = 7 Assertion is ignored Assertion is ignored 196 32072A-AVR32-03/09 AT32UC3A3 16.6.7.4 NWAIT latency and read/write timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the two cycles of resynchronization plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 16-29 on page 197. When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 synchronization cycles + 1 cycle Figure 16-29. NWAIT Latency CLK_SMC A[25:2] NBS0, NBS1, A0, A1 Wait STATE 4 NRD Minimal pulse length 3 2 1 0 0 0 NWAIT nternally synchronized NWAIT signal NWAIT latency 2 cycle resynchronization Read cycle EXNWMODE = 2 or 3 READMODE = 1 (NRD controlled) NRDPULSE = 5 197 32072A-AVR32-03/09 AT32UC3A3 16.6.8 Slow Clock Mode The SMC is able to automatically apply a set of "slow clock mode" read/write waveforms when an internal signal driven by the SMC's Power Management Controller is asserted because CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects. Slow clock mode waveforms Figure 16-30 on page 198 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 16-5 on page 198 indicates the value of read and write parameters in slow clock mode. 16.6.8.1 Figure 16-30. Read and Write Cycles in Slow Clock Mode CLK_SMC CLK_SMC A[25:2] A[25:2] NBS0, NBS1, A0, A1 NBS0, NBS1, A0, A1 NWE 1 1 1 NRD 1 1 NCS NRDCYCLES = 2 SLOW CLOCK MODE READ NCS NWECYCLES = 3 SLOW CLOCK MODE WRITE Table 16-5. Read and Write Timing Parameters in Slow Clock Mode Duration (cycles) 1 1 0 2 2 Write Parameters NWESETUP NWEPULSE NCSWRSETUP NCSWRPULSE NWECYCLE Duration (cycles) 1 1 0 3 3 Read Parameters NRDSETUP NRDPULSE NCSRDSETUP NCSRDPULSE NRDCYCLE 198 32072A-AVR32-03/09 AT32UC3A3 16.6.8.2 Switching from (to) slow clock mode to (from) normal mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 16-31 on page 199. The external device may not be fast enough to support such timings. Figure 16-32 on page 200 illustrates the recommended procedure to properly switch from one mode to the other. Figure 16-31. Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode Internal signal from PM CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 1 1 1 2 3 2 NCS NWECYCLE = 3 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE NWECYCLE = 7 NORMAL MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition Slow clock mode transition is detected: Reload Configuration Wait State 199 32072A-AVR32-03/09 AT32UC3A3 Figure 16-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PM CLK_SMC A[25:2] NBS0, NBS1, A0, A1 NWE 1 NCS 1 1 2 3 2 SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 16.6.9 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the Page Mode Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be configured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 16-6 on page 200. With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa) as shown in Figure 16-33 on page 201. When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Table 16-6. Page Size 4 bytes 8 bytes 16 bytes 32 bytes Notes: Page Address and Data Address within a Page Page Address(1) A[25:2] A[25:3] A[25:4] A[25:5] Data Address in the Page(2) A[1:0] A[2:0] A[3:0] A[4:0] 1. A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. 16.6.9.1 Protocol and timings in page mode Figure 16-33 on page 201 shows the NRD and NCS timings in page mode access. 200 32072A-AVR32-03/09 AT32UC3A3 Figure 16-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 16-6 on page 200) CLK_SMC A[MSB] A[LSB] NRD tpa NCS tsa tsa D[15:0] NCSRDPULSE NRDPULSE NRDPULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the PULSE.NCSRDPULSE field value. The pulse length of subsequent accesses within the page are defined using the PULSE.NRDPULSE field value. In page mode, the programming of the read timings is described in Table 16-7 on page 201: Table 16-7. Parameter READMODE NCSRDSETUP NCSRDPULSE NRDSETUP NRDPULSE NRDCYCLE Programming of Read Timings in Page Mode Value `x' `x' tpa `x' tsa `x' Definition No impact No impact Access time of first access to the page No impact Access time of subsequent accesses in the page No impact The SMC does not check the coherency of timings. It will always apply the NCSRDPULSE timings as page access timing (tpa) and the NRDPULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the programmed value for tsa. 16.6.9.2 Byte access type in page mode The byte access type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the MODE.BAT bit to zero (byte select access type). 201 32072A-AVR32-03/09 AT32UC3A3 16.6.9.3 Page mode restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. Sequential and non-sequential accesses If the chip select and the MSB of addresses as defined in Table 16-6 on page 200 are identical, then the current access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (tsa). Figure 16-34 on page 202 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. 16.6.9.4 Figure 16-34. Access to Non-sequential Data within the Same Page CLK_SMC A[25:3] Page address A[2], A1, A0 A1 A3 A7 NRD NCS D[7:0] NCSRDPULSE D1 NRDPULSE D3 NRDPULSE D7 202 32072A-AVR32-03/09 AT32UC3A3 16.7 User Interface The SMC is programmed using the registers listed in Table 16-8 on page 203. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 16-8 on page 203, "CS_number" denotes the chip select number. Sixteen bytes (0x10) are required per chip select. The user must complete writing the configuration by writing anyone of the Mode Registers. Table 16-8. SMC Register Memory Map Offset 0x00 + CS_number*0x10 0x04 + CS_number*0x10 0x08 + CS_number*0x10 0x0C + CS_number*0x10 Register Setup Register Pulse Register Cycle Register Mode Register Register Name SETUP PULSE CYCLE MODE Access Read/Write Read/Write Read/Write Read/Write Reset 0x01010101 0x01010101 0x00030003 0x10002103 203 32072A-AVR32-03/09 AT32UC3A3 16.7.1 Setup Register Register Name: SETUP Access Type: Offset: Reset Value: Read/Write 0x00 + CS_number*0x10 0x01010101 31 - 30 - 29 28 27 26 25 24 NCSRDSETUP 21 20 19 NRDSETUP 13 12 11 10 9 8 18 17 16 23 - 22 - 15 - 14 - NCSWRSETUP 5 4 3 NWESETUP 2 1 0 7 - 6 - * NCSRDSETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS Setup Length in read access = ( 128 x NCSRDSETUP [ 5 ] + NCSRDSETUP [ 4:0 ] ) clock cycles * NRDSETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD Setup Length = ( 128 x NRDSETUP [ 5 ] + NRDSETUP [ 4:0 ] ) clock cycles * NCSWRSETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS Setup Length in write access = ( 128 x NCSWRSETUP [ 5 ] + NCSWRSETUP [ 4:0 ] ) clock cycles * NWESETUP: NWE Setup Length The NWE signal setup length is defined as: NWE Setup Length = ( 128 x NWESETUP [ 5 ] + NWESETUP [ 4:0 ] ) clock cycles 204 32072A-AVR32-03/09 AT32UC3A3 16.7.2 Pulse Register Register Name: PULSE Access Type: Offset: Reset Value: Read/Write 0x04 + CS_number*0x10 0x01010101 31 - 30 29 28 27 NCSRDPULSE 26 25 24 23 - 22 21 20 19 NRDPULSE 18 17 16 15 - 14 13 12 11 NCSWRPULSE 10 9 8 7 - 6 5 4 3 NWEPULSE 2 1 0 * NCSRDPULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS Pulse Length in read access = ( 256 x NCSRDPULSE [ 6 ] + NCSRDPULSE [ 5:0 ] ) clock cycles The NCS pulse length must be at least one clock cycle. In page mode read access, the NCSRDPULSE field defines the duration of the first access to one page. * NRDPULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD Pulse Length = ( 256 x NRDPULSE [ 6 ] + NRDPULSE [ 5:0 ] ) clock cycles The NRD pulse length must be at least one clock cycle. In page mode read access, the NRDPULSE field defines the duration of the subsequent accesses in the page. * NCSWRPULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS Pulse Length in write access = ( 256 x NCSWRPULSE [ 6 ] + NCSWRPULSE [ 5:0 ] ) clock cycles The NCS pulse length must be at least one clock cycle. * NWEPULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE Pulse Length = ( 256 x NWEPULSE [ 6 ] + NWEPULSE [ 5:0 ] ) clock cycles The NWE pulse length must be at least one clock cycle. 205 32072A-AVR32-03/09 AT32UC3A3 16.7.3 Cycle Register Register Name: CYCLE Access Type: Offset: Reset Value: Read/Write 0x08 + CS_number*0x10 0x00030003 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 NRDCYCLE[8] 23 22 21 20 19 18 17 16 NRDCYCLE[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 NWECYCLE[8] 7 6 5 4 3 2 1 0 NWECYCLE[7:0] * NRDCYCLE[8:0]: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read Cycle Length = ( 256 x NRDCYCLE [ 8:7 ] + NRDCYCLE [ 6:0 ] ) clock cycles * NWECYCLE[8:0]: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write Cycle Length = ( 256 x NWECYCLE [ 8:7 ] + NWECYCLE [ 6:0 ] ) clock cycles 206 32072A-AVR32-03/09 AT32UC3A3 16.7.4 Mode Register Register Name: MODE Access Type: Offset: Reset Value: Read/Write 0x0C + CS_number*0x10 0x10002103 31 - 30 - 29 28 27 - 26 - 25 - 24 PS PMEN 23 - 22 - 21 - 20 19 18 17 16 TDFMODE TDFCYCLES 15 - 14 - 13 12 11 - 10 - 9 - 8 DBW BAT 7 - 6 - 5 4 3 - 2 - 1 WRITEMODE 0 EXNWMODE READMODE * PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. PS 0 1 2 3 Page Size 4-byte page 8-byte page 16-byte page 32-byte page * PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied. * TDFMODE: TDF Optimization 1: TDF optimization is enabled. The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled.The number of TDF wait states is inserted before the next access begins. * TDFCYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDFCYCLES period. The external bus cannot be used by another chip select during TDFCYCLES plus one cycles. From 0 up to 15 TDFCYCLES can be set. 207 32072A-AVR32-03/09 AT32UC3A3 * DBW: Data Bus Width DBW 0 1 2 3 Data Bus Width 8-bit bus 16-bit bus Reserved Reserved * BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. BAT 0 Byte Access Type Byte select access type: Write operation is controlled using NCS, NWE, NBS0, NBS1 Read operation is controlled using NCS, NRD, NBS0, NBS1 Byte write access type: Write operation is controlled using NCS, NWR0, NWR1 Read operation is controlled using NCS and NRD 1 * EXNWMODE: External WAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal. EXNWMODE 0 1 2 External NWAIT Mode Disabled: the NWAIT input signal is ignored on the corresponding chip select. Reserved Frozen Mode: if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle is resumed from the point where it was stopped. Ready Mode: the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 3 * WRITEMODE: Write Mode 1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be inserted after the setup of NWE. 0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be inserted after the setup of NCS. 208 32072A-AVR32-03/09 AT32UC3A3 * READMODE: Read Mode READMODE 0 Read Access Mode The read operation is controlled by the NCS signal. If TDF are programmed, the external bus is marked busy after the rising edge of NCS. If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS. The read operation is controlled by the NRD signal. If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. If TDF optimization is enabled (TDFMODE =1), TDF wait states are inserted after the setup of NRD. 1 209 32072A-AVR32-03/09 AT32UC3A3 17. SDRAM Controller (SDRAMC) Rev: 2.2.0.3 17.1 Features * 128-Mbytes address space * Numerous configurations supported - 2K, 4K, 8K row address memory parts - SDRAM with two or four internal banks - SDRAM with 16-bit data path Programming facilities - Word, halfword, byte access - Automatic page break when memory boundary has been reached - Multibank ping-pong access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable - Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices) Energy-saving capabilities - Self-refresh, power-down, and deep power-down modes supported - Supports mobile SDRAM devices Error detection - Refresh error interrupt SDRAM power-up initialization by software CAS latency of one, two, and three supported Auto Precharge command not used * * * * * * 17.2 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit) accesses. The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access depending on the frequency. The different modes available (self refresh, power-down, and deep power-down modes) minimize power consumption on the SDRAM device. 210 32072A-AVR32-03/09 AT32UC3A3 17.3 Block Diagram Figure 17-1. SDRAM Controller Block Diagram SDCK SDRAMC C h ip S ele ct M em o ry C ontrolle r SDRAMC Interrup t SDCKE SDCS B A [1 :0] A D D R [17 :1 6] RAS CAS SDW E Power M an ag er C LK _ S D R A M C RAS CAS SDW E D Q M [0 ] D Q M [1 ] EBI M U X L og ic I/O C on trolle r A D D R [0] NW E1 SDCK SDCKE SDCS SDRAMC S D R A M C _A [9 :0] A D D R [1 1:2] S D R A M C _ A [10 ] S D R A M C _ A [12 :11 ] U ser Interfa ce A D D R [1 3:14 ] D [1 5 :0 ] D A T A [15 :0 ] P eriph era l B us SDA10 17.4 I/O Lines Description Table 17-1. Name SDCK SDCKE SDCS BA[1:0] RAS CAS SDWE DQM[1:0] SDRAMC_A[12:0] D[15:0] I/O Lines Description Description SDRAM Clock SDRAM Clock Enable SDRAM Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus Type Output Output Output Output Output Output Output Output Output Input/Output Low Low Low High High Low Active Level 17.5 17.5.1 Application Example Hardware Interface Figure 17-2 on page 212 shows an example of SDRAM device connection using a 16-bit data bus width. It is important to note that this example is given for a direct connection of the devices to the SDRAMC, without External Bus Interface or I/O Controller multiplexing. 211 32072A-AVR32-03/09 AT32UC3A3 Figure 17-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width D0-D31 RAS CAS SDCK SDCKE SDWE DQM[0-1] D0-D7 2Mx8 SDRAM D0-D7 CS CLK CKE A0-A9 A11 WE A10 RAS BA0 CAS BA1 DQM D8-D15 2Mx8 SDRAM D0-D7 CS CLK CKE A0-A9 A11 WE A10 RAS BA0 CAS BA1 DQM SDRAM Controller SDRAMC_A10 BA0 BA1 DQM1 SDRAMC_A10 BA0 BA1 DQM0 SDRAMC_A[0-12] BA0 BA1 SDCS 17.5.2 Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows mapping different memory types according to the values set in the SDRAMC Configuration Register (CR). The SDRAMC's function is to make the SDRAM device access protocol transparent to the user. Table 17-2 on page 213 to Table 17-4 on page 213 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 212 32072A-AVR32-03/09 AT32UC3A3 17.5.2.1 Table 17-2. 2 7 2 6 2 5 16-bit memory data bus width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 Row[10:0] Row[10:0] Row[10:0] Row[10:0] 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 M0 M0 M0 M0 BA[1:0] BA[1:0] BA[1:0] BA[1:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] Table 17-3. 2 7 2 6 2 5 SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 M0 M0 M0 M0 BA[1:0] BA[1:0] BA[1:0] BA[1:0] Row[11:0] Row[11:0] Row[11:0] Row[11:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] Table 17-4. 2 7 2 6 2 5 SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 Row[12:0] Row[12:0] Row[12:0] Row[12:0] 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 M0 M0 M0 M0 BA[1:0] BA[1:0] BA[1:0] BA[1:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] Notes: 1. M0 is the byte address inside a 16-bit halfword. 17.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.6.1 I/O Lines The SDRAMC module signals pass through the External Bus Interface (EBI) module where they are multiplexed. The user must first configure the I/O controller to assign the EBI pins corresponding to SDRAMC signals to their peripheral function. If I/O lines of the EBI corresponding to SDRAMC signals are not used by the application, they can be used for other purposes by the I/O Controller. 213 32072A-AVR32-03/09 AT32UC3A3 17.6.2 Power Management The SDRAMC must be properly stopped before entering in reset mode, i.e., the user must issue a Deep power mode command in the Mode (MD) register and wait for the command to be completed. Clocks The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined state. 17.6.4 Interrupts The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC interrupt requires the interrupt controller to be programmed first. 17.6.3 17.7 17.7.1 Functional Description SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be defined in the CR register by writing the following fields with the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR), Number of Columns (NC), Number of Rows (NR), Number of Banks (NB), CAS Latency (CAS), and the Data Bus Width (DBW). 2. For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low Power Register (LPR). 3. The Memory Device Type field must be defined in the Memory Device Register (MDR.MD). 4. A No Operation (NOP) command must be issued to the SDRAM devices to start the SDRAM clock. The user must write the value one to the Command Mode field in the SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM address. 5. A minimum pause of 200s is provided to precede any signal toggle. 6. An All Banks Precharge command must be issued to the SDRAM devices. The user must write the value two to the MR.MODE field and perform a write access to any SDRAM address. 7. Eight Auto Refresh commands are provided. The user must write the value four to the MR.MODE field and performs a write access to any SDRAM location eight times. 8. A Load Mode Register command must be issued to program the parameters of the SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst length. The user must write the value three to the MR.MODE field and perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to zero. See Section 17.8.1 for details about Load Mode Register command. 9. For mobile SDRAM initialization, an Extended Load Mode Register command must be issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must write the value five to the MR.MODE field and perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are equal to one. See Section 17.8.1 for details about Extended Load Mode Register command. 214 32072A-AVR32-03/09 AT32UC3A3 10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and performing a write access at any location in the SDRAM. 11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register (TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The SDRAM device requires a refresh every 15.625s or 7.81s. With a 100MHz frequency, the TR register must be written with the value 1562 (15.625 s x 100 MHz) or 781 (7.81 s x 100 MHz). After initialization, the SDRAM devices are fully functional. Figure 17-3. SDRAM Device Initialization Sequence SDCKE SDCK tRP tRC tMRD SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE DQM Inputs Stable for 200 usec Precharge All Banks 1st Auto Refresh 8th Auto Refresh LMR Command Valid Command 17.7.2 SDRAM Controller Write Cycle The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAMC uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAMC generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge and active (tRP) commands and between active and write (tRCD ) commands. For definition of these timing parameters, refer to the Section 17.8.3. This is described in Figure 17-4 on page 216. 215 32072A-AVR32-03/09 AT32UC3A3 Figure 17-4. Write Burst, 16-bit SDRAM Access tRCD = 3 SDCS SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f Col g Col h Col i Col j Col k Col l RAS CAS SDWE D[15:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl 17.7.3 SDRAM Controller Read Cycle The SDRAMC allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAMC automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between precharge and active (tRP) commands and between active and read (tRCD) commands. These two parameters are set in the CR register of the SDRAMC. After a read command, additional wait states are generated to comply with the CAS latency (one, two, or three clock delays specified in the CR register). For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the next access. While the last value of the column is returned by the SDRAMC on the bus, the SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. 216 32072A-AVR32-03/09 AT32UC3A3 Figure 17-5. Read Burst, 16-bit SDRAM Access tRCD = 3 SDCS CAS = 2 SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDWE D[15:0] (Input) Dnc Dne Dna Dnb Dnd Dnf 17.7.4 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge and active (tRP) commands and between the active and read (tRCD) commands. This is described in Figure 17-6 on page 218. 217 32072A-AVR32-03/09 AT32UC3A3 Figure 17-6. Read Burst with Boundary Row Access TRP = 3 SDCS TRCD = 3 CAS = 2 SDCK Row n SDRAMC_A[12:0] Col a Col b Col c Col d Row m Col a Col b Col c Col d Col e RAS CAS SDWE D[15:0] Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme 17.7.5 SDRAM Controller Refresh Cycles An auto refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto refresh automatically. The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles between successive refresh cycles. A refresh error interrupt is generated when the previous auto refresh command did not perform. In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is cleared by reading the ISR register. When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See Figure 17-7 on page 219. 218 32072A-AVR32-03/09 AT32UC3A3 Figure 17-7. Refresh Cycle Followed by a Read Access tRP = 3 SDCS tRC = 8 tRCD = 3 CAS = 2 SDCK Row n SDRAMC_A[12:0] Col c Col d Row m Col a RAS CAS SDWE D[15:0] (input) Dnb Dnc Dnd Dma 17.7.6 Power Management Three low power modes are available: * Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the SDRAMC. Current drained by the SDRAM is very low. * Power-down mode: auto refresh cycles are controlled by the SDRAMC. Between auto refresh cycles, the SDRAM is in power-down. Current drained in power-down mode is higher than in self refresh mode. * Deep power-down mode (only available with mobile SDRAM): the SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAMC activates one low power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in self refresh and power-down mode after the last access by configuring the Timeout field in the Low Power Register (LPR.TIMEOUT). 17.7.6.1 Self refresh mode This mode is selected by writing the value one to the Low Power Configuration Bits field in the SDRAMC Low Power Register (LPR.LPCB). In self refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto refresh cycles. All the inputs to the SDRAM device become "don't care" except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAMC provides a sequence of commands and exits self refresh mode. Some low power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) 219 32072A-AVR32-03/09 AT32UC3A3 and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR register, and transmitted to the low power SDRAM device during initialization. After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automatically. The PASR/DS/TCSR parameters values are therefore updated before entry into self refresh mode. The SDRAM device must remain in self refresh mode for a minimum period of tRAS and may remain in self refresh mode for an indefinite period. This is described in Figure 17-8 on page 220. Figure 17-8. Self Refresh Mode Behavior Self Refresh Mode TXSR = 3 SDRAMC_A[12:0] Row SDCK SDCKE SDCS RAS CAS SDWE Access Request To the SDRAM Controller 17.7.6.2 Low power mode This mode is selected by writing the value two to the LPR.LPCB field. Power consumption is greater than in self refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self refresh mode, the SDRAM device cannot remain in low power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto refresh operations are performed by the SDRAM itself, the SDRAMC carries out the refresh operation. The exit procedure is faster than in self refresh mode. This is described in Figure 17-9 on page 221. 220 32072A-AVR32-03/09 AT32UC3A3 Figure 17-9. Low Power Mode Behavior TRCD = 3 SDCS CAS = 2 Low Power Mode SDCK SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f RAS CAS SDCKE D[15:0] (input) Dna Dnb Dnc Dnd Dne Dnf 17.7.6.3 Deep power-down mode This mode is selected by writing the value three to the LPR.LPCB field. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the user must not access to the SDRAM until a new initialization sequence is done (See Section 17.7.1). This is described in Figure 17-10 on page 222. 221 32072A-AVR32-03/09 AT32UC3A3 Figure 17-10. Deep Power-down Mode Behavior tRP = 3 SDCS SDCK Row n SDRAMC_A[12:0] Col c Col d RAS CAS SDWE SCKE D[15:0] (Input) Dnb Dnc Dnd 222 32072A-AVR32-03/09 AT32UC3A3 17.8 User Interface SDRAMC Register Memory Map Register Mode Register Refresh Timer Register Configuration Register High Speed Register Low Power Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Memory Device Register Register Name MR TR CR HSR LPR IER IDR IMR ISR MDR Access Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Read/Write Reset 0x00000000 0x00000000 0x852372C0 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 17-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 223 32072A-AVR32-03/09 AT32UC3A3 17.8.1 Mode Register Register Name: MR Access Type: Offset: Reset Value: Read/Write 0x00 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 MODE 0 * MODE: Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. MODE 0 1 2 Description Normal mode. Any access to the SDRAM is decoded normally. The SDRAMC issues a "NOP" command when the SDRAM device is accessed regardless of the cycle. The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. This command will load the CR.CAS field into the SDRAM device Mode Register. All the other parameters of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst mode...). The SDRAMC issues an "Auto Refresh" command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM device Extended Mode Register. All the other bits of the SDRAM device Extended Mode Register will be set to zero. Deep power-down mode. Enters deep power-down mode. 3 4 5 6 224 32072A-AVR32-03/09 AT32UC3A3 17.8.2 Refresh Timer Register Register Name: TR Access Type: Offset: Reset Value: Read/Write 0x04 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 COUNT[11:8] 9 8 7 6 5 4 COUNT[7:0] 3 2 1 0 * COUNT[11:0]: Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (CLK_SDRAMC), the refresh rate of the SDRAM device and the refresh burst length where 15.6s per row is a typical value for a burst of length one. To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 225 32072A-AVR32-03/09 AT32UC3A3 17.8.3 Configuration Register Register Name: CR Access Type: Offset: Reset Value: Read/Write 0x08 0x852372C0 31 30 TXSR 29 28 27 26 TRAS 25 24 23 22 TRCD 21 20 19 18 TRP 17 16 15 14 TRC 13 12 11 10 TWR 9 8 7 DBW 6 CAS 5 4 NB 3 NR 2 1 NC 0 * TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between 0 and 15. * TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is between 0 and 15. * TRCD: Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles is between 0 and 15. * TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is between 0 and 15. * TRC: Row Cycle Delay Reset value is seven cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0 and 15. * TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. * DBW: Data Bus Width Reset value is 16 bits. 0: Reserved. 1: Data bus width is 16 bits. 226 32072A-AVR32-03/09 AT32UC3A3 * CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles is managed. CAS 0 1 2 3 CAS Latency (Cycles) Reserved 1 2 3 * NB: Number of Banks Reset value is two banks. NB 0 1 Number of Banks 2 4 * NR: Number of Row Bits Reset value is 11 row bits. NR 0 1 2 3 Row Bits 11 12 13 Reserved * NC: Number of Column Bits Reset value is 8 column bits. NC 0 1 2 3 Column Bits 8 9 10 11 227 32072A-AVR32-03/09 AT32UC3A3 17.8.4 High Speed Register Register Name: HSR Access Type: Offset: Reset Value: Read/Write 0x0C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DA * DA: Decode Cycle Enable A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus. The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory. 1: Decode cycle is enabled. 0: Decode cycle is disabled. 228 32072A-AVR32-03/09 AT32UC3A3 17.8.5 Low Power Register Register Name: LPR Access Type: Offset: Reset Value: Read/Write 0x10 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 TIMEOUT 12 11 DS 10 9 TCSR 8 7 - 6 5 PASR 4 3 - 2 - 1 LPCB 0 * TIMEOUT: Time to Define when Low Power Mode Is Enabled TIMEOUT 0 1 2 3 Time to Define when Low Power Mode Is Enabled The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer. The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer. The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer. Reserved. * DS: Drive Strength (only for low power SDRAM) This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification. After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode. * TCSR: Temperature Compensated Self Refresh (only for low power SDRAM) This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depending on the temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification. After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode. * PASR: Partial Array Self Refresh (only for low power SDRAM) This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the SDRAM device specification. After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the SDRAM device is accessed automatically and its PASR parameter value is updated before entry in self refresh mode. 229 32072A-AVR32-03/09 AT32UC3A3 * LPCB: Low Power Configuration Bits LPCB 0 Low Power Configuration Low power feature is inhibited: no power-down, self refresh or deep power-down command is issued to the SDRAM device. The SDRAMC issues a self refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access. The SDRAMC issues a power-down command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the power-down mode when accessed and enters it after the access. The SDRAMC issues a deep power-down command to the SDRAM device. This mode is unique to lowpower SDRAM. 1 2 3 230 32072A-AVR32-03/09 AT32UC3A3 17.8.6 Interrupt Enable Register Register Name: IER Access Type: Offset: Reset Value: Write-only 0x14 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 231 32072A-AVR32-03/09 AT32UC3A3 17.8.7 Interrupt Disable Register Register Name: IDR Access Type: Offset: Reset Value: Write-only 0x18 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RES Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 232 32072A-AVR32-03/09 AT32UC3A3 17.8.8 Interrupt Mask Register Register Name: IMR Access Type: Offset: Reset Value: Read-only 0x1C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RES 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 233 32072A-AVR32-03/09 AT32UC3A3 17.8.9 Interrupt Status Register Register Name: ISR Access Type: Offset: Reset Value: Read-only 0x20 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RES * RES: Refresh Error Status This bit is set when a refresh error is detected. This bit is cleared when the register is read. 234 32072A-AVR32-03/09 AT32UC3A3 17.8.10 Memory Device Register Register Name: MDR Access Type: Offset: Reset Value: Read/Write 0x24 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 MD 0 * MD: Memory Device Type MD 0 1 Other Device Type SDRAM Low power SDRAM Reserved 235 32072A-AVR32-03/09 AT32UC3A3 18. Error Corrected Code Controller (ECCHRS) Rev. 1.0.0.0 18.1 Features * Hardware Error Corrected Code Generation with two methods : - Hamming code detection and correction by software (ECC-H) - Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS) Supports NAND Flash and SmartMediaTM devices with 8- or 16-bit data path for ECC-H, and with 8-bit data path for ECC-RS Supports NAND Flash and SmartMediaTM with page sizes of 528, 1056, 2112, and 4224 bytes (specified by software) ECC_H supports : - One bit correction per page of 512,1024,2048, or 4096 bytes - One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes - One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096 bytes ECC_RS supports : - 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and 4096 bytes with 8-bit data path * * * * 18.2 Overview NAND Flash and SmartMediaTM devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash and SmartMediaTM lifetime, additional invalid blocks may occur which can be detected and corrected by an Error Corrected Code (ECC). The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. The ECC controller is capable of single-bit error correction and two-bit random detection when using the Hamming code (ECC-H) and fourerror correction whatever the number of erroneous bit in the byte error when using the Reed-Solomon code (ECC-RS). When NAND Flash/SmartMediaTM have more than two erroneous bits when using the Hamming code (ECC-H) or more than four bits in error when using the Reed-Solomon code (ECC-RS), the data cannot be corrected. 236 32072A-AVR32-03/09 AT32UC3A3 18.3 Block Diagram Figure 18-1. ECCHRS Block Diagram NAND Flash Encoder RS4 SmartMedia Logic Partial Syndrome Rom 1024x10 GF(2 ) 10 Error Evaluator Polynomial process Chien Search Static Memory Controller ECC Controller Ctrl/ECC 1bit Algorithm HECC User Interface Peripheral Bus 18.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 18.4.1 I/O Lines The ECCHRS signals pass through the External Bus Interface module (EBI) where they are multiplexed. The programmer must first configure the I/O Controller to assign the EBI pins corresponding to the Static Memory Controller (SMC) signals to their peripheral function. If I/O lines of the EBI corresponding to SMC signals are not used by the application, they can be used for other purposes by the I/O Controller. 18.4.2 Power Management If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined state. 18.4.4 Interrupts The ECCHRS interrupt request line is connected to the interrupt controller. Using the ECCHRS interrupt requires the interrupt controller to be programmed first. 18.4.3 237 32072A-AVR32-03/09 AT32UC3A3 18.5 Functional Description A page in NAND Flash and SmartMediaTM memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, NAND Flash providers recommend to utilize either one ECC per 256 bytes of data, one ECC per 512 bytes of data, or one ECC for all of the page. For the next generation of deep micron SLC NAND Flash and with the new MLC NAND Flash, it is also recommended to ensure at least a four-error ECC per 512 bytes whatever is the page size. The only configurations required for ECC are the NAND Flash or the SmartMediaTM page size (528/1056/2112/4224) and the type of correction wanted (one ECC-H for all the page, one ECCH per 256 bytes of data, one ECC-H per 512 bytes of data, or four-error ECC-RS per 512 bytes of data). The page size is configured by writing in the Page Size field in the Mode Register (MD.PAGESIZE). Type of correction is configured by writing the Type of Correction field in the Mode Register (MD.TYPECORREC). The ECC is automatically computed as soon as a read (0x00) or a write (0x80) command to the NAND Flash or the SmartMedia TM is detected. Read and write access must start at a page boundary. The ECC results are available as soon as the counter reaches the end of the main area. The values in the Parity Registers (PR0 to PR15) for ECC-H and in the Codeword Parity registers (CWPS00 to CWPS79) for ECC-RS are then valid and locked until a new start condition occurs (read/write command followed by address cycles). 18.5.1 Write Access Once the Flash memory page is written, the computed ECC codes are available in PR0 to PR15 registers for ECC-H and in CWPS00 to CWPS79 registers for ECC-RS. The ECC code values must be written by the software application in the extra area used for redundancy. The number of write access in the extra area depends on the value of the MD.TYPECORREC field. For example, for one ECC per 256 bytes of data for a page of 512 bytes, only the values of PR0 and PR1 must be written by the software application in the extra area. For ECC-RS, a NAND Flash with page of 512 bytes, the software application will have to write the ten registers CWPS00 to CWPS09 in the extra area, and would have to write 40 registers (CWPS00 to CWPS39) for a NAND Flash with page of 2048 bytes. Other registers are meaningless. 18.5.2 Read Access After reading the whole data in the main area, the application must perform read accesses to the extra area where ECC code has been previously stored. Error detection is automatically performed by the ECC-H controller or the ECC-RS controller. In ECC-RS, writing a one to the Halt of Computation bit in the ECC Mode Register (MD.FREEZE) allows to stop error detection when software is jumping to the correct parity area. 238 32072A-AVR32-03/09 AT32UC3A3 Figure 18-2. FREEZE signal waveform Nand Flash page 2048B 512B FREEZE 512B 512B 512B Spare Zone The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up to the application to correct any detected error for ECC-H. The application can correct any detected error or let the hardware do the correction by writing a one to the Correction Enable bit in the MD register (MD.CORRS4) for ECC-RS. ECC computation can detect four different circumstances: * No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or SmartMediaTM page is equal to zero. All bits in the SR1 and SR2 registers will be cleared. * Recoverable error: Only the Recoverable Error bits in the ECC Status registers (SR1.RECERRn and/or SR2.RECERRn) are set. The corrupted word offset in the read page is defined by the Word Address field (WORDADDR) in the PR0 to PR15 registers. The corrupted bit position in the concerned word is defined in the Bit Address field (BITADDR) in the PR0 to PR15 registers. * ECC error: The ECC Error bits in the ECC Status Registers (SR1.ECCERRn / SR2.ECCERRn) are set. An error has been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found by the application performing an XOR between the Parity and the NParity contained in the ECC code stored in the Flash memory. For ECC-RS it is the responsibility of the software to determine where the error is located on ECC code stored in the spare zone flash area and not on user data area. * Non correctable error: The Multiple Error bits (MULERRn) in the SR1 and SR2 registers are set. Several unrecoverable errors have been detected in the Flash memory page. ECC Status Registers, ECC Parity Registers are cleared when a read/write command is detected or a software reset is performed. For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) Hsiao code is used. 24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of 512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in Figure 18-3 on page 240 and Figure 18-4 on page 241. 239 32072A-AVR32-03/09 AT32UC3A3 Figure 18-3. Parity Generation for 512/1024/2048/4096 8-bit Words 1st byte 2nd byte 3rd byte 4 th Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 Bit 6 Bit 6 Bit 6 Bit 5 Bit 5 Bit 5 Bit 5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 2 Bit 2 Bit 2 Bit 2 Bit 1 Bit 1 Bit 1 Bit 1 Bit 0 Bit 0 Bit 0 Bit 0 P8 P16 P8' P32 P8 P16' P8' PX byte (page size-3)th byte (page size-2)th byte (page size-1)th byte page size th byte Bit 7 Bit 7 Bit 7 Bit 7 P1 P2 Bit 6 Bit 6 Bit 6 Bit 6 P1' Bit 5 Bit 5 Bit 5 Bit 5 P1 Bit 4 Bit 4 Bit 4 Bit 4 P1' Bit 3 Bit 3 Bit 3 Bit 3 P1 P2 Bit 2 Bit 2 Bit 2 Bit 2 P1' Bit 1 Bit 1 Bit 1 Bit 1 P1 Bit 0 Bit 0 Bit 0 Bit 0 P1' P8 P16 P8' P32' P8 P16' P8' PX' P2' P4 P2' P4' P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1' P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2' P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4' Page size = 512 Page size = 1024 Page size = 2048 Page size = 4096 Px = 2048 Px = 4096 Px = 8192 Px = 16384 To calculate P8' to PX' and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3] else P[2i+3]'=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 240 32072A-AVR32-03/09 AT32UC3A3 Figure 18-4. Parity Generation for 512/1024/2048/4096 16-bit Words 1st byte 2 nd Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 9 Bit 9 Bit 9 Bit 8 Bit 8 Bit 8 Bit 8 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 Bit 6 Bit 6 Bit 6 Bit 5 Bit 5 Bit 5 Bit 5 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 2 Bit 2 Bit 2 Bit 2 Bit 1 Bit 1 Bit 1 Bit 1 Bit 0 Bit 0 Bit 0 Bit 0 P8 P16 P8' P32 P8 P16' P8' byte 3rd byte 4th byte PX (page size-3)th byte (page size-2)th byte (page size-1)th byte page size th byte Bit 7 Bit 7 Bit 7 Bit 7 P1 P2 Bit 6 Bit 6 Bit 6 Bit 6 P1' Bit 5 Bit 5 Bit 5 Bit 5 P1 Bit 4 Bit 4 Bit 4 Bit 4 P1' Bit 3 Bit 3 Bit 3 Bit 3 P1 P2 Bit 2 Bit 2 Bit 2 Bit 2 P1' Bit 1 Bit 1 Bit 1 Bit 1 P1 Bit 0 Bit 0 Bit 0 Bit 0 P1' P2' Bit 7 Bit 7 Bit 7 Bit 7 P1 P2 Bit 6 Bit 6 Bit 6 Bit 6 P1' Bit 5 Bit 5 Bit 5 Bit 5 P1 Bit 4 Bit 4 Bit 4 Bit 4 P1' Bit 3 Bit 3 Bit 3 Bit 3 P1 P2 Bit 2 Bit 2 Bit 2 Bit 2 P1' Bit 1 Bit 1 Bit 1 Bit 1 P1 Bit 0 Bit 0 Bit 0 Bit 0 P1' P8 P16 P8' P32' P8 P16' P8' PX' P2' P4 P5 P2' P4 P5' P2' P4' P4' Page size = 512 Page size = 1024 Page size = 2048 Page size = 4096 Px = 2048 Px = 4096 Px = 8192 Px = 16384 P1=bit15(+)bit13(+)bit11(+)bit9(+)bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit15(+)bit14(+)bit11(+)bit10(+)bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit15(+)bit14(+)bit13(+)bit12(+)bit7(+)bit6(+)bit5(+)bit4(+)P4 P5=bit15(+)bit14(+)bit13(+)bit12(+)bit11(+)bit10(+)bit9(+)bit8(+)P5 To calculate P8' to PX' and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]'=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 241 32072A-AVR32-03/09 AT32UC3A3 For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the codeword have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area, according to the scheme shown in Figure 18-5 on page 242 Figure 18-5. RS Codeword Generation Feedback 28 CW7 500 397 CW6 402 CW5 603 CW4 395 CW3 383 CW2 539 + + + + + + + CW1 DataIn + CW0 In read mode, firstly, the detection for any error is done with the partial syndrome module. It is the responsibility of the ECC-RS Controller to determine after receiving the old codeword stored in the extra area if there is any error on data and /or on the old codeword. If all syndromes (Si) are equal to zero, there is no error, otherwise a polynomial representation is written into CWPS00 to CWPS79 registers. The Partial Syndrome module performs an algorithm according to the scheme in Figure 18-6 on page 242 Figure 18-6. Partial Syndrome Block Diagram S7 Mult i x x x RegOct S2 S1 S0 DataIn(x) If the Correction Enable bit is set in the ECC Mode Register (MD.CORRS4) then the polynomial representation of error are sent to the polynomial processor. The aim of this module is to perform the polynomial division in order to calculate two polynomials, Omega (Z) and Lambda (Z), which are necessary for the two following modules (Chien Search and Error Evaluator). In order to perform addition, multiplication, and division a Read Only Memory (ROM) has been added containing the 1024 elements of the Galois field. Both Chien Search and Error Evaluator work in parallel. The Error Evaluator has the responsibility to determine the Nth error value in the data and in the old codeword according to the scheme in Figure 18-7 on page 243 242 32072A-AVR32-03/09 AT32UC3A3 Figure 18-7. Error Evaluator Block Diagram -1 0 1 -3 3 -4 4 -5 5 -7 7 + odd( ) -j ( ) -j Rom 1024x10 10 GF(2 ) inverted Array - Mult ErrorLoc Error value @ position j The Chien Search takes charge of determining if an error has occurred at symbol N according to the scheme in Figure 18-8 on page 243 Figure 18-8. Chien Search Block Diagram -2 0 0 2 -8 8 -1 1 -3 3 -7 7 + Degree of Lambda + + ( ) -j Error Located counter Flag error Not Error located odd( ) -j 243 32072A-AVR32-03/09 AT32UC3A3 18.6 User Interface ECCHRS Register Memory Map Register Control Register Mode Register Status Register 1 Parity Register 0 Parity Register 1 Status Register 2 Parity Register 2 Parity Register 3 Parity Register 4 Parity Register 5 Parity Register 6 Parity Register 7 Parity Register 8 Parity Register 9 Parity Register 10 Parity Register 11 Parity Register 12 Parity Register 13 Parity Register 14 Parity Register 15 Codeword and Syndrome 00 Codeword and Syndrome 79 MaskData 0 - Mask Data 3 Address Offset 0 - Address Offset 3 Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Status Clear Register Version Register Name CTRL MD SR1 PR0 PR1 SR2 PR2 PR3 PR4 PR5 PR6 PR7 PR8 PR9 PR10 PR11 PR12 PR13 PR14 PR15 CWPS00 CWPS79 MDATA0 - MDATA3 ADOFF0 - ADOFF3 IER IDR MR ISR ISCR VERSION Access Write-only Read/write Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) Table 18-1. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 - 0x18C 0x190 - 0x19C 0x1A0 - 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC 0x1C0 0x1FC Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter. 244 32072A-AVR32-03/09 AT32UC3A3 18.6.1 Name: Control Register CR Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RST * RST: RESET Parity Writing a one to this bit will reset the ECC Parity registers. Writing a zero to this bit has no effect. This bit always reads as zero. 245 32072A-AVR32-03/09 AT32UC3A3 18.6.2 Name: Mode Register MD Read/Write 0x004 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 CORRS4 9 - 8 FREEZE 7 - 6 5 TYPECORREC 4 3 - 2 1 PAGESIZE 0 * CORRS4: Correction Enable Writing a one to this bit will enable the correction to be done after the Partial Syndrome process and allow interrupt to be sent to CPU. Writing a zero to this bit will stop the correction after the Partial Syndrome process. 1: The correction will continue after the Partial Syndrome process. 0: The correction will stop after the Partial Syndrome process. * FREEZE: Halt of Computation Writing a one to this bit will stop the computation. Writing a zero to this bit will allow the computation as soon as read/write command to the NAND Flash or the SmartMediaTM is detected. 1: The computation will stop until a zero is written to this bit. 0: The computation is allowed. * TYPECORREC: Type of Correction ECC code TYPECORREC 0b000 ECC-H 0b001 0b010 ECC-RS 0b100 Others Description One bit correction per page One bit correction per sector of 256 bytes One bit correction per sector of 512 bytes Four bits correction per sector of 512 bytes Reserved 246 32072A-AVR32-03/09 AT32UC3A3 * PAGESIZE: Page Size This table defines the page size of the NAND Flash device when using the ECC-H code (TYPECORREC = 0b0xx). Page Size 0 1 2 3 Others Description 528 words 1056 words 2112 words 4224 words Reserved A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMediaTM memory organization. This table defines the page size of the NAND Flash device when using the ECC-RS code (TYPECORREC = 0b1xx) Page Size 0 1 2 3 4 5 6 7 Description 528 bytes 1056 bytes 1584 bytes 2112 bytes 2640 bytes 3168 bytes 3696 bytes 4224 bytes Comment 1 page of 512 bytes 2 pages of 512 bytes 3 pages of 512 bytes 4 pages of 512 bytes 5 pages of 512 bytes 6 pages of 512 bytes 7 pages of 512 bytes 8 pages of 512 bytes i.e.: for NAND Flash device with page size of 4096 bytes and 128 bytes extra area ECC-RS can manage any sub page of 512 bytes up to 8. 247 32072A-AVR32-03/09 AT32UC3A3 18.6.3 Name: Status Register 1 SR1 Read-only 0x008 0x000000000 Access Type: Offset: Reset Value: MD.TYPECORREC=0b0xx, using ECC-H code 31 - 30 MULERR7 29 ECCERR7 28 RECERR7 27 - 26 MULERR6 25 ECCERR6 24 RECERR6 23 - 22 MULERR5 21 ECCERR5 20 RECERR5 19 - 18 MULERR4 17 ECCERR4 16 RECERR4 15 - 14 MULERR3 13 ECCERR3 12 RECERR3 11 - 10 MULERR2 9 ECCERR2 8 RECERR2 7 - 6 MULERR1 5 ECCERR1 4 RECERR1 3 - 2 MULERR0 1 ECCERR0 0 RECERR0 * MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page 1: Multiple errors are detected. 0: No multiple error is detected. TYPECORREC 0 1 2 Others Sector Size page size 256 512 Reserved Comments Only MULERR0 is used MULERR0 to MULERR7 are used depending on the page size MULERR0 to MULERR7 are used depending on the page size * ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page 1: A single bit error has occurred. 0: No error have been detected. TYPECORREC 0 1 2 Others Sector Size page size 256 512 Reserved Comments Only ECCERR0 is used The user should read PR0 and PR1 to know where the error occurs in the page. ECCERR0 to ECCERR7 are used depending on the page size ECCERR0 to ECCERR7 are used depending on the page size 248 32072A-AVR32-03/09 AT32UC3A3 * RECERRn: Recoverable Error in the packet number n of 256/512 Bytes in the page 1: Errors detected. If MULERRn is zero, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. 0: No errors have been detected. TYPECORREC 0 1 2 Others sector size page size 256 512 Reserved Comments Only RECERR0 is used RECERR0 to RECERR7 are used depending on the page size RECERR0 to RECERR7 are used depending on the page size MD.TYPECORREC=0b1xx, using ECC-RS code 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 SYNVEC 3 2 1 0 * SYNVEC: Syndrome Vector After reading a page made of n sector of 512 bytes, this field returns which sector contains error detected after the syndrome analysis. The SYNVEC[n] bit is set when there is at least one error in the corresponding sector. The SYNVEC[n] bit is cleared when a read/write command is detected or a software reset is performed. 1: At least one error has occurred in the corresponding sector. 0: No error has been detected. Bit Index (n) 0 1 2 3 4 Sector Boundaries 0-511 512-1023 1023-1535 1536-2047 2048-2559 249 32072A-AVR32-03/09 AT32UC3A3 Bit Index (n) 5 6 7 Sector Boundaries 2560-3071 3072-3583 3584-4095 250 32072A-AVR32-03/09 AT32UC3A3 18.6.4 Name: Parity Register 0 PR0 Read-only 0x00C 0x00000000 Access Type: Offset: Reset Value: Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 11 10 9 8 WORDADDR[11:4] 7 6 5 4 3 2 BITADDR 1 0 WORDADDR[3:0] Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * WORDADDR: Word Address During a page read, this field contains the word address (8-bit or 16-bit word, depending on the memory plane organization) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDR: Bit Address During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 21 20 19 NPARITY0[10:4] 18 17 16 15 14 13 12 11 10 9 8 251 32072A-AVR32-03/09 AT32UC3A3 NPARITY0[3:0] 0 WORDADD0[7:5] 7 6 5 WORDADD0[4:0] 4 3 2 1 BITADDR0 0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * NPARITY0: Parity N Parity calculated by the ECC-H. * WORDADDR0: Corrupted Word Address in the page between the first byte and the 255th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDR0: Corrupted Bit Address in the page between the first byte and the 255th byte During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. 252 32072A-AVR32-03/09 AT32UC3A3 Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 NPARITY0[11:4] 15 14 13 12 11 10 9 8 NPARITY0[3:0] WORDADD0[8:5] 7 6 5 WORDADD0[4:0] 4 3 2 1 BITADDR0 0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * NPARITY0: Parity N Parity calculated by the ECC-H. * WORDADDR0: Corrupted Word Address in the page between the first byte and the 511th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDR0: Corrupted Bit Address in the page between the first byte and the 511th byte During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. 253 32072A-AVR32-03/09 AT32UC3A3 18.6.5 Name: Parity Register 1 PR1 Read-only 0x010 0x00000000 Access Type: Offset: Reset Value: Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 11 10 9 8 NPARITY[15:8] 7 6 5 4 NPARITY[7:0] 3 2 1 0 * NPARITY: Parity N During a write, the field of this register must be written in the extra area used for redundancy (for a 512-byte page size: address 514-515). Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 21 20 19 NPARITY1[10:0] 18 17 16 15 14 13 12 11 0 10 9 WORDADD1[7:5] 8 NPARITY1[3:0] 7 6 5 WORDADD1[4:0] 4 3 2 1 BITADDR1 0 254 32072A-AVR32-03/09 AT32UC3A3 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * NPARITY1: Parity N Parity alculated by the ECC-H. * WORDADDR1: corrupted Word Address in the page between the 256th and the 511th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDR1: corrupted Bit Address in the page between the 256th and the 511th byte During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 NPARITY1[11:4] 15 14 13 12 11 10 9 8 NPARITY1[3:0] WORDADD1[8:5] 7 6 5 WORDADD1[4:0] 4 3 2 1 BITADDR1 0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * NPARITY1: Parity N Parity calculated by the ECC-H. * WORDADDR1: Corrupted Word Address in the page between the 512th and the 1023th byte During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDR1: Corrupted Bit Address in the page between the 512th and the 1023th byte During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. 255 32072A-AVR32-03/09 AT32UC3A3 18.6.6 Name: Status Register 2 SR2 Read-only 0x014 0x00000000 Access Type: Offset: Reset Value: MD.TYPECORREC=0b0xx, using ECC-H code 31 - 30 MULERR15 29 ECCERR15 28 RECERR15 27 - 26 MULERR14 25 ECCERR14 24 RECERR14 23 - 22 MULERR13 21 ECCERR13 20 RECERR13 19 - 18 MULERR12 17 ECCERR12 16 RECERR12 15 - 14 MULERR11 13 ECCERR11 12 RECERR11 11 - 10 MULERR10 9 ECCERR10 8 RECERR10 7 - 6 MULERR9 5 ECCERR9 4 RECERR9 3 - 2 MULERR8 1 ECCERR8 0 RECERR8 * MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page 1: Multiple errors are detected. 0: No multiple error is detected. TYPECORREC 0 1 2 Others Sector Size page size 256 512 Reserved Comments Only MULERR0 is used MULERR0 to MULERR7 are used depending on the page size MULERR0 to MULERR7 are used depending on the page size * ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page 1: A single bit error has occurred. 0: No error is detected. TYPECORREC 0 1 2 Others sector size page size 256 512 Reserved Comments Only ECCERR0 is used The user should read PR0 and PR1 to know where the error occurs in the page. ECCERR0 to ECCERR7 are used depending on the page size ECCERR0 to ECCERR7 are used depending on the page size 256 32072A-AVR32-03/09 AT32UC3A3 MD.TYPECORREC=0b1xx, using ECC-RS code 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 MULERR 2 1 RECERR 0 Only one sub page of 512 bytes is corrected at a time. If several sub page are on error then it is necessary to do several time the correction process. * MULERR: Multiple error This bit is set to one when a multiple error have been detected by the ECC-RS. This bit is cleared when a read/write command is detected or a software reset is performed. 1: Multiple errors detected: more than four errors.Registers for one ECC for a page of 512/1024/2048/4096 bytes 0: No multiple error detected * RECERR: Number of recoverable errors if MULERR is zero RECERR 000 001 010 011 100 Comments no error one single error detected two errors detected three errors detected four errors detected 257 32072A-AVR32-03/09 AT32UC3A3 18.6.7 Name: Parity Register 2 - 15 PR2 - PR15 Read-only 0x018 - 0x04C 0x00000000 Access Type: Offset: Reset Value: 258 32072A-AVR32-03/09 AT32UC3A3 Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001) 31 23 15 30 22 29 21 28 20 27 19 NPARITYn[10:4] 26 18 25 17 24 16 14 13 12 11 0 10 9 WORDADDn[7:5] 8 NPARITYn[3:0] 7 6 5 WORDADDn[4:0] 4 3 2 1 BITADDRn 0 Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare area. * NPARITYn: Parity N Parity calculated by the ECC-H. * WORDADDRn: corrupted Word Address in the packet number n of 256 bytes in the page During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDRn: corrupted Bit Address in the packet number n of 256 bytes in the page During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010) 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 NPARITYn[11:4] 15 14 13 12 11 10 9 8 NPARITYn[3:0] WORDADDn[8:5] 7 6 5 WORDADDn[4:0] 4 3 2 1 BITADDRn 0 Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare area. Only PR2 to PR7 registers are available in this case. 259 32072A-AVR32-03/09 AT32UC3A3 * NPARITYn: Parity N Parity calculated by the ECC-H. * WORDADDRn: corrupted Word Address in the packet number n of 512 bytes in the page During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. * BITADDRn: corrupted Bit Address in the packet number n of 512 bytes in the page During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless. 260 32072A-AVR32-03/09 AT32UC3A3 18.6.8 Name: Codeword 00 - Codeword79 CWPS00 - CWPS79 Read-only 0x050 - 0x18C 0x00000000 Access Type: Offset: Reset Value: Page Write: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 CODEWORD 3 2 1 0 * CODEWORD: Once the 512 bytes of a page is written with data, this register content must be stored to any free location of the spare area. For a page of 512 bytes the entire redundancy words are made of 8 words of 10 bits. All those redundancies words are concatenated to a word of 80 bits and then cut to 10 words of 8 bits to facilitate their writing in the extra area. At the end of a page write, this field contains the redundancy word to be stored to the extra area. Page Read: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 PARSYND 3 2 1 0 261 32072A-AVR32-03/09 AT32UC3A3 * PARSYND: At the end of a page read, this field contains the Partial Syndrome S. PARSYND00-PARSYND09: this conclude all the codeword and partial syndrome word for the sub page 1 PARSYND10-PARSYND19: this conclude all the codeword and partial syndrome word for the sub page 2 PARSYND20-PARSYND29: this conclude all the codeword and partial syndrome word for the sub page 3 PARSYND30-PARSYND39: this conclude all the codeword and partial syndrome word for the sub page 4 PARSYND40-PARSYND49: this conclude all the codeword and partial syndrome word for the sub page 5 PARSYND50-PARSYND59: this conclude all the codeword and partial syndrome word for the sub page 6 PARSYND60-PARSYND69: this conclude all the codeword and partial syndrome word for the sub page 7 PARSYND70-PARSYND79: this conclude all the codeword and partial syndrome word for the sub page 8 262 32072A-AVR32-03/09 AT32UC3A3 18.6.9 Name: Mask Data 0 - Mask Data 3 MDATA0 -MDATA3 Read-only 0x190 - 0x19C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 8 MASKDATA[9:8] 7 6 5 4 3 2 1 0 MASKDATA[7:0] * MASKDATA: At the end of the correction process, this field contains the mask to be XORed with the data read to perform the final correction.This XORed is under the responsibility of the software. This field is meaningless if MD.CORRS4 is zero. 263 32072A-AVR32-03/09 AT32UC3A3 18.6.10 Name: Address Offset 0 - Address Offset 3 ADOFF0 - ADOFF3 Read-only 0x1A0 - 0x1AC 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 OFFSET[9:8] 8 7 6 5 4 OFFSET[7:0] 3 2 1 0 * OFFSET: At the end of correction process, this field contains the offset address of the data read to be corrected. This field is meaningless if MD.CORRS4 is zero. 264 32072A-AVR32-03/09 AT32UC3A3 18.6.11 Name: Interrupt Enable Register IER Write-only 0x1B0 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDCOR * ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. 265 32072A-AVR32-03/09 AT32UC3A3 18.6.12 Name: Interrupt Disable Register IDR Write-only 0x1B4 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDCOR * ENDCOR: Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 266 32072A-AVR32-03/09 AT32UC3A3 18.6.13 Name: Interrupt Mask Register IMR Read-only 0x1B8 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDCOR * ENDCOR: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 267 32072A-AVR32-03/09 AT32UC3A3 18.6.14 Name: Interrupt Status Register ISR Read-only 0x1BC 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDCOR * ENDCOR: This bit is cleared when the corresponding bit in ISCR is written to one. This bit is set when a correction process has ended. 268 32072A-AVR32-03/09 AT32UC3A3 18.6.15 Name: Interrupt Status Clear Register ISCR Write-only 0x1C0 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 ENDCOR * ENDCOR: Writing a zero to this bit has no effect Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt request. 269 32072A-AVR32-03/09 AT32UC3A3 18.6.16 Name: Version Register VERSION Read-only 0x1FC 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 VARIANT 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associated. 270 32072A-AVR32-03/09 AT32UC3A3 18.7 Module Configuration The specific configuration for the ECCHRS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 18-2. Module name ECCHRS Module clock name Clock name CLK_ECCHRS Table 18-3. Register VERSION Register Reset Values Reset Value 0x00000100 271 32072A-AVR32-03/09 AT32UC3A3 19. Peripheral DMA Controller (PDCA) Rev: 1.1.0.0 19.1 Features * * * * 8 channels Generates transfers to/from peripherals such as USART, SSC and SPI Two address pointers/counters per channel allowing double buffering Performance monitors to measure average and maximum transfer latency 19.2 Overview The Peripheral DMA controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI, SSC and memories (those memories may be on- and off-chip memories). Using the PDCA avoids CPU intervention for data transfers, improving the performance of the microcontroller. The PDCA can transfer data from memory to a peripheral or from a peripheral to memory. The PDCA consists of 8 DMA channels. Each channel has: * A 32-bit memory pointer * A 16-bit transfer counter * A 32-bit memory pointer reload value * A 16-bit transfer counter reload value The PDCA communicates with the peripheral modules over a number of handshake interfaces. The peripheral signals to the PDCA when it is ready to receive or transmit data. The PDCA acknowledges the request when the transmission has started. The number of handshake-interfaces may be higher than the number of DMA channels. If this is the case, the DMA channel must be programmed to use the desired interface. When a transmit buffer is empty or a receive buffer is full, an interrupt request can be signalled. 272 32072A-AVR32-03/09 AT32UC3A3 19.3 Block Diagram Figure 19-1. PDCA Block Diagram Peripheral 0 HSB to PB Bridge HSB Peripheral Bus Peripheral 1 Bus Matrix HSB Peripheral 2 Peripheral DMA Controller (PDCA) Interrupt Controller IRQ Peripheral (n-1) Handshake Interfaces 19.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 19.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the PDCA, the PDCA will stop functioning and resume operation after the system wakes up from sleep mode. To avoid unexpected results after waking up from sleep mode, it requires to be checked that all the data transfers through PDCA are completed before entering a sleep mode. Clocks The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. It is recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in an undefined state. 19.4.2 19.4.3 Interrupts The PDCA interrupt request line is connected to the interrupt controller. Using the PDCA interrupt requires the interrupt controller to be programmed first. 273 32072A-AVR32-03/09 AT32UC3A3 19.4.4 Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 19.5 19.5.1 Functional Description Channel Configuration Each channel in the PDCA has a set of configuration registers. Among these are the Memory Address Register (MAR), the Peripheral Select Register (PSR) and the Transfer Counter Register (TCR). The 32-bit MAR must be programmed with the start address of the memory buffer. The register will be automatically updated after each transfer to point to the next location in memory. The PSR must be programmed to select the desired peripheral/handshake interface. The TCR determines the number of data items to be transferred. The counter will be decreased by one for each data item that has been transferred. Both the MAR and the TCR registers can be read at any time to check the progress of the transfer. Each channel has reload registers for the MAR and the TCR: the Memory Address Reload Register (MARR) and the Transfer Counter Reload Register (TCRR). When the TCR reaches zero, the values in the reload registers are loaded into MAR and TCR. In this way, the PDCA can operate on two buffers for each channel. Since a new transfer starts immediately when TCR gets a non-zero value, TCR and TCRR should be the last registers to be written. 19.5.2 Memory Pointer Each channel has a 32-bit Memory Address Register. This register holds the memory address for the next transfer to be performed. The register is automatically updated after each transfer. The address will be increased by either one, two or four depending on the size of the DMA transfer (byte, halfword or word). The MAR can be read at any time during transfer. Transfer Counter Each channel has a 16-bit Transfer Counter Register. This register must be programmed with the number of transfers to be performed. The TCR register should contain the number of data items to be transferred independently of the transfer size. The TCR can be read at any time during transfer to see the number of remaining transfers. Reload Registers Both the MAR and the TCR have a reload register, respectively Memory Address Reload Register and Transfer Counter Reload Register. These registers provide the possibility for the PDCA to work on two memory buffers for each channel. When one buffer has completed, MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value. If TCR is zero when writing to TCRR and MARR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 19.5.3 19.5.4 19.5.5 Peripheral Selection The Peripheral Select Register decides which peripheral should be connected to the PDCA channel. Configuring PSR will both select the direction of the transfer (memory to peripheral or 274 32072A-AVR32-03/09 AT32UC3A3 peripheral to memory), which handshake interface to use, and the address of the peripheral holding register. 19.5.6 Transfer Size The transfer size can be set individually for each channel to be either byte, halfword or word (8bit, 16-bit or 32-bit respectively). Transfer size is set by writing the desired value to the Transfer Size field in the Mode Register (MR.SIZE). 19.5.7 Enabling and Disabling Each DMA channel is enabled by writing a one to the Transfer Enable bit in the Control Register (CR.TEN) and disabled by writing a one to the Transfer Disable bit (CR.TDIS). The current status can be read from the Status Register (SR). Interrupts Interrupts can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The Interrupt Mask Register (IMR) can be read to see whether an interrupt is enabled or not. The current status of an interrupt source can be read through the Interrupt Status Register (ISR). The PDCA has three interrupt sources: * Reload Counter Zero - The TCRR register is zero. * Transfer Finished - Both the TCR and TCRR registers are zero. * Transfer Error - An error has occurred in accessing memory. 19.5.9 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 19.5.10 Error Handling If the memory address is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory Address Register to a valid address and then write a one to the Error Clear bit in the Control Register (CR.ECLR). An interrupt can optionally be triggered on errors by writing a one to the Transfer Error bit in the Interrupt Enable Register (IER.TERR). 19.5.11 Performance Monitors The performance monitor hardware allows the user to measure the activity and stall cycles for PDCA transfers. Performance monitoring is implemented for two PDCA channels, the other channels cannot be monitored. This reduces the hardware cost of the feature. The selection of the two PDCA channels to monitor is done through the PDCA Channel to Monitor with Counter0/1 fields in the Performance Control Register (PCONTROL.MON1CH and PCONTROL.MON0CH). Due to performance monitor hardware resource sharing, the two monitor channels should NOT be programmed to monitor the same PDCA channel. This may result in UNDEFINED performance monitor behavior. 19.5.8 275 32072A-AVR32-03/09 AT32UC3A3 19.5.11.1 Measuring mechanisms Three different parameters can be measured by each channel: * The number of data transfer cycles since last channel reset, both for read and write * The number of stall cycles since last channel reset, both for read and write * The maximum latency since last channel reset, both for read and write These measurements can be extracted by software and used to generate indicators for bus latency, bus load and maximum bus latency. Each of the counters has a fixed width, and may therefore overflow. When overflow is encountered in either the Performance Channel Data Read/Write Cycle registers (PRDATAn and PWDATAn) or Performance Channel Read/Write Stall Cycles registers (PRSTALLn and PWSTALLn) of a channel, all registers in the channel are reset. This behavior is altered if the Channel Overflow Freeze bit is written to one in the Performance Control register (PCONTROL.CHnOVF). If this bit is set, the channel registers are frozen when either DATA or STALL reaches its maximum value. This simplifies one-shot readout of the counter values. The registers can also be manually reset by writing a one to the Channel Reset bit in PCONTROL register (PCONTROL.CHnRES). The Performance Channel Read/Write Latency registers (PRLATn and PWLATn) are saturating when their maximum count value is reached. The PRLATn and PWLATn registers are reset only by the user writing the reset bits in PCONTROL (PCONTROL.CHnRES). A counter must manually be enabled by writing a one to the Channel Enable bit in the Performance Control Register (PCONTROL.CHnEN). 276 32072A-AVR32-03/09 AT32UC3A3 19.6 19.6.1 User Interface Memory Map Overview PDCA Register Memory Map Contents DMA channel 0 configuration registers DMA channel 1 configuration registers ... DMA channel 7 configuration registers Performance Monitor registers Version register Table 19-1. Address Range 0x000 - 0x03F 0x040 - 0x07F ... 0x1C0 - 0x1FF 0x800-0x830 0x834 19.6.2 Channel Memory Map PDCA Channel Register Memory Map Register Memory Address Register Peripheral Select Register Transfer Counter Register Memory Address Reload Register Transfer Counter Reload Register Control Register Mode Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Register Name MAR PSR TCR MARR TCRR CR MR SR IER IDR IMR ISR Access Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Read/Write Read-only Write-only Write-only Read-only Read-only Reset 0x00000000 - (1) 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 19-2. Offset 0x000 + n*0x040 0x004 + n*0x040 0x008 + n*0x040 0x00C + n*0x040 0x010 + n*0x040 0x014 + n*0x040 0x018 + n*0x040 0x01C + n*0x040 0x020 + n*0x040 0x024 + n*0x040 0x028 + n*0x040 0x02C + n*0x040 19.6.3 Performance Monitor Memory Map PDCA Performance Monitor Register Memory Map Register Control Channel0 Read Data Cycles Channel0 Read Stall Cycles Channel0 Read Max Latency Channel0 Write Data Cycles Channel0 Write Stall Cycles Channel0 Write Max Latency Register Name PCONTROL PRDATA0 PRSTALL0 PRLAT0 PWDATA0 PWSTALL0 PWLAT0 Access Read/Write Read-only Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 19-3. Offset 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 277 32072A-AVR32-03/09 AT32UC3A3 Table 19-3. Offset 0x81C 0x820 0x824 0x828 0x82C 0x830 PDCA Performance Monitor Register Memory Map Register Channel1 Read Data Cycles Channel1 Read Stall Cycles Channel1 Read Max Latency Channel1 Write Data Cycles Channel1 Write Stall Cycles Channel1 Write Max Latency Register Name PRDATA1 PRSTALL1 PRLAT1 PWDATA1 PWSTALL1 PWLAT1 Access Read-only Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 19.6.4 Version Register Memory Map PDCA Version Register Memory Map Register Version Register Register Name VERSION Access Read-only Reset - (1) Table 19-4. Offset 0x834 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 278 32072A-AVR32-03/09 AT32UC3A3 19.6.5 Name: Memory Address Register MAR Read/Write 0x000 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 MADDR[31:24] 23 22 21 20 19 18 17 16 MADDR[23:16] 15 14 13 12 MADDR[15:8] 11 10 9 8 7 6 5 4 MADDR[7:0] 3 2 1 0 * MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA. During transfer, MADDR will point to the next memory location to be read/written. 279 32072A-AVR32-03/09 AT32UC3A3 19.6.6 Name: Peripheral Select Register PSR Read/Write 0x004 + n*0x040 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 PID 3 2 1 0 * PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel. Programming PID will select both which handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the peripheral. See the module configuration section of PDCA for details. The width of the PID field is implementation specific and dependent on the number of peripheral modules in the microcontroller. 280 32072A-AVR32-03/09 AT32UC3A3 19.6.7 Name: Transfer Counter Register TCR Read/Write 0x008 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TCV[15:8] 11 10 9 8 7 6 5 4 TCV[7:0] 3 2 1 0 * TCV: Transfer Counter Value Number of data items to be transferred by PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done. 281 32072A-AVR32-03/09 AT32UC3A3 19.6.8 Name: Memory Address Reload Register MARR Read/Write 0x00C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 MARV[31:24] 27 26 25 24 23 22 21 20 MARV[23:16] 19 18 17 16 15 14 13 12 MARV[15:8] 11 10 9 8 7 6 5 4 MARV[7:0] 3 2 1 0 * MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value. 282 32072A-AVR32-03/09 AT32UC3A3 19.6.9 Name: Transfer Counter Reload Register TCRR Read/Write 0x010 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TCRV[15:8] 11 10 9 8 7 6 5 4 TCRV[7:0] 3 2 1 0 * TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared. 283 32072A-AVR32-03/09 AT32UC3A3 19.6.10 Name: Control Register CR Write-only 0x014 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 ECLR 7 - 6 - 5 - 4 - 3 - 2 - 1 TDIS 0 TEN * ECLR: Transfer Error Clear Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the channel to transmit data. The memory address must first be set to point to a valid location. Writing a zero to this bit has no effect. * TDIS: Transfer Disable Writing a one to this bit will disable transfer for DMA channel. Writing a zero to this bit has no effect. * TEN: Transfer Enable Writing a one to this bit will enable transfer for DMA channel. Writing a zero to this bit has no effect. 284 32072A-AVR32-03/09 AT32UC3A3 19.6.11 Name: Mode Register MR Read/Write 0x018 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 SIZE 0 * SIZE: Size of Transfer Table 19-5. SIZE 0 1 2 3 Size of Transfer Size of Transfer byte halfword word Reserved 285 32072A-AVR32-03/09 AT32UC3A3 19.6.12 Name: Status Register SR Read-only 0x01C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 TEN * TEN: Transfer Enabled This bit is set when the TEN bit in CR register is written to one. This bit is cleared when the TDIS bit in CR register is written to one. 1: Transfer is enabled for the DMA channel. 0: Transfer is disabled for the DMA channel. 286 32072A-AVR32-03/09 AT32UC3A3 19.6.13 Name: Interrupt Enable Register IER Write-only 0x020 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 287 32072A-AVR32-03/09 AT32UC3A3 19.6.14 Name: Interrupt Disable Register IDR Write-only 0x024 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 288 32072A-AVR32-03/09 AT32UC3A3 19.6.15 Name: Interrupt Mask Register IMR Read-only 0x028 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 289 32072A-AVR32-03/09 AT32UC3A3 19.6.16 Name: Interrupt Status Register ISR Read-only 0x02C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ * TERR: Transfer Error 1: A transfer error has occurred. 0: No transfer errors have occurred. * TRC: Transfer Complete 1: Both the TCR and the TCRR are zero. 0: The TCR and/or the TCRR hold a non-zero value. * RCZ: Reload Counter Zero 1: The TCRR is zero. 0: The TCRR holds a non-zero value. 290 32072A-AVR32-03/09 AT32UC3A3 19.6.17 Name: Performance Control Register PCONTROL Read/Write 0x800 0x00000000 30 29 28 27 MON1CH 26 25 24 Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 20 19 MON0CH 18 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 CH1RES 8 CH0RES 7 - 6 - 5 CH1OF 4 CH0OF 3 - 2 - 1 CH1EN 0 CH0EN * MON1CH: PDCA Channel to Monitor with Counter 1 * MON0CH: PDCA Channel to Monitor with Counter 0 Due to performance monitor hardware resource sharing, the two monitor channels should NOT be programmed to monitor the same PDCA channel. This may result in UNDEFINED performance monitor behavior. * CH1RES: Channel 1 Counter Reset Writing a one to this bit will reset the counter in the channel 1. Writing a zero to this bit has no effect. Always read as 0. * CH0RES: Channel 0 Counter Reset Writing a one to this bit will reset the counter in the channel 0. Writing a zero to this bit has no effect. Always read as 0. * CH1OF: Channel Overflow Freeze 1: All channel registers are frozen just before DATA or STALL overflows. 0: The channel registers are reset if DATA or STALL overflows. * CH1OF: Channel Overflow Freeze 1: All channel registers are frozen just before DATA or STALL overflows. 0: The channel registers are reset if DATA or STALL overflows. * CH1EN: Channel 1 Enable 1: Channel 1 is enabled. 0: Channel 1 is disabled. * CH0EN: Channel 0 Enable 1: Channel 0 is enabled. 0: Channel 0 is disabled. 291 32072A-AVR32-03/09 AT32UC3A3 19.6.18 Name: Performance Channel 0 Read Data Cycles PRDATA0 Read-only 0x804 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA: Data Cycles Counted Since Last Reset 292 32072A-AVR32-03/09 AT32UC3A3 19.6.19 Name: Performance Channel 0 Read Stall Cycles PRSTALL0 Read-only 0x808 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 * STALL: Stall Cycles Counted Since Last Reset 293 32072A-AVR32-03/09 AT32UC3A3 19.6.20 Name: Performance Channel 0 Read Max Latency PRLAT0 Read/Write 0x80C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 * LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset This counter is saturating. The register is reset only when the reset bits in PCONTROL are written. 294 32072A-AVR32-03/09 AT32UC3A3 19.6.21 Name: Performance Channel 0 Write Data Cycles PWDATA0 Read-only 0x810 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA: Data Cycles Counted Since Last Reset 295 32072A-AVR32-03/09 AT32UC3A3 19.6.22 Name: Performance Channel 0 Write Stall Cycles PWSTALL0 Read-only 0x814 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 * STALL: Stall Cycles Counted Since Last Reset 296 32072A-AVR32-03/09 AT32UC3A3 19.6.23 Name: Performance Channel 0 Write Max Latency PWLAT0 Read/Write 0x818 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 * LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset This counter is saturating. The register is reset only when the reset bits in PCONTROL are written. 297 32072A-AVR32-03/09 AT32UC3A3 19.6.24 Name: Performance Channel 1 Read Data Cycles PRDATA1 Read-only 0x81C 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA: Data Cycles Counted Since Last Reset 298 32072A-AVR32-03/09 AT32UC3A3 19.6.25 Name: Performance Channel 1 Read Stall Cycles PRSTALL1 Read-only 0x820 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 * STALL: Stall Cycles Counted Since Last Reset 299 32072A-AVR32-03/09 AT32UC3A3 19.6.26 Name: Performance Channel 1 Read Max Latency PLATR1 Read/Write 0x824 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 * LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset This counter is saturating. The register is reset only when the reset bits in PCONTROL are written. 300 32072A-AVR32-03/09 AT32UC3A3 19.6.27 Name: Performance Channel 1 Write Data Cycles PWDATA1 Read-only 0x828 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA: Data Cycles Counted Since Last Reset 301 32072A-AVR32-03/09 AT32UC3A3 19.6.28 Name: Performance Channel 1 Write Stall Cycles PWSTALL1 Read-only 0x82C 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 * STALL: Stall Cycles Counted Since Last Reset 302 32072A-AVR32-03/09 AT32UC3A3 19.6.29 Name: Performance Channel 1 Write Max Latency PWLAT1 Read/Write 0x830 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 * LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset This counter is saturating. The register is reset only when the reset bits in PCONTROL are written. 303 32072A-AVR32-03/09 AT32UC3A3 19.6.30 Name: PDCA Version Register VERSION Read-only 0x834 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version number Version number of the module. No functionality associated. 304 32072A-AVR32-03/09 AT32UC3A3 19.7 Module Configuration The specific configuration for the PDCA instance is listed in the following tables. Table 19-6. Register PSRn VERSION Register Reset Values Reset Value n 0x00000110 19.7.1 DMA Handshake Signals The following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA Peripheral Select Register (PSR).). Table 19-7. PID Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PDCA Handshake Signals Peripheral module & direction ADC - RX SSC - RX USART0 - RX USART1 - RX USART2 - RX USART3 - RX TWIM0 - RX TWIM1 - RX TWIS0 - RX TWIS1 - RX SPI0 - RX SPI1 - RX SSC - TX USART0 - TX USART1 - TX USART2 - TX USART3 - TX TWIM0 - TX TWIM1 - TX TWIS0 - TX TWIS1 - TX SPI0 - TX SPI1 - TX DAC - TX 305 32072A-AVR32-03/09 AT32UC3A3 20. DMA Controller (DMACA) Rev: 2.0.6a.6 20.1 Features * 2 HSB Master Interfaces * 4 Channels * Software and Hardware Handshaking Interfaces - 11 Hardware Handshaking Interfaces * Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer * Single-block DMA Transfer * Multi-block DMA Transfer - Linked Lists - Auto-Reloading - Contiguous Blocks * DMA Controller is Always the Flow Controller * Additional Features - Scatter and Gather Operations - Channel Locking - Bus Locking - FIFO Mode - Pseudo Fly-by Operation 20.2 Overview The DMA Controller (DMACA) is an HSB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more System Bus. One channel is required for each source/destination pair. In the most basic configuration, the DMACA has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two System Bus transfers are required for each DMA data transfer. This is also known as a dual-access transfer. The DMACA is programmed via the HSB slave interface. 306 32072A-AVR32-03/09 AT32UC3A3 20.3 Block Diagram Figure 20-1. DMA Controller (DMACA) Block Diagram DMA Controller HSB Slave HSB Slave I/F Interrupt Generator irq_dma CFG Channel 1 Channel 0 FIFO HSB Master HSB Master I/F SRC FSM DST FSM 20.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 20.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines. The user must first program the GPIO controller to assign the DMACA pins to their peripheral functions. 20.4.2 Power Management To prevent bus errors the DMACA operation must be terminated before entering sleep mode. Clocks The CLK_DMACA to the DMACA is generated by the Power Manager (PM). Before using the DMACA, the user must ensure that the DMACA clock is enabled in the power manager. 20.4.3 20.4.4 Interrupts The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the DMACA interrupt requires programming the interrupt controller before configuring the DMACA. 20.4.5 Peripherals Both the source peripheral and the destination peripheral must be set up correctly prior to the DMA transfer. 307 32072A-AVR32-03/09 AT32UC3A3 20.5 20.5.1 Functional Description Basic Definitions Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (previously read from the source peripheral). Memory: Source or destination that is always "ready" for a DMA transfer and does not require a handshaking interface to interact with the DMACA. A peripheral should be assigned as memory only if it does not insert more than 16 wait states. If more than 16 wait states are required, then the peripheral should use a handshaking interface (the default if the peripheral is not programmed to be memory) in order to signal when it is ready to accept or supply data. Channel: Read/write datapath between a source peripheral on one configured System Bus layer and a destination peripheral on the same or different System Bus layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. Master interface: DMACA is a master on the HSB bus reading data from the source and writing it to the destination over the HSB bus. Slave interface: The HSB interface over which the DMACA is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMACA and source or destination peripheral to control the transfer of a single or burst transaction between them. This interface is used to request, acknowledge, and control a DMACA transaction. A channel can receive a request through one of three types of handshaking interface: hardware, software, or peripheral interrupt. Hardware handshaking interface: Uses hardware signals to control the transfer of a single or burst transaction between the DMACA and the source or destination peripheral. Software handshaking interface: Uses software registers to control the transfer of a single or burst transaction between the DMACA and the source or destination peripheral. No special DMACA handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMACA without modifying it. Peripheral interrupt handshaking interface: A simple use of the hardware handshaking interface. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. Other interface signals are ignored. Flow controller: The device (either the DMACA or source/destination peripheral) that determines the length of and terminates a DMA block transfer. If the length of a block is known before enabling the channel, then the DMACA should be programmed as the flow controller. If the length of a block is not known prior to enabling the channel, the source or destination peripheral needs to terminate a block transfer. In this mode, the peripheral is the flow controller. Flow control mode (CFGx.FCMODE): Special mode that only applies when the destination peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral. 308 32072A-AVR32-03/09 AT32UC3A3 Transfer hierarchy: Figure 20-2 on page 309 illustrates the hierarchy between DMACA transfers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for non-memory peripherals. Figure 20-3 on page 309 shows the transfer hierarchy for memory. Figure 20-2. DMACA Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer DMA Transfer Level Block Block Block Block Transfer Level Burst Transaction Burst Transaction Burst Transaction Single Transaction DMA Transaction Level System Bus Burst Transfer System Bus Burst Transfer System Bus Burst Transfer System Bus Single Transfer System Bus Single Transfer System Bus Transfer Level Figure 20-3. DMACA Transfer Hierarchy for Memory DMAC Transfer DMA Transfer Level Block Transfer Level Block Block Block System Bus Burst Transfer System Bus Burst Transfer System Bus Burst Transfer System Bus Single Transfer System Bus Transfer Level Block: A block of DMACA data. The amount of data (block length) is determined by the flow controller. For transfers between the DMACA and memory, a block is broken directly into a sequence of System Bus bursts and single transfers. For transfers between the DMACA and a non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and bursts). These are in turn broken into a sequence of System Bus transfers. Transaction: A basic unit of a DMACA transfer as determined by either the hardware or software handshaking interface. A transaction is only relevant for transfers between the DMACA and a source or destination peripheral if the source or destination peripheral is a non-memory device. There are two types of transactions: single and burst. 309 32072A-AVR32-03/09 AT32UC3A3 -Single transaction: The length of a single transaction is always 1 and is converted to a single System Bus transfer. -Burst transaction: The length of a burst transaction is programmed into the DMACA. The burst transaction is converted into a sequence of System Bus bursts and single transfers. DMACA executes each burst transfer by performing incremental bursts that are no longer than the maximum System Bus burst size set. The burst transaction length is under program control and normally bears some relationship to the FIFO sizes in the DMACA and in the source and destination peripherals. DMA transfer: Software controls the number of blocks in a DMACA transfer. Once the DMA transfer has completed, then hardware within the DMACA disables the channel and can generate an interrupt to signal the completion of the DMA transfer. You can then re-program the channel for a new DMA transfer. Single-block DMA transfer: Consists of a single block. Multi-block DMA transfer: A DMA transfer may consist of multiple DMACA blocks. Multi-block DMA transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. The source and destination can independently select which method to use. -Linked lists (block chaining) - A linked list pointer (LLP) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next block (block descriptor) and an LLP register. The DMACA fetches the LLI at the beginning of every block when block chaining is enabled. -Auto-reloading - The DMACA automatically reloads the channel registers at the end of each block to the value when the channel was first enabled. -Contiguous blocks - Where the address between successive blocks is selected to be a continuation from the end of the previous block. Scatter: Relevant to destination transfers within a block. The destination System Bus address is incremented or decremented by a programmed amount -the scatter increment- when a scatter boundary is reached. The destination System Bus address is incremented or decremented by the value stored in the destination scatter increment (DSRx.DSI) field, multiplied by the number of bytes in a single HSB transfer to the destination (decoded value of CTLx.DST_TR_WIDTH)/8. The number of destination transfers between successive scatter boundaries is programmed into the Destination Scatter Count (DSC) field of the DSRx register. Scatter is enabled by writing a `1' to the CTLx.DST_SCATTER_EN bit. The CTLx.DINC field determines if the address is incremented, decremented or remains fixed when a scatter boundary is reached. If the CTLx.DINC field indicates a fixed-address control throughout a DMA transfer, then the CTLx.DST_SCATTER_EN bit is ignored, and the scatter feature is automatically disabled. Gather: Relevant to source transfers within a block. The source System Bus address is incremented or decremented by a programmed amount when a gather boundary is reached. The number of System Bus transfers between successive gather boundaries is programmed into the Source Gather Count (SGRx.SGC) field. The source address is incremented or decremented by the value stored in the source gather increment (SGRx.SGI) field multiplied by the number of bytes in a single HSB transfer from the source -(decoded value of CTLx.SRC_TR_WIDTH)/8 when a gather boundary is reached. 310 32072A-AVR32-03/09 AT32UC3A3 Gather is enabled by writing a `1' to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field determines if the address is incremented, decremented or remains fixed when a gather boundary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gather feature is automatically disabled. Note: For multi-block transfers, the counters that keep track of the number of transfer left to reach a gather/scatter boundary are re-initialized to the source gather count (SGRx.SGC) and destination scatter count (DSRx.DSC), respectively, at the start of each block transfer. Figure 20-4. Destination Scatter Transfer System Memory D11 A0 + 0x218 A0 + 0x210 A0 + 0x208 A0 + 0x200 Data Stream Scatter Increment 0 x 080 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 Scatter Boundary A0 + 0x220 d11 D10 D9 D8 d8 D7 A0 + 0x118 D6 A0 + 0x110 A0 + 0x108 A0 + 0x100 D4 D5 d4 d7 Scatter Boundary A0 + 0x120 Scatter Increment 0 x 080 Scatter Boundary A0 + 0x020 D3 A0 + 0x018 D2 A0 + 0x010 A0 + 0x008 D0 A0 D1 d0 d3 CTLx.DST_TR_WIDTH = 3'b011 (64bit/8 = 8 bytes) DSR.DSI = 16 DSR.DSC = 4 DSR.DSI * 8 = 0x80 (Scatter Increment in bytes) 311 32072A-AVR32-03/09 AT32UC3A3 Figure 20-5. Source Gather Transfer System Memory D11 A0 + 0x034 A0 + 0x030 A0 + 0x02C D8 A0 + 0x028 A0 + 0x020 D7 A0 + 0x01C A0 + 0x018 A0 + 0x014 D4 D6 D5 d4 d7 d11 Gather Boundary A0 + 0x38 Gather Increment = 4 D10 D9 d8 Data Stream d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 Gather Boundary A0 + 0x24 Gather Increment = 4 D3 A0 + 0x00C D2 A0 + 0x008 A0 + 0x004 A0 D1 D0 d3 Gather Boundary A0 + 0x10 Gather Increment = 4 CTLx.SRC_TR_WIDTH = 3'b010 (32bit/8 = 4 bytes) SGR.SGI = 1 SGR.SGC = 4 SGR.SGI * 4 = 0x4 (Gather Increment in bytes) d0 Channel locking: Software can program a channel to keep the HSB master interface by locking the arbitration for the master bus interface for the duration of a DMA transfer, block, or transaction (single or burst). Bus locking: Software can program a channel to maintain control of the System Bus bus by asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Channel locking is asserted for the duration of bus locking at a minimum. FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is greater than or equal to half full to send data to the destination peripheral. Thus, the channel can transfer the data using System Bus bursts, eliminating the need to arbitrate for the HSB master interface for each single System Bus transfer. When this mode is not enabled, the channel only waits until the FIFO can transmit/accept a single System Bus transfer before requesting the master bus interface. Pseudo fly-by operation: Typically, it takes two System Bus cycles to complete a transfer, one for reading the source and one for writing to the destination. However, when the source and destination peripherals of a DMA transfer are on different System Bus layers, it is possible for the DMACA to fetch data from the source and store it in the channel FIFO at the same time as the DMACA extracts data from the channel FIFO and writes it to the destination peripheral. This activity is known as pseudo fly-by operation. For this to occur, the master interface for both source and destination layers must win arbitration of their HSB layer. Similarly, the source and destination peripherals must win ownership of their respective master interfaces. 312 32072A-AVR32-03/09 AT32UC3A3 20.6 Arbitration for HSB Master Interface Each DMACA channel has two request lines that request ownership of a particular master bus interface: channel source and channel destination request lines. Source and destination arbitrate separately for the bus. Once a source/destination state machine gains ownership of the master bus interface and the master bus interface has ownership of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA. An arbitration scheme decides which of the request lines (2 * DMAH_NUM_CHANNELS) is granted the particular master bus interface. Each channel has a programmable priority. A request for the master bus interface can be made at any time, but is granted only after the current HSB transfer (burst or single) has completed. Therefore, if the master interface is transferring data for a lower priority channel and a higher priority channel requests service, then the master interface will complete the current burst for the lower priority channel before switching to transfer data for the higher priority channel. If only one request line is active at the highest priority level, then the request with the highest priority wins ownership of the HSB master bus interface; it is not necessary for the priority levels to be unique. If more than one request is active at the highest requesting priority, then these competing requests proceed to a second tier of arbitration: If equal priority requests occur, then the lower-numbered channel is granted. In other words, if a peripheral request attached to Channel 7 and a peripheral request attached to Channel 8 have the same priority, then the peripheral attached to Channel 7 is granted first. 20.7 Memory Peripherals Figure 20-3 on page 309 shows the DMA transfer hierarchy of the DMACA for a memory peripheral. There is no handshaking interface with the DMACA, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMACA that it is ready to transmit/receive data, and then the DMACA can access the peripheral without the peripheral inserting wait states onto the bus. 20.8 Handshaking Interface Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The operation of the handshaking interface is different and depends on whether the peripheral or the DMACA is the flow controller. The peripheral uses the handshaking interface to indicate to the DMACA that it is ready to transfer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer through the DMACA using one of two handshaking interfaces: *Hardware handshaking *Software handshaking 313 32072A-AVR32-03/09 AT32UC3A3 Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface. 20.8.1 Software Handshaking When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller. The interrupt service routine then uses the software registers to initiate and control a DMA transaction. These software registers are used to implement the software handshaking interface. The HS_SEL_SRC/HS_SEL_DST bit in the CFGx channel configuration register must be set to enable software handshaking. When the peripheral is not the flow controller, then the last transaction registers LstSrcReg and LstDstReg are not used, and the values in these registers are ignored. 20.8.1.1 Burst Transactions Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transaction request, where x is the channel number. However, in order for a burst transaction request to start, software must write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] register. You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers in any order, but both registers must be asserted in order to initiate a burst transaction. Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers. 20.8.1.2 Single Transactions Writing a 1 to the SglReqSrcReg/SglReqDstReg initiates a single transaction. Upon completion of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored while a single transaction has been initiated, and the requested burst transaction is not serviced. Again, writing a 1 to the ReqSrcReg/ReqDstReg register is always a burst transaction request. However, in order for a burst transaction request to start, the corresponding channel bit in the SglReqSrcReg/SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSrcReg/SglReqDstReg register. Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSrcReg/ReqDstReg registers. When both are 0, then either the requested burst or single transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled and unmasked in order to generate an interrupt when the requested source or destination transaction has completed. Note: The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same transaction-complete interrupt is used for both single and burst transactions. 20.8.2 Hardware Handshaking There are 11 hardware handshaking interfaces between the DMACA and peripherals. Refer to the module configuration chapter for the device-specific mapping of these interfaces. 314 32072A-AVR32-03/09 AT32UC3A3 20.8.2.1 External DMA Request Definition When an external slave peripheral requires the DMACA to perform DMA transactions, it communicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to ensure a proper functionality (see "External DMA Request Timing" on page 315). The external nDMAREQx signal should be asserted when the source threshold level is reached. After resynchronization, the rising edge of dma_req starts the transfer. An external DMAACKx acknowledge signal is also provided to indicate when the DMA transfer has completed. The peripheral should de-assert the DMA request signal when DMAACKx is asserted. The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted again before a new transaction starts. For a source FIFO, an active edge should be triggered on nDMAREQx when the source FIFO exceeds a watermark level. For a destination FIFO, an active edge should be triggered on nDMAREQx when the destination FIFO drops below the watermark level. The source transaction length, CTLx.SRC_MSIZE, and destination transaction length, CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination peripherals. Figure 20-6. External DMA Request Timing Hclk DMA Transaction nDMAREQx dma_req DMA Transfers DMA Transfers DMA Transfers dma_ack 20.9 DMACA Transfer Types A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multiblock transfer, the SARx/DARx register in the DMACA is reprogrammed using either of the following methods: *Block chaining using linked lists *Auto-reloading *Contiguous address between blocks On successive blocks of a multi-block transfer, the CTLx register in the DMACA is re-programmed using either of the following methods: *Block chaining using linked lists *Auto-reloading When block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the LLPx register in the DMACA is re-programmed using the following method: *Block chaining using linked lists 315 32072A-AVR32-03/09 AT32UC3A3 A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These registers, along with the CFGx register, are used by the DMACA to set up and describe the block transfer. 20.9.1 20.9.1.1 Multi-block Transfers Block Chaining Using Linked Lists In this case, the DMACA re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. This is known as an LLI update. DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the address in memory of the next linked list item. Each LLI (block descriptor) contains the corresponding block descriptor (SARx, DARx, LLPx, CTLx). To set up block chaining, a sequence of linked lists must be programmed in memory. The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update. The updated contents of the CTLx register are written back to memory on block completion. Figure 20-7 on page 316 shows how to use chained linked lists in memory to define multi-block transfers using block chaining. The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN. Figure 20-7. Multi-block Transfer Using Linked Lists LLI(0) System Memory LLI(1) CTLx[63..32] CTLx[31..0] LLPx(1) DARx SARx CTLx[63..32] CTLx[31..0] LLPx(2) DARx SARx LLPx(1) LLPx(2) LLPx(0) 316 32072A-AVR32-03/09 AT32UC3A3 Table 20-1. Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table) LLP. Transfer Type LOC =0 1) Single Block or last transfer of multi-Block 2) Auto Reload multi-block transfer with contiguous SAR 3) Auto Reload multi-block transfer with contiguous DAR 4) Auto Reload multi-block transfer 5) Single Block or last transfer of multi-block 6) Linked List multi-block transfer with contiguous SAR 7) Linked List multi-block transfer with auto-reload SAR 8) Linked List multi-block transfer with contiguous DAR 9) Linked List multi-block transfer with auto-reload DAR 10) Linked List multi-block transfer Yes LLP_S_EN ( CTLx) 0 RELOAD _SR ( CFGx) 0 LLP_D_EN ( CTLx) 0 RELOAD_ DS ( CFGx) 0 CTLx, LLPx Update Method None, user reprograms CTLx,LLPx are reloaded from initial values. CTLx,LLPx are reloaded from initial values. CTLx,LLPx are reloaded from initial values. None, user reprograms CTLx,LLPx loaded from next Linked List item CTLx,LLPx loaded from next Linked List item CTLx,LLPx loaded from next Linked List item CTLx,LLPx loaded from next Linked List item CTLx,LLPx loaded from next Linked List item SARx Update Method None (single) DARx Update Method None (single) Write Back No Yes 0 0 0 1 Contiguous AutoReload No Yes 0 1 0 0 Auto-Reload Contiguous No Yes 0 1 0 1 Auto-Reload AutoReload None (single) No No 0 0 0 0 None (single) Yes No 0 0 1 0 Contiguous Linked List Yes No 0 1 1 0 Auto-Reload Linked List Yes No 1 0 0 0 Linked List Contiguous Yes No 1 0 0 1 Linked List AutoReload Yes No 1 0 1 0 Linked List Linked List Yes 20.9.1.2 Auto-reloading of Channel Registers During auto-reloading, the channel registers are reloaded with their initial values at the completion of each block and the new values used for the new block. Depending on the row number in Table 20-1 on page 317, some or all of the SARx, DARx and CTLx channel registers are reloaded from their initial value at the start of a block transfer. Contiguous Address Between Blocks In this case, the address between successive blocks is selected to be a continuation from the end of the previous block. Enabling the source or destination address to be contiguous between 20.9.1.3 317 32072A-AVR32-03/09 AT32UC3A3 blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS registers (see Figure 20-1 on page 307). Note: Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the maximum value, use Row 10 of Table 20-1 on page 317 and setup the LLI.SARx address of the block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous block. 20.9.1.4 Suspension of Transfers Between Blocks At the end of every block transfer, an end of block interrupt is asserted if: *interrupts are enabled, CTLx.INT_EN = 1 *the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number. Note: The block complete interrupt is generated at the completion of the block transfer to the destination. For rows 6, 8, and 10 of Table 20-1 on page 317, the DMA transfer does not stall between block transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1. For rows 2, 3, 4, 7, and 9 of Table 20-1 on page 317 (SARx and/or DARx auto-reloaded between block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted if the end of block interrupt is enabled and unmasked. The DMACA does not proceed to the next block transfer until a write to the block interrupt clear register, ClearBlock[n], is performed by software. This clears the channel block complete interrupt. For rows 2, 3, 4, 7, and 9 of Table 20-1 on page 317 (SARx and/or DARx auto-reloaded between block transfers), the DMA transfer does not stall if either: *interrupts are disabled, CTLx.INT_EN = 0, or *the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number. Channel suspension between blocks is used to ensure that the end of block ISR (interrupt service routine) of the next-to-last block is serviced before the start of the final block commences. This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits b efo re co mp let ion of t he fina l blo ck. Th e r elo ad bit s CFGx .REL OAD _SR a nd /o r CFGx.RELOAD_DS should be cleared in the `end of block ISR' for the next-to-last block transfer. 20.9.2 Ending Multi-block Transfers All multi-block transfers must end as shown in either Row 1 or Row 5 of Table 20-1 on page 317. At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA transfer is terminated. Note: Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for the last block. For rows 2,3 and 4 of Table 20-1 on page 317, (LLPx = 0 and CFGx.RELOAD_SR and/or CFGx.RELOAD_DS is set), multi-block DMA transfers continue until both the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be 318 32072A-AVR32-03/09 AT32UC3A3 programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. This puts the DMACA into Row 1 state. For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block descriptor in memory is zero, then the DMA transfer is terminated in Row 1. For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block transfer should clear the CFGx.RELOAD_SR and CFGx.RELOAD_DS reload bits. The last block descriptor in memory should be set up so that both the LLI.CTLx.LLP_S_EN and LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block descriptor in memory is zero, then the DMA transfer is terminated in Row 1. Note: The only allowed transitions between the rows of Table 20-1 on page 317are from any row into row 1 or row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA transfer. All other transitions between rows are not allowed. Software must ensure that illegal transitions between rows do not occur between blocks of a multi-block transfer. For example, if block N is in row 10 then the only allowed rows for block N + 1 are rows 10, 5 or 1. 20.10 Programming a Channel Three registers, the LLPx, the CTLx and CFGx, need to be programmed to set up whether single or multi-block transfers take place, and which type of multi-block transfer is used. The different transfer types are shown in Table 20-1 on page 317. The "Update Method" column indicates where the values of SARx, DARx, CTLx, and LLPx are obtained for the next block transfer when multi-block DMACA transfers are enabled. Note: In Table 20-1 on page 317, all other combinations of LLPx.LOC = 0, CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS are illegal, and causes indeterminate or erroneous behavior. 20.10.1 20.10.1.1 Programming Examples Single-block Transfer (Row 1) Row 5 in Table 20-1 on page 317 is also a single block transfer. 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers: a. Write the starting source address in the SARx register for channel x. b. Write the starting destination address in the DARx register for channel x. c. Program CTLx and CFGx according to Row 1 as shown in Table 20-1 on page 317. Program the LLPx register with `0'. d. Write the control information for the DMA transfer in the CTLx register for channel x. For example, in the register, you can program the following: -i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register. 319 32072A-AVR32-03/09 AT32UC3A3 -ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. Write the channel configuration information into the CFGx register for channel x. -i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests. Writing a `1' activates the software handshaking interface to handle source/destination requests. -ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. After the DMACA selected channel has been programmed, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled. 5. Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 6. Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. 20.10.1.2 Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control information in the LLI.CTLx register location of the block descriptor for each LLI in memory (see Figure 20-7 on page 316) for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register. b. Set up the transfer characteristics, such as: -i. Transfer width for the source in the SRC_TR_WIDTH field. -ii. Transfer width for the destination in the DST_TR_WIDTH field. -iii. Source master layer in the SMS field where source resides. -iv. Destination master layer in the DMS field where destination resides. -v. Incrementing/decrementing or fixed address for source in SINC field. -vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the channel configuration information into the CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires pro- 320 32072A-AVR32-03/09 AT32UC3A3 gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the last) are set as shown in Row 10 of Table 20-1 on page 317. The LLI.CTLx register of the last Linked List Item must be set as described in Row 1 or Row 5 of Table 20-1 on page 317. Figure 20-9 on page 323 shows a Linked List example with two list items. 5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory point to the start source/destination block address preceding that LLI fetch. 7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI entries in memory are cleared. 8. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 9. Program the CTLx, CFGx registers according to Row 10 as shown in Table 20-1 on page 317. 10.Program the LLPx register with LLPx(0), the pointer to the first Linked List item. 11.Finally, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. The transfer is performed. 12.The DMACA fetches the first LLI from the location pointed to by LLPx(0). Note: The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automatically reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0). 13.Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripheral). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. Note: Table 20-1 on page 317 14.The DMACA does not wait for the block interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current LLPx register and automatically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA transfer continues until the DMACA determines that the CTLx and LLPx registers at the end of a block transfer match that described in Row 1 or Row 5 of Table 20-1 on page 317. The DMACA then knows that the previous block transferred was the last block in the DMA transfer. The DMA transfer might look like that shown in Figure 20-8 on page 322. 321 32072A-AVR32-03/09 AT32UC3A3 Figure 20-8. Multi-Block with Linked List Address for Source and Destination Address of Source Layer Address of Destination Layer Block 2 SAR(2) DAR(2) Block 2 Block 1 SAR(1) DAR(1) Block 1 Block 0 SAR(0) Source Blocks DAR(0) Block 0 Destination Blocks If the user needs to execute a DMA transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum block size CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in Figure 20-9 on page 323. 322 32072A-AVR32-03/09 AT32UC3A3 Figure 20-9. Multi-Block with Linked Address for Source and Destination Blocks are Contiguous Address of Source Layer Address of Destination Layer Block 2 DAR(3) Block 2 SAR(3) Block 2 SAR(2) Block 1 SAR(1) Block 0 SAR(0) Block 0 DAR(0) Block 1 DAR(1) Block 2 DAR(2) Source Blocks Destination Blocks The DMA transfer flow is shown in Figure 20-11 on page 326. 323 32072A-AVR32-03/09 AT32UC3A3 Figure 20-10. DMA Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SARx, DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table? no DMAC transfer Complete interrupt generated here yes Channel Disabled by hardware 20.10.1.3 Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4) 1. Read the Channel Enable register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers: 324 32072A-AVR32-03/09 AT32UC3A3 a. Write the starting source address in the SARx register for channel x. b. Write the starting destination address in the DARx register for channel x. c. Program CTLx and CFGx according to Row 4 as shown in Table 20-1 on page 317. Program the LLPx register with `0'. d. Write the control information for the DMA transfer in the CTLx register for channel x. For example, in the register, you can program the following: -i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register. -ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. Write the channel configuration information into the CFGx register for channel x. Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are enabled. -i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. -ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. After the DMACA selected channel has been programmed, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled. 5. Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges on completion of each burst/single transaction and carry out the block transfer. 6. When the block transfer has completed, the DMACA reloads the SARx, DARx and CTLx registers. Hardware sets the Block Complete interrupt. The DMACA then samples the row number as shown in Table 20-1 on page 317. If the DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is disabled, to detect when the transfer is complete. If the DMACA is not in Row 1, the next step is performed. 7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) 325 32072A-AVR32-03/09 AT32UC3A3 should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers. This put the DMACA into Row 1 as shown in Table 20-1 on page 317. If the next block is not the last block in the DMA transfer, then the reload bits should remain enabled to keep the DMACA in Row 4. b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1'b0, where x is the channel number), then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the DMACA into ROW 1 of Table 20-1 on page 317 before the last block of the DMA transfer has completed. The transfer is similar to that shown in Figure 20-11 on page 326. The DMA transfer flow is shown in Figure 20-12 on page 327. Figure 20-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded Address of Source Layer Address of Destination Layer Block0 Block1 Block2 SAR DAR BlockN Source Blocks Destination Blocks 326 32072A-AVR32-03/09 AT32UC3A3 Figure 20-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Block Transfer Reload SARx, DARx, CTLx Block Complete interrupt generated here DMAC transfer Complete interrupt generated here yes Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.INT_EN=1 && MASKBLOCK[x]=1? no yes Stall until block complete interrupt cleared by software 20.10.1.4 Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of linked list items (otherwise known as block descriptors) in memory. Write the control information in the LLI.CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the TT_FC of the CTLx register. b. Set up the transfer characteristics, such as: -i. Transfer width for the source in the SRC_TR_WIDTH field. -ii. Transfer width for the destination in the DST_TR_WIDTH field. -iii. Source master layer in the SMS field where source resides. -iv. Destination master layer in the DMS field where destination resides. -v. Incrementing/decrementing or fixed address for source in SINC field. -vi. Incrementing/decrementing or fixed address for destination DINC field. 327 32072A-AVR32-03/09 AT32UC3A3 3. Write the starting source address in the SARx register for channel x. Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used. 4. Write the channel configuration information into the CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last) are set as shown in Row 7 of Table 20-1 on page 317 while the LLI.CTLx register of the last Linked List item must be set as described in Row 1 or Row 5 of Table 20-1 on page 317. Figure 20-7 on page 316 shows a Linked List example with two list items. 6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start destination block address proceeding that LLI fetch. 8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in memory is cleared. 9. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 10.Program the CTLx, CFGx registers according to Row 7 as shown in Table 20-1 on page 317. 11.Program the LLPx register with LLPx(0), the pointer to the first Linked List item. 12.Finally, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DmaCfgReg register is enabled. 13.The DMACA fetches the first LLI from the location pointed to by LLPx(0). Note: The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register although fetched is not used. 14.Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 15.Table 20-1 on page 317The DMACA reloads the SARx register from the initial value. Hardware sets the block complete interrupt. The DMACA samples the row number as shown in Table 20-1 on page 317. If the DMACA is in Row 1 or 5, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMACA is not in Row 1 or 5 as shown in Table 20-1 on page 317 the following steps are performed. 16.The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the 328 32072A-AVR32-03/09 AT32UC3A3 block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into Row1 as shown in Table 20-1 on page 317. If the next block is not the last block in the DMA transfer, then the source reload bit should remain enabled to keep the DMACA in Row 7 as shown in Table 20-1 on page 317. b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1'b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case, software must clear the source reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of Table 20-1 on page 317 before the last block of the DMA transfer has completed. 17.The DMACA fetches the next LLI from memory location pointed to by the current LLPx register, and automatically reprograms the DARx, CTLx and LLPx channel registers. Note that the SARx is not re-programmed as the reloaded value is used for the next DMA block transfer. If the next block is the last block of the DMA transfer then the CTLx and LLPx registers just fetched from the LLI should match Row 1 or Row 5 of Table 201 on page 317. The DMA transfer might look like that shown in Figure 20-13 on page 329. Figure 20-13. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List Address of Source Layer Address of Destination Layer Block0 DAR(0) Block1 DAR(1) SAR Block2 DAR(2) BlockN DAR(N) Source Blocks Destination Address Destination Blocks The DMA Transfer flow is shown in Figure 20-14 on page 330. 329 32072A-AVR32-03/09 AT32UC3A3 Figure 20-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Reload SARx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Is DMAC in Row1 or Row5 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.INT_EN=1 && MASKBLOCK[X]=1 ? no yes Stall until block interrupt Cleared by hardware 330 32072A-AVR32-03/09 AT32UC3A3 20.10.1.5 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing a `1' to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers: a. Write the starting source address in the SARx register for channel x. b. Write the starting destination address in the DARx register for channel x. c. Program CTLx and CFGx according to Row 3 as shown in Table 20-1 on page 317. Program the LLPx register with `0'. d. Write the control information for the DMA transfer in the CTLx register for channel x. For example, in this register, you can program the following: -i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register. -ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. Write the channel configuration information into the CFGx register for channel x. -i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. -ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. After the DMACA channel has been programmed, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled. 5. Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carries out the block transfer. 6. When the block transfer has completed, the DMACA reloads the SARx register. The DARx register remains unchanged. Hardware sets the block complete interrupt. The DMACA then samples the row number as shown in Table 20-1 on page 317. If the DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn- 331 32072A-AVR32-03/09 AT32UC3A3 Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMACA is not in Row 1, the next step is performed. 7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into Row1 as shown in Table 20-1 on page 317. If the next block is not the last block in the DMA transfer then the source reload bit should remain enabled to keep the DMACA in Row3 as shown in Table 20-1 on page 317. b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1'b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of Table 20-1 on page 317 before the last block of the DMA transfer has completed. The transfer is similar to that shown in Figure 20-15 on page 332. The DMA Transfer flow is shown in Figure 20-16 on page 333. Figure 20-15. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address Address of Source Layer Address of Destination Layer Block2 DAR(2) Block1 DAR(1) Block0 SAR DAR(0) Source Blocks Destination Blocks 332 32072A-AVR32-03/09 AT32UC3A3 Figure 20-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software Block Transfer Reload SARx, CTLx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Is DMAC in Row1 of DMAC State Machine Table? Channel Disabled by hardware no CTLx.INT_EN=1 && MASKBLOCK[x]=1? no yes Stall until Block Complete interrupt cleared by software 20.10.1.6 Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI. CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register. b. Set up the transfer characteristics, such as: -i. Transfer width for the source in the SRC_TR_WIDTH field. -ii. Transfer width for the destination in the DST_TR_WIDTH field. -iii. Source master layer in the SMS field where source resides. -iv. Destination master layer in the DMS field where destination resides. 333 32072A-AVR32-03/09 AT32UC3A3 -v. Incrementing/decrementing or fixed address for source in SINC field. -vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the starting destination address in the DARx register for channel x. Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripherals. This requires programming the SRC_PER and DEST_PER bits, respectively. 5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as shown in Row 8 of Table 20-1 on page 317, while the LLI.CTLx register of the last Linked List item must be set as described in Row 1 or Row 5 of Table 20-1 on page 317. Figure 20-7 on page 316 shows a Linked List example with two list items. 6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.SARx register location of all LLIs in memory point to the start source block address proceeding that LLI fetch. 8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in memory is cleared. 9. Clear any pending interrupts on the channel from the previous DMA transfer by writing a `1' to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 10.Program the CTLx, CFGx registers according to Row 8 as shown in Table 20-1 on page 317 11.Program the LLPx register with LLPx(0), the pointer to the first Linked List item. 12.Finally, enable the channel by writing a `1' to the ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DmaCfgReg register is enabled. 13.The DMACA fetches the first LLI from the location pointed to by LLPx(0). Note: The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. The LLI.DARx register location of the LLI although fetched is not used. The DARx register in the DMACA remains unchanged. 14.Source and destination requests single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. Note: 15.The DMACA does not wait for the block interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by current LLPx register and automatically reprograms the SARx, CTLx and LLPx channel registers. The DARx register is left unchanged. The DMA transfer continues until the DMACA samples the CTLx and LLPx registers at the end of a block transfer match that described in Row 1 or Row 334 32072A-AVR32-03/09 AT32UC3A3 5 of Table 20-1 on page 317. The DMACA then knows that the previous block transferred was the last block in the DMA transfer. The DMACA transfer might look like that shown in Figure 20-17 on page 335 Note that the destination address is decrementing. Figure 20-17. DMA Transfer with Linked List Source Address and Contiguous Destination Address Address of Source Layer Address of Destination Layer Block 2 SAR(2) Block 2 DAR(2) Block 1 SAR(1) Block 0 Block 0 SAR(0) Source Blocks Destination Blocks Block 1 DAR(1) DAR(0) The DMA transfer flow is shown in Figure 20-19 on page 336. Figure 20-18. 335 32072A-AVR32-03/09 AT32UC3A3 Figure 20-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address Channel Enabled by software LLI Fetch Hardware reprograms SARx, CTLx, LLPx DMAC block transfer Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row 1 of Table 4 ? no DMAC Transfer Complete interrupt generated here yes Channel Disabled by hardware 20.11 Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a `1' to the Channel Enable Register, ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the ChEnReg.CH_EN register bit. The recommended way for software to disable a channel without losing data is to use the CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register (CFGx) register. 1. If software wishes to disable a channel prior to the DMA transfer completion, then it can set the CFGx.CH_SUSP bit to tell the DMACA to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel FIFO is empty. 336 32072A-AVR32-03/09 AT32UC3A3 3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty. When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a `0' to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner. Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement. 20.11.1 Abnormal Transfer Termination A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to disable the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the channel is disabled by reading back 0. A case where the channel is not be disabled after a channel disable request is where either the source or destination has received a split or retry response. The DMACA must keep re-attempting the transfer to the system HADDR that originally received the split or retry response until an OKAY response is returned. To do otherwise is an System Bus protocol violation. Software may terminate all channels abruptly by clearing the global enable bit in the DMACA Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are disabled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider this as a request to disable all channels. The ChEnReg must be polled and then it must be confirmed that all channels are disabled by reading back `0'. Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals such as a source FIFO this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement. Note: 337 32072A-AVR32-03/09 AT32UC3A3 20.12 User Interface Table 20-2. Offset 0x000 0x008 0x010 0x018 0x01C 0x040 0x044 0x048 0x050 0x058 0x060 0x068 0x070 0x074 0x098 0x09C 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0C8 0x0CC 0x0F0 0x0F4 0x0F8 0x100 0x108 0x110 0x118 0x120 0x124 0x148 0x14c 0x150 DMA Controller Memory Map Register Channel 0 Source Address Register Channel 0 Destination Address Register Channel 0 Linked List Pointer Register Channel 0 Control Register Low Channel 0 Control Register High Channel 0 Configuration Register Low Channel 0 Configuration Register High Channel 0 Source Gather Register Channel 0 Destination Scatter Register Channel 1 Source Address Register Channel 1 Destination Address Register Channel 1 Linked List Pointer Register Channel 1 Control Register Low Channel 1 Control Register High Channel 1 Configuration Register Low Channel 1 Configuration Register High Channel 1Source Gather Register Channel 1 Destination Scatter Register Channel 2 Source Address Register Channel 2 Destination Address Register Channel 2 Linked List Pointer Register Channel 2 Control Register Low Channel 2 Control Register High Channel 2 Configuration Register Low Channel 2 Configuration Register High Channel 2 Source Gather Register Channel 2 Destination Scatter Register Channel 3 Source Address Register Channel 3 Destination Address Register Channel 3 Linked List Pointer Register Channel 3 Control Register Low Channel 3 Control Register High Channel 3 Configuration Register Low Channel 3 Configuration Register High Channel 3 Source Gather Register Register Name SAR0 DAR0 LLP0 CTL0L CTL0H CFG0L CFG0H SGR0 DSR0 SAR1 DAR1 LLP1 CTL1L CTL1H CFG1L CFG1H SGR1 DSR1 SAR2 DAR2 LLP2 CTL2L CTL2H CFG2L CFG2H SGR2 DSR2 SAR3 DAR3 LLP3 CTL3L CTL3H CFG3L CFG3H SGR3 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00304801 0x00000002 0x00000c00 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00304801 0x00000002 0x00000c20 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00304801 0x00000002 0x00000c40 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00304801 0x00000002 0x00000c60 0x00000004 0x00000000 338 32072A-AVR32-03/09 AT32UC3A3 Table 20-2. Offset 0x158 0x2C0 0x2C8 0x2D0 0x2D8 0x2E0 0x2E8 0x2F0 0x2F8 0x300 0x308 0x310 0x318 0x320 0x328 0x330 0x338 0x340 0x348 0x350 0x358 0x360 0x368 0x370 0x378 0x380 0x388 0x390 0x398 0x3A0 0x3F8 0x3FC DMA Controller Memory Map (Continued) Register Channel 3Destination Scatter Register Raw Status for IntTfr Interrupt Raw Status for IntBlock Interrupt Raw Status for IntSrcTran Interrupt Raw Status for IntDstTran Interrupt Raw Status for IntErr Interrupt Status for IntTfr Interrupt Status for IntBlock Interrupt Status for IntSrcTran Interrupt Status for IntDstTran Interrupt Status for IntErr Interrupt Mask for IntTfr Interrupt Mask for IntBlock Interrupt Mask for IntSrcTran Interrupt Mask for IntDstTran Interrupt Mask for IntErr Interrupt Clear for IntTfr Interrupt Clear for IntBlock Interrupt Clear for IntSrcTran Interrupt Clear for IntDstTran Interrupt Clear for IntErr Interrupt Status for each interrupt type Source Software Transaction Request Register Destination Software Transaction Request Register Single Source Transaction Request Register Single Destination Transaction Request Register Last Source Transaction Request Register Last Destination Transaction Request Register DMA Configuration Register DMA Channel Enable Register DMA Component ID Register Low DMA Component ID Register High Register Name DSR3 RawTfr RawBlock RawSrcTran RawDstTran RawErr StatusTfr StatusBlock StatusSrcTran StatusDstTran StatusErr MaskTfr MaskBlock MaskSrcTran MaskDstTran MaskErr ClearTfr ClearBlock ClearSrcTran ClearDstTran ClearErr StatusInt ReqSrcReg ReqDstReg SglReqSrcReg SglReqDstReg LstSrcReg LstDstReg DmaCfgReg ChEnReg DmaCompIdRegL DmaCompIdRegH Access Read/Write Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Write-only Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Read-only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x44571110 0x3230362A 339 32072A-AVR32-03/09 AT32UC3A3 20.12.1 Name: Channel x Source Address Register SARx Read/Write 0x000 + [x * 0x58] 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 SADD[31:24] 27 26 25 24 23 22 21 20 SADD[23:16] 19 18 17 16 15 14 13 12 SADD[15:8] 11 10 9 8 7 6 5 4 SADD[7:0] 3 2 1 0 * SADD: Source Address of DMA transfer The starting System Bus source address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the source address of the current System Bus transfer. Updated after each source System Bus transfer. The SINC field in the CTLx register determines whether the address increments, decrements, or is left unchanged on every source System Bus transfer throughout the block transfer. 340 32072A-AVR32-03/09 AT32UC3A3 20.12.2 Name: Channel x Destination Address Register DARx Read/Write 0x008 + [x * 0x58] 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DADD[31:24] 27 26 25 24 23 22 21 20 DADD[23:16] 19 18 17 16 15 14 13 12 DADD[15:8] 11 10 9 8 7 6 5 4 DADD[7:0] 3 2 1 0 * DADD: Destination Address of DMA transfer The starting System Bus destination address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination address of the current System Bus transfer. Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer. 341 32072A-AVR32-03/09 AT32UC3A3 20.12.3 Name: Linked List Pointer Register for Channel x LLPx Read/Write 0x010 + [x * 0x58] 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 LOC[29:22] 27 26 25 24 23 22 21 20 LOC[21:14] 19 18 17 16 15 14 13 12 LOC[13:6] 11 10 9 8 7 6 5 LOC[5:0] 4 3 2 1 LMS 0 * LOC: Address of the next LLI Starting address in memory of next LLI if block chaining is enabled. The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled. The LLP register has two functions: The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block). If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type. It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists. The LLPx register is also used to point to the address where write back of the control and source/destination status information occurs after block completion. * LMS: List Master Select Identifies the High speed bus interface for the device that stores the next linked list item: Table 20-3. LMS 0 1 Other List Master Select HSB Master HSB master 1 HSB master 2 Reserved 342 32072A-AVR32-03/09 AT32UC3A3 20.12.4 Name: Control Register for Channel x Low CTLxL Read/Write 0x018 + [x * 0x58] 0x00304801 Access Type: Offset: Reset Value: 31 30 29 28 LLP_SRC_E N 27 LLP_DST_E N 19 26 SMS 25 24 DMS[1] 23 DMS[0] 22 21 TT_FC 20 18 DST_GATHE R_EN 17 SRC_GATH ER_EN 9 SINC 16 SRC_MSIZE [2] 8 DINC[1] 15 14 13 12 DEST_MSIZE 11 10 SRC_MSIZE[1:0] 7 DINC[0] 6 5 SRC_TR_WIDTH 4 3 2 DST_TR_WIDTH 1 0 INT_EN This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. * LLP_SRC_EN Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero. * LLP_DST_EN Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non-zero. * SMS: Source Master Select Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from Table 20-4. SMS 0 1 Other Source Master Select HSB Master HSB master 1 HSB master 2 Reserved 343 32072A-AVR32-03/09 AT32UC3A3 * DMS: Destination Master Select Identifies the Master Interface layer where the destination device (peripheral or memory) resides Table 20-5. DMS 0 1 Other Destination Master Select HSB Master HSB master 1 HSB master 2 Reserved * TT_FC: Transfer Type and Flow Control The four following transfer types are supported: * Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral. The DMACA is always the Flow Controller. TT_FC 000 001 010 011 Other Transfer Type Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Reserved Flow Controller DMACA DMACA DMACA DMACA Reserved * DST_SCATTER_EN: Destination Scatter Enable 0 = Scatter disabled 1 = Scatter enabled Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing address control. * SRC_GATHER_EN: Source Gather Enable 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTLx.SINC bit indicates an incrementing or decrementing address control. * SRC_MSIZE: Source Burst Transaction Length Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. SRC_MSIZE 0 1 2 Size (items number) 1 4 8 344 32072A-AVR32-03/09 AT32UC3A3 SRC_MSIZE 3 4 Other Size (items number) 16 32 Reserved * DST_MSIZE: Destination Burst Transaction Length Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. DST_MSIZE 0 1 2 3 4 Other Size (items number) 1 4 8 16 32 Reserved * SINC: Source Address Increment Indicates whether to increment or decrement the source address on every source System Bus transfer. If your device is fetching data from a source peripheral FIFO with a fixed address, then set this field to "No change" Source Address Increment Increment Decrement No change SINC 0 1 Other * DINC: Destination Address Increment Indicates whether to increment or decrement the destination address on every destination System Bus transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to "No change" Destination Address Increment Increment Decrement No change DINC 0 1 Other 345 32072A-AVR32-03/09 AT32UC3A3 * SRT_TR_WIDTH: Source Transfer Width * DSC_TR_WIDTH: Destination Transfer Width SRC_TR_WIDTH/DST_TR_WIDTH 0 1 2 Other * INT_EN: Interrupt Enable Bit Size (bits) 8 16 32 Reserved If set, then all five interrupt generating sources are enabled. 346 32072A-AVR32-03/09 AT32UC3A3 20.12.5 Name: Control Register for Channel x High CTLxH Read/Write 0x01C + [x * 0x58] 0x00000002 Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 DONE 4 27 19 11 26 18 10 25 17 9 24 16 8 BLOCK_TS[11:8] 3 2 1 0 BLOCK_TS[7:0] * DONE: Done Bit Software can poll this bit to see when a block transfer is complete * BLOCK_TS: Block Transfer Size When the DMACA is flow controller, this field is written by the user before the channel is enabled to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer, unless the transfer is already in progress, in which case the value of BLOCK_TS indicates the number of single transactions that have been performed so far. The width of the single transaction is determined by CTLx.SRC_TR_WIDTH. 347 32072A-AVR32-03/09 AT32UC3A3 20.12.6 Name: Configuration Register for Channel x Low CFGxL Read/Write 0x040 + [x * 0x58] Access Type: Offset: * Reset Value: 0x00000C00 + [x * 0x20] 31 RELOAD_D ST 23 - 30 RELOAD_S RC 22 - 29 - 28 - 27 - 26 - 25 - 24 - 21 - 20 - 19 SRC_HS_P OL 11 HS_SEL_SR C 18 DST_HS_PO L 10 HS_SEL_DS T 2 - 17 - 16 - 15 - 14 13 - 12 9 FIFO_EMPT Y 1 - 8 CH_SUSP 7 6 CH_PRIOR 5 4 - 3 - 0 - * RELOAD_DST: Automatic Destination Reload The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. * RELOAD_SRC: Automatic Source Reload The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. * SRC_HS_POL: Source Handshaking Interface Polarity 0 = Active high 1 = Active low * DST_HS_POL: Destination Handshaking Interface Polarity 0 = Active high 1 = Active low * HS_SEL_SRC: Source Software or Hardware Handshaking Select This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored. * HS_SEL_DST: Destination Software or Hardware Handshaking Select This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel. 348 32072A-AVR32-03/09 AT32UC3A3 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware Initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored. * FIFO_EMPTY Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 1 = Channel's FIFO empty 0 = Channel's FIFO not empty * CH_SUSP: Channel Suspend Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0 = Not Suspended. 1 = Suspend. Suspend DMA transfer from the source. * CH_PRIOR: Channel priority A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x-1]. A programmed value outside this range causes erroneous behavior. 349 32072A-AVR32-03/09 AT32UC3A3 20.12.7 Name: Configuration Register for Channel x High CFGxH Read/Write 0x044 + [x * 0x58] 0x00000004 Access Type: Offset: Reset Value: 31 23 15 7 SRC_PER[0] 30 22 14 29 21 13 DEST_PER 28 20 12 27 19 11 26 18 10 25 17 9 SRC_PER[3:1] 24 16 8 6 - 5 - 4 3 PROTCTL 2 1 FIFO_MODE 0 FCMODE * DEST_PER: Destination Hardware Handshaking Interface Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface via the assigned hardware handshaking interface. For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. * SRC_PER: Source Hardware Handshaking Interface Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface via the assigned hardware handshaking interface. For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. * PROTCTL: Protection Control Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. * FIFO_MODE: R/W 0x0 FIFO Mode Select Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0 = Space/data available for single System Bus transfer of the specified transfer width. 1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 350 32072A-AVR32-03/09 AT32UC3A3 * FCMODE: Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 351 32072A-AVR32-03/09 AT32UC3A3 20.12.8 Name: Source Gather Register for Channel x SGRx Read/Write 0x048 + [x * 0x58] 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 SGC[11:4] 27 26 25 24 23 22 SGC[3:0] 21 20 19 18 SGI[19:16] 17 16 15 14 13 12 SGI[15:8] 11 10 9 8 7 6 5 4 SGI[7:0] 3 2 1 0 * SGC: Source Gather Count Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. * SGI: Source Gather Interval Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer. 352 32072A-AVR32-03/09 AT32UC3A3 20.12.9 Name: Destination Scatter Register for Channel x DSRx Read/Write 0x050 + [x * 0x58] 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DSC[11:4] 27 26 25 24 23 22 DSC[3:0] 21 20 19 18 DSI[19:16] 17 16 15 14 13 12 DSI[15:8] 11 10 9 8 7 6 5 4 DSI[7:0] 3 2 1 0 * DSC: Destination Scatter Count Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries. * DSI: Destination Scatter Interval Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. 353 32072A-AVR32-03/09 AT32UC3A3 20.12.10 Interrupt Registers The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: * IntTfr: DMA Transfer Complete Interrupt This interrupt is generated on DMA transfer completion to the destination peripheral. * IntBlock: Block Transfer Complete Interrupt This interrupt is generated on DMA block transfer completion to the destination peripheral. * IntSrcTran: Source Transaction Complete Interrupt This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from the handshaking interface on the source side. If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence the corresponding bit in this field is not set. * IntDstTran: Destination Transaction Complete Interrupt This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from the handshaking interface on the destination side. If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corresponding bit in this field is not set. * IntErr: Error Interrupt This interrupt is generated when an ERROR response is received from an HSB slave on the HRESP bus during a DMA transfer. In addition, the DMA transfer is cancelled and the channel is disabled. 354 32072A-AVR32-03/09 AT32UC3A3 20.12.11 Interrupt Raw Status Registers Name: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr Access Type: Offset: Reset Value: Read-only 0x2C0, 0x2C8, 0x2D0, 0x2D8, 0x2E0 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 RAW3 26 18 10 2 RAW2 25 17 9 1 RAW1 24 16 8 0 RAW0 * RAW[3:0]Raw interrupt for each channel Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Channel 2's raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers. 355 32072A-AVR32-03/09 AT32UC3A3 20.12.12 Interrupt Status Registers Name: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr Access Type: Offset: Reset Value: Read-only 0x2E8, 0x2F0, 0x2F8, 0x300, 0x308 0x00000000 31 23 15 7 * STATUS[3:0] 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 STATUS3 26 18 10 2 STATUS2 25 17 9 1 STATUS1 24 16 8 0 STATUS0 All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, StatusTfr[2] is Channel 2's status transfer complete interrupt.The contents of these registers are used to generate the interrupt signals leaving the DMACA. 356 32072A-AVR32-03/09 AT32UC3A3 20.12.13 Interrupt Mask Registers Name: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr Access Type: Offset: Reset Value: Read/Write 0x310, 0x318, 0x320, 0x328, 0x330 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 INT_M_WE3 3 INT_MASK3 26 18 10 INT_M_WE2 2 INT_MASK2 25 17 9 INT_M_WE1 1 INT_MASK1 24 16 8 INT_M_WE0 0 INT_MASK0 The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is the mask bit for Channel 2's transfer complete interrupt. A channel's INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged. Writing hex 00xx leaves MaskTfr[7:0] unchanged. Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the appropriate bit in the Status Registers. * INT_M_WE[11:8]: Interrupt Mask Write Enable 0 = Write disabled 1 = Write enabled * INT_MASK[3:0]: Interrupt Mask 0= Masked 1 = Unmasked 357 32072A-AVR32-03/09 AT32UC3A3 20.12.14 Interrupt Clear Registers Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr Access Type: Offset: Reset Value: Write-only 0x338, 0x340, 0x348, 0x350, 0x358 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 CLEAR3 26 18 10 2 CLEAR2 25 17 9 1 CLEAR1 24 16 8 0 CLEAR0 * CLEAR[3:0]: Interrupt Clear 0 = No effect 1 = Clear interrupt Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Each Interrupt Clear register has a bit allocated per channel, for example, ClearTfr[2] is the clear bit for Channel 2's transfer complete interrupt. Writing a 0 has no effect. These registers are not readable. 358 32072A-AVR32-03/09 AT32UC3A3 20.12.15 Combined Interrupt Status Registers Name: StatusInt Access Type: Offset: Reset Value: Read-only 0x360 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 ERR 27 19 11 3 DSTT 26 18 10 2 SRCT 25 17 9 1 BLOCK 24 16 8 0 TFR The contents of each of the five Status Registers (StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr) is OR'ed to produce a single bit per interrupt type in the Combined Status Register (StatusInt). * ERR OR of the contents of StatusErr Register. * DSTT OR of the contents of StatusDstTran Register. * SRCT OR of the contents of StatusSrcTran Register. * BLOCK OR of the contents of StatusBlock Register. * TFR OR of the contents of StatusTfr Register. 359 32072A-AVR32-03/09 AT32UC3A3 20.12.16 Source Software Transaction Request Register Name: ReqSrcReg Access Type: Offset: Reset Value: Read/write 0x368 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 REQ_WE3 3 SRC_REQ3 26 18 10 REQ_WE2 2 SRC_REQ2 25 17 9 REQ_WE1 1 SRC_REQ1 24 16 8 REQ_WE0 0 SRC_REQ0 A bit is assigned for each channel in this register. ReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer. For example, writing 0x101 writes a 1 into ReqSrcReg[0], while ReqSrcReg[4:1] remains unchanged. Writing hex 0x0yy leaves ReqSrcReg[4:0] unchanged. This allows software to set a bit in the ReqSrcReg register without performing a readmodified write * REQ_WE[11:8]: Request write enable 0 = Write disabled 1 = Write enabled * SRC_REQ[3:0]: Source request 360 32072A-AVR32-03/09 AT32UC3A3 20.12.17 Destination Software Transaction Request Register Name: ReqDstReg Access Type: Offset: Reset Value: Read/write 0x370 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 REQ_WE3 3 DST_REQ3 26 18 10 REQ_WE2 2 DST_REQ2 25 17 9 REQ_WE1 1 DST_REQ1 24 16 8 REQ_WE0 0 DST_REQ0 A bit is assigned for each channel in this register. ReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel DST_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer. * REQ_WE[11:8]: Request write enable 0 = Write disabled 1 = Write enabled * DST_REQ[3:0]: Destination request 361 32072A-AVR32-03/09 AT32UC3A3 20.12.18 Single Source Transaction Request Register Name: SglReqSrcReg Access Type: Offset: Reset Value: Read/write 0x378 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 REQ_WE3 3 S_SG_REQ3 26 18 10 REQ_WE2 2 S_SG_REQ2 25 17 9 REQ_WE1 1 S_SG_REQ1 24 16 8 REQ_WE0 0 S_SG_REQ0 A bit is assigned for each channel in this register. SglReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer. * REQ_WE[11:8]: Request write enable 0 = Write disabled 1 = Write enabled * S_SG_REQ[3:0]: Source single request 362 32072A-AVR32-03/09 AT32UC3A3 20.12.19 Single Destination Transaction Request Register Name: SglReqDstReg Access Type: Offset: Reset Value: Read/write 0x380 0x0000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 REQ_WE3 3 D_SG_REQ3 26 18 10 REQ_WE2 2 D_SG_REQ2 25 17 9 REQ_WE1 1 D_SG_REQ1 24 16 8 REQ_WE0 0 D_SG_REQ0 A bit is assigned for each channel in this register. SglReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer. * REQ_WE[11:8]: Request write enable 0 = Write disabled 1 = Write enabled * D_SG_REQ[3:0]: Destination single request 363 32072A-AVR32-03/09 AT32UC3A3 20.12.20 Last Source Transaction Request Register Name: LstSrcReg Access Type: Offset: Reset Value: Read/write 0x388 0x0000000 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 11 LSTSRC_W E3 3 LSTSRC3 26 18 10 LSTSRC_W E2 2 LSTSRC2 25 17 9 LSTSRC_W E1 1 LSTSRC1 24 16 8 LSTSRC_W E0 0 LSTSRC0 7 - 6 - 5 - 4 - A bit is assigned for each channel in this register. LstSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSRC_WE field is asserted on the same System Bus write transfer. * LSTSRC_WE[11:8]: Source Last Transaction request write enable 0 = Write disabled 1 = Write enabled * LSTSRC[3:0]: Source Last Transaction request 364 32072A-AVR32-03/09 AT32UC3A3 20.12.21 Last Destination Transaction Request Register Name: LstDstReg Access Type: Offset: Reset Value: Read/write 0x390 0x00000000 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 11 LSTDST_WE 3 3 LSTDST3 26 18 10 LSTDST_WE 2 2 LSTDST2 25 17 9 LSTDST_WE 1 1 LSTDST1 24 16 8 LSTDST_WE 0 0 LSTDST0 7 - 6 - 5 - 4 - A bit is assigned for each channel in this register. LstDstReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDST_WE field is asserted on the same System Bus write transfer. * LSTDST_WE[11:8]: Destination Last Transaction request write enable 0 = Write disabled 1 = Write enabled * LSTDST[3:0]: Destination Last Transaction request 365 32072A-AVR32-03/09 AT32UC3A3 20.12.22 DMA Configuration Register Name: DmaCfgReg Access Type: Offset: Reset Value: Read/Write 0x398 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 DMA_EN * DMA_EN: DMA Controller Enable 0 = DMACA Disabled 1 = DMACA Enabled. This register is used to enable the DMACA, which must be done before any channel activity can begin. If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns `1' to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the DmaCfgReg.DMA_EN bit returns `0'. 366 32072A-AVR32-03/09 AT32UC3A3 20.12.23 DMA Channel Enable Register Name: ChEnReg Access Type: Offset: Reset Value: Read/Write 0x3A0 0x00000000 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 11 CH_EN_WE 3 3 CH_EN3 26 18 10 CH_EN_WE 2 2 CH_EN2 25 17 9 CH_EN_WE 1 1 CH_EN1 24 16 8 CH_EN_WE 0 0 CH_EN0 7 - 6 - 5 - 4 - * CH_EN_WE[11:8]: Channel Enable Write Enable The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on the same System Bus write transfer. For example, writing 0x101 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged. * CH_EN[3:0] 0 = Disable the Channel 1 = Enable the Channel Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer has completed. 367 32072A-AVR32-03/09 AT32UC3A3 20.12.24 DMACA Component Id Register Low Name: DmaCompIdRegL Access Type: Offset: Reset Value: Read-only 0x3F8 0x44571110 31 30 29 28 27 26 25 24 DMA_COMP_TYPE[31:24] 23 22 21 20 19 18 17 16 DMA_COMP_TYPE[23:16] 15 14 13 12 11 10 9 8 DMA_COMP_TYPE[15:8] 7 6 5 4 3 2 1 0 DMA_COMP_TYPE[7:0] * DMA_COMP_TYPE DesignWare component type number = 0x44571110. This assigned unique hex value is constant and is derived from the two ASCII letters "DW" followed by a 32-bit unsigned number 368 32072A-AVR32-03/09 AT32UC3A3 20.12.25 DMACA Component Id Register High Name: DmaCompIdRegH Access Type: Offset: Reset Value: Read-only 0x3FC 0x3230362A 31 30 29 28 27 26 25 24 DMA_COMP_VERSION[31:24] 23 22 21 20 19 18 17 16 DMA_COMP_VERSION[23:16] 15 14 13 12 11 10 9 8 DMA_COMP_VERSION[15:8] 7 6 5 4 3 2 1 0 DMA_COMP_VERSION[7:0] * DMA_COMP_VERSION: Version of the component 369 32072A-AVR32-03/09 AT32UC3A3 20.13 Module Configuration The following table defines the valid settings for the DEST_PER and SRC_PER fields in the CFGxH register. Table 20-6. PER Value 0 1 2 3 4 5 6 7 DMACA Handshake Interfaces Hardware Handshaking Interface AES - RX AES - TX MCI - RX MCI -TX MSI - RX MSI - TX EXTRQ0 EXTRQ1 370 32072A-AVR32-03/09 AT32UC3A3 21. General-Purpose Input/Output Controller (GPIO) Rev: 1.1.0.4 21.1 Features * * * * * Each I/O line of the GPIO features: Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line A glitch filter providing rejection of pulses shorter than one clock cycle Input visibility and output control Multiplexing of up to four peripheral functions per I/O line Programmable internal pull-up resistor 21.2 Overview The General Purpose Input/Output Controller manages the I/O pins of the microcontroller. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. 21.3 Block Diagram Figure 21-1. GPIO Block Diagram PB Configuration Interface GPIO Interrupt Request Interrupt Controller PIN PIN PIN PIN PIN MCU I/O Pins General Purpose Input/Output - GPIO CLK_GPIO Power Manager Embedded Peripheral Pin Control Signals 21.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.4.1 Module Configuration Most of the features of the GPIO are configurable for each product. The user must refer to the Package and Pinout chapter for these settings. Product specific settings includes: * Number of I/O pins. * Functions implemented on each pin 371 32072A-AVR32-03/09 AT32UC3A3 * Peripheral function(s) multiplexed on each I/O pin * Reset state of registers 21.4.2 Clocks The clock for the GPIO bus interface (CLK_GPIO) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The CLK_GPIO must be enabled in order to access the configuration registers of the GPIO or to use the GPIO interrupts. After configuring the GPIO, the CLK_GPIO can be disabled if interrupts are not used. 21.4.3 Interrupts The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt requires the interrupt controller to be configured first. 21.5 Functional Description The GPIO controls the I/O lines of the microcontroller. The control logic associated with each pin is represented in the figure below: Figure 21-2. Overview of the GPIO Pad Connections ODER PUER 1 Periph. A output enable Periph. B output enable 0 Periph. C output enable Periph. D output enable PMR1 GPER PMR0 Periph. A output data Periph. B output data Periph. C output data Periph. D output data 0 PAD OVR 1 Periph. A input data Periph. B input data Periph. C input data Periph. D input data IER 0 Edge Detector 1 Interrupt Request PVR 1 Glitch Filter IMR1 GFER IMR0 0 372 32072A-AVR32-03/09 AT32UC3A3 21.5.1 21.5.1.1 Basic Operation I/O Line or peripheral function selection When a pin is multiplexed with one or more peripheral functions, the selection is controlled with the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is controlled by the GPIO. If a bit is written to zero, the corresponding pin is controlled by a peripheral function. Peripheral selection The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by accessing Peripheral Mux Register 0 (PMR0) and Peripheral Mux Register 1 (PMR1). Output control When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is written to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on the value in PMR0 and PMR1, determines whether the pin is driven or not. When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register (ODER) determines if the pin is driven or not. When a bit in this register is written to one, the corresponding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not drive the line. The level driven on an I/O line can be determined by writing to the Output Value Register (OVR). 21.5.1.4 Inputs The level on each I/O line can be read through the Pin Value Register (PVR). This register indicates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an external component. Note that due to power saving measures, the PVR register can only be read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin. 21.5.1.5 Output line timings The figure below shows the timing of the I/O line when writing a one and a zero to OVR. The same timing applies when performing a `set' or `clear' access, i.e., writing a one to the Output Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is also shown. Figure 21-3. Output Line Timings CLK_GPIO 21.5.1.2 21.5.1.3 Write OVR to 1 PB Access Write OVR to 0 PB Access OVR / I/O Line PVR 373 32072A-AVR32-03/09 AT32UC3A3 21.5.2 21.5.2.1 Advanced Operation Pull-up resistor control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register (PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a peripheral or the GPIO. Input glitch filter Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with duration of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock cycles, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces 2 clock cycles of latency. The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit is written to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters. 21.5.3 Interrupts The GPIO can be configured to generate an interrupt when it detects an input change on an I/O line. The module can be configured to signal an interrupt whenever a pin changes value or only to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1). Interrupts can be enabled on a pin, regardless of the configuration of the I/O line, i.e. whether it is controlled by the GPIO or assigned to a peripheral function. In every port there are four interrupt lines connected to the interrupt controller. Groups of eight interrupts in the port are ORed together to form an interrupt line. When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to one, the GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired together to generate a single interrupt signal to the interrupt controller. The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt. The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC). GPIO interrupts can only be triggered when the CLK_GPIO is enabled. 21.5.4 Interrupt Timings The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In this example, this is not the case for the first pulse. The second pulse is however sampled on a rising edge and will trigger an interrupt request. 21.5.2.2 374 32072A-AVR32-03/09 AT32UC3A3 Figure 21-4. Interrupt Timing With Glitch Filter Disabled clock Pin Level GPIO_IFR The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In the example, the first pulse is rejected while the second pulse is accepted and causes an interrupt request. Figure 21-5. Interrupt Timing With Glitch Filter Enabled clock Pin Level GPIO_IFR 375 32072A-AVR32-03/09 AT32UC3A3 21.6 User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32bit ports that are configurable through a PB interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports are product specific. Figure 21-6. Overall Mermory Map 0x0000 Port 0 Configuration Registers 0x0100 Port 1 Configuration Registers 0x0200 Port 2 Configuration Registers 0x0300 Port 3 Configuration Registers 0x0400 Port 4 Configuration Registers In the GPIO Controller Function Multiplexingtable in the Package and Pinout chapter, each GPIO line has a unique number. Note that the PA, PB, PC and PX ports do not directly correspond to the GPIO ports. To find the corresponding port and pin the following formula can be used: GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1 GPIO pin = GPIO number mod 32, example: 36 mod 32 = 4 The table below shows the configuration registers for one port. Addresses shown are relative to the port address offset. The specific address of a configuration register is found by adding the 376 32072A-AVR32-03/09 AT32UC3A3 register offset and the port offset to the GPIO start address. One bit in each of the configuration registers corresponds to an I/O pin. Table 21-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5c 0x60 0x70 0x74 0x78 0x7C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 GPIO Register Memory Map Register GPIO Enable Register GPIO Enable Register GPIO Enable Register GPIO Enable Register Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 1 Peripheral Mux Register 1 Peripheral Mux Register 1 Peripheral Mux Register 1 Function Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Name GPER GPERS GPERC GPERT PMR0 PMR0S PMR0C PMR0T PMR1 PMR1S PMR1C PMR1T ODER ODERS ODERC ODERT OVR OVRS OVRC OVRT PVR PUER PUERS PUERC PUERT IER IERS IERC IERT IMR0 IMR0S IMR0C IMR0T IMR1 Access Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read-Only Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read/Write Reset value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Output Driver Enable Register Output Driver Enable Register Output Driver Enable Register Output Driver Enable Register Output Value Register Output Value Register Output Value Register Output Value Register Pin Value Register Pull-up Enable Register Pull-up Enable Register Pull-up Enable Register Pull-up Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 1 377 32072A-AVR32-03/09 AT32UC3A3 Table 21-1. Offset 0xB4 0xB8 0xBC 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC Note: GPIO Register Memory Map Register Interrupt Mode Register 1 Interrupt Mode Register 1 Interrupt Mode Register 1 Glitch Filter Enable Register Glitch Filter Enable Register Glitch Filter Enable Register Glitch Filter Enable Register Interrupt Flag Register Interrupt Flag Register Interrupt Flag Register Interrupt Flag Register Function Set Clear Toggle Read/Write Set Clear Toggle Read Clear Name IMR1S IMR1C IMR1T GFER GFERS GFERC GFERT IFR IFRC Access Write-Only Write-Only Write-Only Read/Write Write-Only Write-Only Write-Only Read-Only Write-Only Reset value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 1. The reset value is undefined depending on the pin states. 21.6.1 Access Types Each configuration register can be accessed in four different ways. The first address location can be used to write the register directly. This address can also be used to read the register value. The following addresses facilitate three different types of write access to the register. Performing a "set" access, all bits written to one will be set. Bits written to zero will be unchanged by the operation. Performing a "clear" access, all bits written to one will be cleared. Bits written to zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits written to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. 378 32072A-AVR32-03/09 AT32UC3A3 21.6.2 Name: Enable Register GPER Read, Write, Set, Clear, Toggle 0x00, 0x04, 0x08, 0x0C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pin Enable 0: A peripheral function controls the corresponding pin. 1: The GPIO controls the corresponding pin. 379 32072A-AVR32-03/09 AT32UC3A3 21.6.3 Name: Peripheral Mux Register 0 PMR0 Read, Write, Set, Clear, Toggle 0x10, 0x14, 0x18, 0x1C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Peripheral Multiplexer Select bit 0 380 32072A-AVR32-03/09 AT32UC3A3 21.6.4 Name: Peripheral Mux Register 1 PMR1 Read, Write, Set, Clear, Toggle 0x20, 0x24, 0x28, 0x2C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Peripheral Multiplexer Select bit 1 {PMR1, PMR0} 00 01 10 11 Selected Peripheral Function A B C D 381 32072A-AVR32-03/09 AT32UC3A3 21.6.5 Name: Output Driver Enable Register ODER Read, Write, Set, Clear, Toggle 0x40, 0x44, 0x48, 0x4C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Output Driver Enable 0: The output driver is disabled for the corresponding pin. 1: The output driver is enabled for the corresponding pin. 382 32072A-AVR32-03/09 AT32UC3A3 21.6.6 Name: Output Value Register OVR Read, Write, Set, Clear, Toggle 0x50, 0x54, 0x58, 0x5C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Output Value 0: The value to be driven on the I/O line is 0. 1: The value to be driven on the I/O line is 1. 383 32072A-AVR32-03/09 AT32UC3A3 21.6.7 Name: Pin Value Register PVR Read 0x60, 0x64, 0x68, 0x6C 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Pin Value 0: The I/O line is at level `0'. 1: The I/O line is at level `1'. Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin. 384 32072A-AVR32-03/09 AT32UC3A3 21.6.8 Name: Pull-up Enable Register PUER Read, Write, Set, Clear, Toggle 0x70, 0x74, 0x78, 0x7C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Pull-up Enable 0: The internal pull-up resistor is disabled for the corresponding pin. 1: The internal pull-up resistor is enabled for the corresponding pin. 385 32072A-AVR32-03/09 AT32UC3A3 21.6.9 Name: Interrupt Enable Register IER Read, Write, Set, Clear, Toggle 0x90, 0x94, 0x98, 0x9C 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin. 1: Interrupt is enabled for the corresponding pin. 386 32072A-AVR32-03/09 AT32UC3A3 21.6.10 Name: Interrupt Mode Register 0 IMR0 Read, Write, Set, Clear, Toggle 0xA0, 0xA4, 0xA8, 0xAC 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Interrupt Mode Bit 0 387 32072A-AVR32-03/09 AT32UC3A3 21.6.11 Name: Interrupt Mode Register 1 IMR1 Read, Write, Set, Clear, Toggle 0xB0, 0xB4, 0xB8, 0xBC 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Interrupt Mode Bit 1 {IMR1, IMR0} 00 01 10 11 Interrupt Mode Pin Change Rising Edge Falling Edge Reserved 388 32072A-AVR32-03/09 AT32UC3A3 21.6.12 Name: Glitch Filter Enable Register GFER Read, Write, Set, Clear, Toggle 0xC0, 0xC4, 0xC8, 0xCC 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin. 1: Glitch filter is enabled for the corresponding pin. NOTE! The value of this register should only be changed when IER is `0'. Updating this GFER while interrupt on the corresponding pin is enabled can cause an unintentional interrupt to be triggered. 389 32072A-AVR32-03/09 AT32UC3A3 21.6.13 Name: Interrupt Flag Register IFR Read, Clear 0xD0, 0xD8 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-31: Interrupt Flag 1: An interrupt condition has been detected on the corresponding pin. 0: No interrupt condition has beedn detected on the corresponding pin since reset or the last time it was cleared. The number of interrupt request lines is dependant on the number of I/O pins on the MCU. Refer to the product specific data for details. Note also that a bit in the Interrupt Flag register is only valid if the corresponding bit in IER is set. 390 32072A-AVR32-03/09 AT32UC3A3 21.7 21.7.1 Programming Examples 8-bit LED-Chaser // Set R0 to GPIO base address mov orh R0, LO(AVR32_GPIO_ADDRESS) R0, HI(AVR32_GPIO_ADDRESS) // Enable GPIO control of pin 0-8 mov st.w R1, 0xFF R0[AVR32_GPIO_GPERS], R1 // Set initial value of port mov st.w R2, 0x01 R0[AVR32_GPIO_OVRS], R2 // Set up toggle value. Two pins are toggled // in each round. The bit that is currently set, // and the next bit to be set. mov orh R2, 0x0303 R2, 0x0303 loop: // Only change 8 LSB mov and st.w rol rcall rjmp R3, 0x00FF R3, R2 R0[AVR32_GPIO_OVRT], R3 R2 delay loop It is assumed in this example that a subroutine "delay" exists that returns after a given time. 21.7.2 Configuration of USART pins The example below shows how to configure a peripheral module to control I/O pins. It assumed in this example that the USART receive pin (RXD) is connected to PC16 and that the USART transmit pin (TXD) is connected to PC17. For both pins, the USART is peripheral B. In this example, the state of the GPIO registers is assumed to be unknown. The two USART pins are therefore first set to be controlled by the GPIO with output drivers disabled. The pins can then be assured to be tri-stated while changing the Peripheral Mux Registers. // Set up pointer to GPIO, PORTC mov orh R0, LO(AVR32_GPIO_ADDRESS + PORTC_OFFSET) R0, HI(AVR32_GPIO_ADDRESS + PORTC_OFFSET) // Disable output drivers 391 32072A-AVR32-03/09 AT32UC3A3 mov orh st.w R1, 0x0000 R1, 0x0003 R0[AVR32_GPIO_ODERC], R1 // Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS], R1 // Select peripheral B on PC16-PC17 st.w st.w R0[AVR32_GPIO_PMR0S], R1 R0[AVR32_GPIO_PMR1C], R1 // Enable peripheral control st.w R0[AVR32_GPIO_GPERC], R1 392 32072A-AVR32-03/09 AT32UC3A3 22. Serial Peripheral Interface (SPI) Rev. 2.1.0.1 22.1 Features * Compatible with an embedded 32-bit microcontroller * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors - External co-processors * Master or Slave Serial Peripheral Bus Interface - 4 - to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Connection to Peripheral DMA Controller channel capabilities optimizes data transfers - One channel for the receiver, one channel for the transmitter - Next buffer support - Four character FIFO in reception 22.2 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: * Master Out Slave In (MOSI): this data line supplies the output data from the master shifted into the input(s) of the slave(s). * Master In Slave Out (MISO): this data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. * Serial Clock (SPCK): this control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. * Slave Select (NSS): this control line allows slaves to be turned on and off by hardware. 393 32072A-AVR32-03/09 AT32UC3A3 22.3 Block Diagram Figure 22-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI Spi Interface I/O Controller MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 SPI Interrupt Interrupt Control 22.4 Application Block Diagram Figure 22-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI Spi Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 2 394 32072A-AVR32-03/09 AT32UC3A3 22.5 I/O Lines Description Table 22-1. I/O Lines Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input 22.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 22.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first configure the I/O Controller to assign the SPI pins to their peripheral functions. 22.6.2 Clocks The clock for the SPI bus interface (CLK_SPI) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SPI before disabling the clock, to avoid freezing the SPI in an undefined state. 22.6.3 Interrupts The SPI interrupt request line is connected to the interrupt controller. Using the SPI interrupt requires the interrupt controller to be programmed first. 22.7 22.7.1 Functional Description Modes of Operation The SPI operates in master mode or in slave mode. Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the Mode Register (MR.MSTR). The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in master mode. 395 32072A-AVR32-03/09 AT32UC3A3 22.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled. Each of the two bits has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 22-2 on page 396 shows the four modes and corresponding parameter settings. Table 22-2. SPI modes SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 22-3 on page 396 and Figure 22-4 on page 397 show examples of data transfers. Figure 22-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB *** NSS (to slave) *** Not Defined, but normaly MSB of previous character received 396 32072A-AVR32-03/09 AT32UC3A3 Figure 22-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) *** MSB 6 5 4 3 2 1 LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 22.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register (TDR) and the Receive Data Register (RDR), and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the TDR register. The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing to the TDR, the Peripheral Chip Select field in TDR (TDR.PCS) must be written in order to select a slave. If new data is written to TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in TDR in the Shift Register is indicated by the Transmit Data Register Empty bit in the Status Register (SR.TDRE). When new data is written in TDR, this bit is cleared. The SR.TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel. The end of transfer is indicated by the Transmission Registers Empty bit in the SR register (SR.TXEMPTY). If a transfer delay (CSRn.DLYBCT) is greater than zero for the last transfer, SR.TXEMPTY is set after the completion of said delay. The CLK_SPI can be switched off at this time. During reception, received data are transferred from the Shift Register to the reception FIFO. The FIFO can contain up to 4 characters (both Receive Data and Peripheral Chip Select fields). While a character of the FIFO is unread, the Receive Data Register Full bit in SR remains high (SR.RDRF). Characters are read through the RDR register. If the four characters stored in the FIFO are not read and if a new character is stored, this sets the Overrun Error Status bit in the SR register (SR.OVRES). The procedure to follow in such a case is described in Section 22.7.3.8. 397 32072A-AVR32-03/09 AT32UC3A3 In master mode, if the received data is not read fast enough compared to the transfer rhythm imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is enabled. To insure a perfect data integrity of received data (especially at high data rate), the mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When this mode is activated, no transfer starts while received data remains unread in the RDR. When data is written to the TDR and if unread received data is stored in the RDR, the transfer is paused until the RDR is read. In this mode no overrun error can occur. Please note that if this mode is enabled, it is useless to activate the FIFO in reception. Figure 22-5 on page 398shows a block diagram of the SPI when operating in master mode. Figure 22-6 on page 399 shows a flow chart describing how transfers are handled. 22.7.3.1 Master mode block diagram Figure 22-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDR RD RDRF OVRES CSR0..3 BITS NCPHA CPOL MISO LSB Shift Register 0 1 MSB 4 - Character FIFO MOSI TDR TD TDRE RXFIFOEN RDR PCS CSR0..3 CSNAAT PS MR PCS 0 TDR PCS 1 Current Peripheral NPCS2 NPCS1 NPCS0 PCSDEC CSAAT 0 1 4 - Character FIFO NPCS3 MSTR MODF NPCS0 MODFDIS 398 32072A-AVR32-03/09 AT32UC3A3 22.7.3.2 Master mode flow diagram Figure 22-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes MR(PCS) = NPCS ? no NPCS = 0xF 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = MR(PCS) Fixed peripheral 1 TDR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = TDR(PCS) NPCS = MR(PCS), TDR(PCS) Delay DLYBS Serializer = TDR(TD) TDRE = 1 Data Transfer RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 399 32072A-AVR32-03/09 AT32UC3A3 22.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be configured in the CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 22.7.3.4 Transfer delays Figure 22-7 on page 400 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be configured to modify the transfer waveforms: * The delay between chip selects, programmable only once for all the chip selects by writing to the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a delay between release of one chip select and before assertion of a new one. * The delay before SPCK, independently programmable for each chip select by writing the Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to be delayed after the chip select has been asserted. * The delay between consecutive transfers, independently programmable for each chip select by writing the Delay Between Consecutive Transfers field in the CSRn registers (CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 22-7. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 400 32072A-AVR32-03/09 AT32UC3A3 22.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: * Fixed Peripheral Select: SPI exchanges data with only one peripheral * Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.PS). In this case, the current peripheral is defined by the MR.PCS field and the TDR.PCS field has no effect. Variable Peripheral Select is activated by writing a one to the MR.PS bit . The TDR.PCS field is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Peripheral DMA Controller is an optimal means, as the size of the data transfer between the memory and the SPI is either 4 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the MR register. Data written to TDR is 32-bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the CSRn registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 22.7.3.6 Peripheral chip select decoding The user can configure the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing a one to the Chip Select Decode bit in the MR register (MR.PCSDEC). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the MR register or the TDR register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at one) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, the CRS0 register defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 22.7.3.7 Peripheral deselection When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding 401 32072A-AVR32-03/09 AT32UC3A3 to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as soon as the content of the TDR is transferred into the internal shifter. When this bit is detected the TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Not Active After Transfer bit (CSRn.CSNAAT) written to one. This allows to de-assert systematically the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into account only if the CSRn.CSAAT bit is written to zero for the same Chip Select). Figure 22-8 on page 403 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 22.7.3.8 FIFO management A FIFO has been implemented in Reception FIFO (both in master and in slave mode), in order to be able to store up to 4 characters without causing an overrun error. If an attempt is made to store a fifth character, an overrun error rises. If such an event occurs, the FIFO must be flushed. There are two ways to Flush the FIFO: * By performing four read accesses of the RDR (the data read must be ignored) * By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO). After that, the SPI is able to receive new data. 402 32072A-AVR32-03/09 AT32UC3A3 Figure 22-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 DLYBCT TDRE CSAAT = 0 and CSNAAT = 1 DLYBCT NPCS[0..3] A A A DLYBCS A PCS = A Write TDR PCS = A Figure 22-8 on page 403 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 22.7.3.9 Mode fault detection A mode fault is detected when the SPI is configured in master mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the I/O Controller, so that external pull up resistors are needed to guarantee high level. 403 32072A-AVR32-03/09 AT32UC3A3 When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the Spi Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled. The user can disable mode fault detection by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS). 22.7.4 SPI Slave Mode When operating in slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are processed following a phase and a polarity defined respectively by the CSR0.NCPHA and CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers have no effect when the SPI is configured in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the SR.RDRF bit rises. If the RDR register has not been read before new data is received, the SR.OVRES bit is set. As long as this bit is set, data is loaded in RDR. The user has to read the SR register to clear the SR.OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the TDR register, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets to zero. When a first data is written in TDR, it is transferred immediately in the Shift Register and the SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to be transmitted, i.e. no character has been written in TDR since the last load from TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. In this case the Underrun Error Status bit is set in SR (SR.UNDES). Figure 22-9 on page 405 shows a block diagram of the SPI when operating in slave mode. 404 32072A-AVR32-03/09 AT32UC3A3 Figure 22-9. Slave Mode Functional Block Diagram SPCK NSS SPIEN SPIENS SPIDIS CSR0 BITS NCPHA CPOL MOSI LSB Shift Register 0 1 MSB 4 - Character FIFO RXFIFOEN RDR RD RDRF OVRES SPI Clock MISO TDR TD UNDES TDRE 405 32072A-AVR32-03/09 AT32UC3A3 22.8 User Interface SPI Register Memory Map Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Write Protection Control Register Write Protection Status Register Version Register Register Name CR MR RDR TDR SR IER IDR IMR CSR0 CSR1 CSR2 CSR3 WPCR WPSR VERSION Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x000000F0 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0X00000000 0x00000000 - (1) Table 22-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x30 0x34 0x38 0x3C 0x E4 0xE8 0xFC Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 406 32072A-AVR32-03/09 AT32UC3A3 22.8.1 Name: Control Register CR Write-only 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 LASTXFER 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 FLUSHFIFO 7 SWRST 6 - 5 - 4 - 3 - 2 - 1 SPIDIS 0 SPIEN * LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. * FLUSHFIFO: Flush Fifo Command 1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to empty the FIFO. 0: Writing a zero to this bit has no effect. * SWRST: SPI Software Reset 1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset. 0: Writing a zero to this bit has no effect. * SPIDIS: SPI Disable 1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled. 0: Writing a zero to this bit has no effect. * SPIEN: SPI Enable 1: Writing a one to this bit will enable the SPI to transfer and receive data. 0: Writing a zero to this bit has no effect. 407 32072A-AVR32-03/09 AT32UC3A3 22.8.2 Name: Mode Register MR Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCS 27 26 25 24 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 LLB 6 RXFIFOEN 5 WDRBT 4 MODFDIS 3 - 2 PCSDEC 1 PS 0 MSTR * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default. Otherwise, the following equation determines the delay: Delay Between Chip Selects = DLYBCS ---------------------CLKSPI * PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. * LLB: Local Loopback Enable 1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is internally connected on MOSI). 0: Local loopback path disabled. * RXFIFOEN: FIFO in Reception Enable 1: The FIFO is used in reception (four characters can be stored in the SPI). 408 32072A-AVR32-03/09 AT32UC3A3 0: The FIFO is not used in reception (only one character can be stored in the SPI). * WDRBT: Wait Data Read Before Transfer 1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception. 0: No Effect. In master mode, a transfer can be initiated whatever the state of the RDR register is. * MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. 0: Mode fault detection is enabled. * PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The CSRn registers define the characteristics of the 15 chip selects according to the following rules: CSR0 defines peripheral chip select signals 0 to 3. CSR1 defines peripheral chip select signals 4 to 7. CSR2 defines peripheral chip select signals 8 to 11. CSR3 defines peripheral chip select signals 12 to 14. * PS: Peripheral Select 1: Variable Peripheral Select. 0: Fixed Peripheral Select. * MSTR: Master/Slave Mode 1: SPI is in master mode. 0: SPI is in slave mode. 409 32072A-AVR32-03/09 AT32UC3A3 22.8.3 Name: Receive Data Register RDR Read-only 0x08 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 14 13 12 RD[15:8] 11 10 9 8 7 6 5 4 RD[7:0] 3 2 1 0 * PCS: Peripheral Chip Select In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. * RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. 410 32072A-AVR32-03/09 AT32UC3A3 22.8.4 Name: Transmit Data Register TDR Write-only 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 LASTXFER 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 14 13 12 TD[15:8] 11 10 9 8 7 6 5 4 TD[7:0] 3 2 1 0 * LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. This field is only used if Variable Peripheral Select is active (MR.PS = 1). * PCS: Peripheral Chip Select If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS This field is only used if Variable Peripheral Select is active (MR.PS = 1). * TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the TDR register in a right-justified format. 411 32072A-AVR32-03/09 AT32UC3A3 22.8.5 Name: Status Register SR Read-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 SPIENS 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF * SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled. * UNDES: Underrun Error Status (Slave Mode Only) 1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register. 0: This bit is cleared when the SR register is read. * TXEMPTY: Transmission Registers Empty 1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. 0: This bit is cleared as soon as data is written in TDR. * NSSR: NSS Rising 1: A rising edge occurred on NSS pin since last read. 0: This bit is cleared when the SR register is read. * OVRES: Overrun Error Status 1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR. 0: This bit is cleared when the SR register is read. * MODF: Mode Fault Error 1: This bit is set when a Mode Fault occurred. 0: This bit is cleared when the SR register is read. * TDRE: Transmit Data Register Empty 1: This bit is set when the last data written in the TDR register has been transferred to the serializer. 0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * RDRF: Receive Data Register Full 1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR. 0: No data has been received since the last read of RDR 412 32072A-AVR32-03/09 AT32UC3A3 22.8.6 Name: Interrupt Enable Register IER Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 413 32072A-AVR32-03/09 AT32UC3A3 22.8.7 Name: Interrupt Disable Register IDR Write-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 414 32072A-AVR32-03/09 AT32UC3A3 22.8.8 Name: Interrupt Mask Register IMR Read-only 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 415 32072A-AVR32-03/09 AT32UC3A3 22.8.9 Name: Chip Select Register 0 CSR0 Read/Write 0x30 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 416 32072A-AVR32-03/09 AT32UC3A3 * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved * CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. * CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI * NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 417 32072A-AVR32-03/09 AT32UC3A3 22.8.10 Name: Chip Select Register 1 CSR1 Read/Write 0x34 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 418 32072A-AVR32-03/09 AT32UC3A3 * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved * CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. * CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI * NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 419 32072A-AVR32-03/09 AT32UC3A3 22.8.11 Name: Chip Select Register 2 CSR2 Read/Write 0x38 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 420 32072A-AVR32-03/09 AT32UC3A3 * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved * CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. * CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI * NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 421 32072A-AVR32-03/09 AT32UC3A3 22.8.12 Name: Chip Select Register 3 CSR3 Read/Write 0x3C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 422 32072A-AVR32-03/09 AT32UC3A3 * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved * CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. * CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI * NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 423 32072A-AVR32-03/09 AT32UC3A3 22.8.13 Write Protection Control Register Register Name: WPCR Access Type: Offset: Reset Value: Read-write 0xE4 0x00000000 31 30 29 28 27 26 25 24 SPIWPKEY[23:16] 23 22 21 20 19 18 17 16 SPIWPKEY[15:8] 15 14 13 12 11 10 9 8 SPIWPKEY[7:0] 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SPIWPEN * SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with "SPI" (SPI written in ASCII Code, i.e. 0x535049 in hexadecimal). * SPIWPEN: SPI Write Protection Enable 1: The Write Protection is Enabled 0: The Write Protection is Disabled 424 32072A-AVR32-03/09 AT32UC3A3 22.8.14 Write Protection Status Register Register Name: WPSR Access Type: Offset: Reset Value: Read-only 0xE8 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 SPIWPVSRC 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 1 SPIWPVS 0 * SPIWPVSRC: SPI Write Protection Violation Source This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx) * SPIWPVS: SPI Write Protection Violation Status SPIWPVS value 1 2 3 4 Violation Type The Write Protection has blocked a Write access to a protected register (since the last read). Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. The Write Protection has blocked a Write access to a protected register and write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx) and some write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. - The Write Protection has blocked a Write access to a protected register. and - Software Reset has been performed while Write Protection was enabled. and - Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select "i" was active) since the last read. 5 6 7 425 32072A-AVR32-03/09 AT32UC3A3 22.8.15 Version Register Register Name: VERSION Access Type: Offset: Reset Value: Read-only 0xFC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 14 13 12 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT Reserved. No functionality associated. * VERSION Version number of the module. No functionality associated. 426 32072A-AVR32-03/09 AT32UC3A3 22.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager section for details. Table 22-4. Module Name SPI0 SPI1 Module Clock Name Clock Name CLK_SPI0 CLK_SPI1 Table 22-5. Register VERSION Register Reset Values Reset Value 0x00000200 427 32072A-AVR32-03/09 AT32UC3A3 23. Two-Wire Slave Interface (TWIS) Rev 1.0.0.1 23.1 Features * Compatible with IC standard - 100 and 400 kbit/s transfer speeds - 7 and 10-bit and General Call addressing Compatible with SMBus standard - Hardware Packet Error Checking (CRC) generation and verification with ACK response - SMBALERT interface - 25 ms clock low timeout delay - 25 ms slave cumulative clock low extend time Compatible with PMBus DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer 32-bit Peripheral Bus interface for configuration of the interface * * * * * * 23.2 Overview The Atmel Two-wire Interface Slave (TWIS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus IC or SMBus compatible master. TWIS is always a bus slave and can transfer sequential or single bytes. Below, Table 23-1 on page 428 lists the compatibility level of the Atmel Two-wire Slave Interface and a full IC compatible device. Table 23-1. IC Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE(1) Repeated Start (Sr) Condition ACK and NAK Management Slope control and input filtering (Fast mode) Clock stretching Note: 1. START + b000000001 + Ack + Sr Atmel TWIS Compatibility with IC Standard Atmel TWIS Supported Supported Supported Not Supported Supported Supported Supported Supported 428 32072A-AVR32-03/09 AT32UC3A3 Below, Table 23-2 on page 429 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 23-2. Bus Timeouts Address Resolution Protocol Alert Packet Error Checking Atmel TWIS Compatibility with SMBus Standard Atmel TWIS Supported Supported Supported Supported SMBus Standard 23.3 List of Abbreviations Table 23-3. Abbreviation TWI A NA P S Sr SADR ADR R W Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address Any address except SADR Read Write 23.4 Block Diagram Figure 23-1. Block Diagram Peripheral Bus Bridge TWCK I/O controller Two-wire Interface CLK_TWIS TWI Interrupt Interrupt Controller TWD TWALM Power Manager 429 32072A-AVR32-03/09 AT32UC3A3 23.5 Application Block Diagram Figure 23-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI serial EEPROM Slave 1 IC RTC Slave 2 IC LCD controller Slave 3 IC temp. sensor Slave 4 Rp: Pull up value as given by the IC Standard 23.6 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock SMBus SMBALERT Type Input/Output Input/Output Input/Output Table 23-4. Pin Name TWD TWCK TWALM 23.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 23.7.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 23-2 on page 430). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. TWD, TWCK and TWALM pins may be multiplexed with I/O Controller lines. To enable the TWIS, the programmer must perform the following steps: * Program the I/O Controller to: - Dedicate TWD, TWCK and optionally TWALM as peripheral lines. - Define TWD, TWCK and optionally TWALM as open-drain. 23.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. 430 32072A-AVR32-03/09 AT32UC3A3 23.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 23.7.4 Interrupts The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS interrupts requires the interrupt controller to be programmed first. 23.7.5 Debug Operation When an external debugger forces the CPU into debug mode, the TWIS continues normal operation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 23.8 23.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4 on page 431). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 23-3 on page 431). * A high-to-low transition on the TWD line while TWCK is high defines the START condition. * A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 23-3. START and STOP Conditions TWD TWCK Start Stop Figure 23-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 23.8.2 Operation TWIS has two modes of operation: * Slave transmitter mode * Slave receiver mode 431 32072A-AVR32-03/09 AT32UC3A3 A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 23-5. Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 IC RTC Slave 2 IC LCD Controller Slave 3 IC Temp. Sensor Slave 4 Rp: Pull up value as given by the IC Standard 23.8.2.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by TWIS. TR describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling can be selected through TR.EXP. f CLK - TWIS f prescaled = -------------------------( EXP + 1 ) ) 2 TR has the following fields: TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT. TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. 432 32072A-AVR32-03/09 AT32UC3A3 Figure 23-6. Bus Timing Diagram t LOW t HIGH t LOW S t t HD:STA SU:DAT t HD:DAT t t SU:DAT SU:STO P t SU:STA Sr 23.8.2.2 Setting Up and Performing a Transfer Operation of TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by programming the Timing Register (TR). 2. If a DMA controller is to be used for the transfers, it must be set up. 3. The Control Register (CR) must be configured with information such as the slave address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and which addresses to match. The interrupt system can be set up to give interrupt request on specific events or error conditions, for example when a byte has been received. The NBYTES register is only used in SMBus mode, when PEC is enabled. In IC mode or in SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to 0. NBYTES is updated by hardware, so in order to avoid hazards, software updates of NBYTES can only be done through writes to the NBYTES register. 23.8.2.3 Address Matching TWIS can be set up to match several different addresses. More than one address match may be enabled simultaneously, allowing TWIS to be assigned to several addresses. The address matching phase is initiated after a START or REPEATED START condition. When TWIS receives an address that generates an address match, an ACK is automatically returned to the master. In IC mode: * The address in CR.ADR is checked for address match if CR.SMATCH is set. * The General Call address is checked for address match if CR.GCMATCH is set. In SMBus mode: 433 32072A-AVR32-03/09 AT32UC3A3 * The address in CR.ADR is checked for address match if CR.SMATCH is set. * The Alert Response Address is checked for address match if CR.SMAL is set. * The Default Address is checked for address match if CR.SMDA is set. * The Host Header Address is checked for address match if CR.SMHH is set. 23.8.2.4 Clock Stretching Any slave or bus master taking part in a transfer may extend the TWCK low period at any time. TWIS may extend the TWCK low period after each byte transfer if CR.STREN=1 and: * Module is in slave transmitter mode, data should be transmitted, but THR is empty, or * Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full, or * Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains stretched until all address match bits in SR have been cleared. If CR.STREN=0 and: * Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit the value present in THR (the last transmitted byte or reset value), and set SR.URUN. * Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full: Discard the received byte and set SR.ORUN. 23.8.2.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and TWIS waits for a new START condition. 23.8.3 Slave Transmitter Mode If TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will enter slave transmitter mode and set SR.TRA After the address phase, the following is done: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to transmit. This is necessary in order to know when to transmit PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Byte to transmit depends on IC/SMBus mode and CR.PEC: - If in IC mode or CR.PEC=0 or NBYTES!=0: TWIS waits until THR contains a valid data byte, possibly stretching low period of TWCK. SR.TXRDY indicates the state of THR. - SMBus mode and CR.PEC=1: If NBYTES=0, the generated PEC byte is automatically transmitted instead of a data byte from THR. TWCK will not be stretched by TWIS. 3. Transmit the correct data byte. Set SR.BTF when done. 4. Update NBYTES. If CR.CUP is set, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transferred, the master transmits an ACK or NAK bit. If a NAK bit is received, transfer is finished, and TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, more data should be transmitted, jump to step 2. 6. If STOP is received, SR.TCOMP and SR.STO will be set. 7. If REPEATED START is received, SR.REP will be set. 434 32072A-AVR32-03/09 AT32UC3A3 The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. The slave polls the data line during this clock pulse and sets the Not Acknowledge bit (NAK) in the Status Register if the master does not acknowledge the data byte. A NAK means that the master does not wish to receive additional data bytes. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of the complete transfer is marked by the SR.TCOMP bit set to one. See Figure 23-7 on page 435 and Figure 23-8 on page 435. Figure 23-7. Slave Transmitter with One Data Byte TWD S DADR W A DATA A P TCOMP TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES= 0) Figure 23-8. Master Write with Multiple Data Bytes TWD S DADR W A DATA n A DATA n+5 A DATA n+m A P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent automatically (ACK received and NBYTES= 0) 23.8.4 Slave Receiver Mode If TWIS matches an address in which the R/W bit in the TWI address phase transfer is cleared, it will enter slave receiver mode and clear SR.TRA. After the address phase, the following is repeated: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to receive. This is necessary in order to know which of the received bytes is the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Receive a byte. Set SR.BTF when done. 435 32072A-AVR32-03/09 AT32UC3A3 3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is used. 4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordinary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC is enabled and the last byte received was a PEC byte (indicated by NBYTES=0), TWIS will automatically return an ACK if the PEC value was correct, otherwise a NAK will be returned. 5. If STOP is received, SR.TCOMP will be set. 6. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 23-9. Slave Receiver with One Data Byte TWD S DADR R A DATA N P TCOMP Write START & STOP Bit, NBYTES=1 RXRDY Read RHR Figure 23-10. Slave Receiver with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TCOMP Write START + STOP Bit NBYTES=m RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Send STOP when NBYTES=0 Read RHR DATA (n+m) 23.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The programmer can set up ring buffers for the DMA controller, containing data to transmit or free buffer space to place received data. By initializing NBYTES to 0 before a transfer, and setting CR.CUP, 436 32072A-AVR32-03/09 AT32UC3A3 NBYTES is incremented by 1 each time a data has been transmitted or received. This allows the programmer to detect how much data was actually transferred by the DMA system. To assure correct behavior, respect the following programming sequences: 23.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit. 4. Wait for the Peripheral DMA Controller end TX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller TXDIS bit. 23.8.5.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit. 4. Wait for the Peripheral DMA Controller end RX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller RXDIS bit. 23.8.6 SMBus Mode SMBus mode is enabled when CR.SMEN is written to one. SMBus mode operation is similar to IC operation with the following exceptions: * Only 7-bit addressing can be used. * The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be programmed into TR. * Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). * A dedicated bus line, SMBALERT, allows a slave to get a master's attention. * A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. Address matching on these addresses can be enabled by configuring CR appropriately. 23.8.6.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CR.PECEN enables automatic PEC handling in the current transfer. The PEC generator is always updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct. In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error occurred. In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare 437 32072A-AVR32-03/09 AT32UC3A3 it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the master must take appropriate action. The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 23.8.6.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 23.8.6.3 SMBALERT A slave can get the master's attention by pulling the SMBALERT line low. This is done by setting the CR.SMBAL bit. This will also enable address match on the Alert Response Address (ARA). 23.8.7 Identifying Bus Events This chapter lists the different bus events, and how these affects bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 23-5. Event Slave transmitter has sent a data byte Bus Events Effect SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. SR.RHR is set. SR.BTF is set. SR.NAK updated according to value of ACK bit received from master. None. Slave receiver has received a data byte Start+Sadr on bus, but address is to another slave Start+Sadr on bus, current slave is addressed, but address match enable bit in CR is not set Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Repeated Start received after being addressed None. Correct address match bit in SR is set. SR.TRA updated according to transfer direction. Slave enters appropriate transfer direction mode and data transfer can commence. Correct address match bit in SR is set. SR.TRA updated according to transfer direction. Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared. Slave the enters appropriate transfer direction mode and data transfer can commence. SR.REP set. SR.TCOMP unchanged. 438 32072A-AVR32-03/09 AT32UC3A3 Table 23-5. Event Stop received after being addressed Start, Repeated Start or Stop received in illegal position on bus Data is to be received in slave receiver mode, SR.STREN is set, and RHR is full Data is to be transmitted in slave receiver mode, SR.STREN is set, and THR is empty Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty SMBus timeout received Slave transmitter in SMBus PEC mode has transmitted a PEC byte, that was not identical to the PEC calculated by the master receiver. Slave receiver discovers SMBus PEC Error Bus Events Effect SR.STO set. SR.TCOMP set. SR.BUSERR set. TWCK is stretched until RHR has been read. TWCK is stretched until THR has been written. TWCK is not stretched, read data is discarded. SR.ORUN is set. TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SR.SMBTOUT is set. TWCK and TWD are immediately released. Master receiver will transmit a NAK as usual after the last byte of a master receiver transfer. Master receiver will retry the transfer at a later time. SR.SMBPECERR is set. NAK returned after the data byte. 439 32072A-AVR32-03/09 AT32UC3A3 23.9 User Interface TWIS Register Memory Map Register Control Register NBYTES Register Timing Register Receive Holding Register Transmit Holding Register Packet Error Check Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Clear Register Parameter Register Version Register Note: Register Name CR NBYTES TR RHR THR PECR SR IER IDR IMR SCR PR VR Access Read/Write Read/Write Read/Write Read-only Write-only Read-only Read-only Write-only Write-only Read-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 (1) (1) Table 23-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2C 0x30 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 440 32072A-AVR32-03/09 AT32UC3A3 23.9.1 Name: Control Register CR Read/Write 0x00 0x00000000 30 29 28 27 26 TENBIT 25 ADR[9:8] 24 Access Type: Offset: Reset Value: 31 - 23 22 21 20 ADR[7:0] 19 18 17 16 15 - 14 SOAM 13 CUP 12 ACK 11 PECEN 10 SMHH 9 SMDA 8 SMBALERT 7 SWRST 6 - 5 - 4 STREN 3 GCMATCH 2 SMATCH 1 SMEN 0 SEN * TENBIT: Ten Bit Address Match Write this bit to zero to disable Ten Bit Address Match. Write this bit to one to enable Ten Bit Address Match. * ADR: Slave Address Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise. * SOAM: Stretch Clock on Address Match Writing this bit to zero will not strech bus clock after address match. Writing this bit to one will strech bus clock after address match. * CUP: NBYTES Count Up Writing this bit to zero causes NBYTES to count down (decrement) per byte transferred. Writing this bit to one causes NBYTES to count up (increment) per byte transferred. * ACK: Slave Receiver Data Phase ACK Value Writing this bit to zero causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode. Writing this bit to one causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode. * PECEN: Packet Error Checking Enable Writing this bit to zero disables SMBus PEC (CRC) generation and check. Writing this bit to one enables SMBus PEC (CRC) generation and check. * SMHH: SMBus Host Header Writing this bit to zero causes TWIS not to acknowledge the SMBus Host Header. Writing this bit to one causes TWIS to acknowledge the SMBus Host Header. * SMDA: SMBus Default Address Writing this bit to zero causes TWIS not to acknowledge the SMBus Default Address. Writing this bit to one causes TWIS to acknowledge the SMBus Default Address. * SMBALERT: SMBus Alert Writing this bit to zero causes TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA). Writing this bit to zero causes TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA). 441 32072A-AVR32-03/09 AT32UC3A3 * SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. Writing a one to this bit resets the TWIS. * STREN: Clock Stretch Enable Writing this bit to zero disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. Writing this bit to one enables clock stretching if RHR/THR buffer full/empty. * GCMATCH: General Call Address Match Writing this bit to zero causes TWIS not to acknowledge the General Call Address. Writing this bit to one causes TWIS to acknowledge the General Call Address. * SMATCH: Slave Address Match Writing this bit to zero causes TWIS not to acknowledge the Slave Address. Writing this bit to one causes TWIS to acknowledge the Slave Address. * SMEN: SMBus Mode Enable Writing this bit to zero disables SMBus mode. Writing this bit to one enables SMBus mode. * SEN: Slave Enable Writing this bit to zero disables the slave interface. Writing this bit to one enables the slave interface. 442 32072A-AVR32-03/09 AT32UC3A3 23.9.2 Name: NBYTES Register NBYTES Read/Write 0x04 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 - 19 18 17 16 15 14 13 12 - 11 10 9 8 7 6 5 4 NBYTES 3 2 1 0 * NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. Can also be read to to learn the progress of the transfer. Can be incremented or decremented automatically by hardware. 443 32072A-AVR32-03/09 AT32UC3A3 23.9.3 Name: Timing Register TR Read/Write 0x08 0x00000000 30 EXP 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 SUDAT 19 18 17 16 15 14 13 12 TTOUT 11 10 9 8 7 6 5 4 TLOWS 3 2 1 0 * EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula: f clkpb f prescaled = ---------------------( EXP + 1 ) 2 * SUDAT: Data Setup Cycles Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode. * TTOUT: SMBus Ttimeout Cycles Prescaled clock cycles used to time SMBus TTIMEOUT. * TLOWS: SMBus Tlow:sext Cycles Prescaled clock cycles used to time SMBus TLOW:SEXT. 444 32072A-AVR32-03/09 AT32UC3A3 23.9.4 Name: Receive Holding Register RHR Read-only 0x0C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 RXDATA 3 2 1 0 * RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is set, this field contains a byte received from the TWI bus. 445 32072A-AVR32-03/09 AT32UC3A3 23.9.5 Name: Transmit Holding Register THR Write-only 0x10 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 TXDATA 3 2 1 0 * TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here. 446 32072A-AVR32-03/09 AT32UC3A3 23.9.6 Name: Packet Error Check Register PECR Read-only 0x14 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 PEC 3 2 1 0 * PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware. 447 32072A-AVR32-03/09 AT32UC3A3 23.9.7 Name: Status Register SR Read-only 0x18 0x000000002 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 TRA 4 - 3 TCOMP 2 SEN 1 TXRDY 0 RXRDY * BTF: Byte Transfer Finished This bit is set when byte transfer has completed. This bit is cleared when the corresponding bit in SCR is written to one. * REP: Repeated Start Received This bit is set when REPEATED START condition received. This bit is cleared when the corresponding bit in SCR is written to one. * STO: Stop Received This bit is set when STOP condition received. This bit is cleared when the corresponding bit in SCR is written to one. * SMBDAM: SMBus Default Address Match This bit is set when received address matched SMBus Default Address. This bit is cleared when the corresponding bit in SCR is written to one. * SMBHHM: SMBus Host Header Address Match This bit is set when received address matched SMBus Host Header Address. This bit is cleared when the corresponding bit in SCR is written to one. * SMBALERTM: SMBus Alert Response Address Match This bit is set when received address matched SMBus Alert Response Address. This bit is cleared when the corresponding bit in SCR is written to one. * GCM: General Call Match This bit is set when received address matched General Call Address. This bit is cleared when the corresponding bit in SCR is written to one. * SAM: Slave Address Match This bit is set when received address matched Slave Address. This bit is cleared when the corresponding bit in SCR is written to one. * BUSERR: Bus Error This bit is set when a misplaced start or stop condition has occurred. This bit is cleared when the corresponding bit in SCR is written to one. 448 32072A-AVR32-03/09 AT32UC3A3 * SMBPECERR: SMBus PEC Error This bit is set when SMBus PEC error has occurred. This bit is cleared when the corresponding bit in SCR is written to one. * SMBTOUT: SMBus Timeout This bit is set when SMBus timeout has occurred. This bit is cleared when the corresponding bit in SCR is written to one. * NAK: NAK Received This bit is set when NAK was received from master during slave transmitter operation. This bit is cleared when the corresponding bit in SCR is written to one. * ORUN: Overrun This bit is set when overrun has occurred in slave receiver mode. Can only occur if CR.STREN=0. This bit is cleared when the corresponding bit in SCR is written to one. * URUN: Underrun This bit is set when underrun has occurred in slave transmitter mode. Can only occur if CR.STREN=0. This bit is cleared when the corresponding bit in SCR is written to one. * TRA: Transmitter Mode 0: The slave is in slave receiver mode. 1: The slave is in slave transmitter mode. * TCOMP: Transmission Complete This bit is set when transmission is complete. Set after receiving a STOP after being addressed. This bit is cleared when the corresponding bit in SCR is written to one. * SEN: Slave Enabled 0: The slave interface is disabled. 1: The slave interface is enabled. * TXRDY: TX Buffer Ready 0: The TX buffer is full and should not be written to. 1: The TX buffer is empty, and can accept new data. * RXRDY: RX Buffer Ready 0: No RX data ready in RHR. 1: RX data is ready to be read from RHR. 449 32072A-AVR32-03/09 AT32UC3A3 23.9.8 Name: Interrupt Enable Register IER Write-only 0x1C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 450 32072A-AVR32-03/09 AT32UC3A3 23.9.9 Name: Interrupt Disable Register IDR Write-only 0x20 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 451 32072A-AVR32-03/09 AT32UC3A3 23.9.10 Name: Interrupt Mask Register IMR Read-only 0x24 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 452 32072A-AVR32-03/09 AT32UC3A3 23.9.11 Name: Status Clear Register SCR Read/Write 0x28 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 - 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 453 32072A-AVR32-03/09 AT32UC3A3 23.9.12 Name: Parameter Register PR Read-only 0x2C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 454 32072A-AVR32-03/09 AT32UC3A3 23.9.13 Name: Version Register (VR) VR Read-only 0x30 Device-specific 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION [11:8] 7 6 5 4 VERSION [7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associated. 455 32072A-AVR32-03/09 AT32UC3A3 23.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 23-7. Module name TWIS0 TWIS1 Module Clock Name Clock name CLK_TWIS0 CLK_TWIS1 Table 23-8. Register VR PR Register Reset Values Reset Value 0x00000100 0x00000000 456 32072A-AVR32-03/09 AT32UC3A3 24. Two-Wire Master Interface (TWIM) Rev 1.0.0.0 24.1 Features * Compatible with IC standard - Multi-master support - 100 and 400 kbit/s transfer speeds - 7- and 10-bit and General Call addressing Compatible with SMBus standard - Hardware Packet Error Checking (CRC) generation and verification with ACK control - SMBus ALERT interface - 25 ms clock low timeout delay - 10 ms master cumulative clock low extend time - 25 ms slave cumulative clock low extend time Compatible with PMBus Compatible with Atmel Two-Wire Interface Serial Memories DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer * * * * * * 24.2 Overview The Atmel Two-wire Interface Master (TWIM) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial EEPROM and IC compatible device such as a real rime clock (RTC), dot matrix/graphic LCD controller and temperature sensor, to name a few. TWIM is always a bus master and can transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus is performed internally and relinquishes the bus automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.Table 24-1 on page 457 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full IC compatible device. Table 24-1. IC Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7- or 10-bits Slave Addressing START BYTE (1) Atmel TWIM Compatibility with IC Standard Atmel TWIM Supported Supported Supported Not Supported Supported Supported Supported Supported Repeated Start (Sr) Condition ACK and NACK Management Slope Control and Input Filtering (Fast mode) Clock Stretching Note: 1. START + b000000001 + Ack + Sr 457 32072A-AVR32-03/09 AT32UC3A3 Table 24-2 on page 458 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 24-2. Bus Timeouts Address Resolution Protocol Alert Host Functionality Packet Error Checking Atmel TWIM Compatibility with SMBus Standard Atmel TWIM Supported Supported Supported Supported Supported SMBus Standard 24.3 List of Abbreviations Table 24-3. Abbreviation TWI A NA P S Sr SADR ADR R W Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address Any address except SADR Read Write 458 32072A-AVR32-03/09 AT32UC3A3 24.4 Block Diagram Figure 24-1. Block Diagram Peripheral Bus Bridge TWCK I/O controller Two-wire Interface CLK_TWIM TWI Interrupt TWD TWALM Power Manager INTC 24.5 Application Block Diagram Figure 24-2. Application Block Diagram VDD Rp TWD TWI Master TWCK Rp Atmel TWI serial EEPROM Slave 1 IC RTC Slave 2 IC LCD controller Slave 3 IC temp. sensor Slave 4 Rp: Pull up value as given by the IC Standard 24.6 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock SMBus SMBALERT Type Input/Output Input/Output Input/Output Table 24-4. Pin Name TWD TWCK TWALM 459 32072A-AVR32-03/09 AT32UC3A3 24.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 24.7.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 24-2 on page 459). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. TWD, TWCK and TWALM pins may be multiplexed with I/O Controller lines. To enable the TWIM, the programmer must perform the following steps: * Program the I/O Controller to: - Dedicate TWD, TWCK and optionally TWALM as peripheral lines. - Define TWD, TWCK and optionally TWALM as open-drain. 24.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIM, the TWIM will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 24.7.4 Interrupts The TWIM interrupt request lines are connected to the interrupt controller. Using the TWIM interrupts requires the interrupt controller to be programmed first. 24.7.5 Debug Operation When an external debugger forces the CPU into debug mode, the TWIM continues normal operation. If the TWIM is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 24.7.3 460 32072A-AVR32-03/09 AT32UC3A3 24.8 24.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 24-4 on page 461). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 24-4 on page 461). * A high-to-low transition on the TWD line while TWCK is high defines the START condition. * A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 24-3. START and STOP Conditions TWD TWCK Start Stop Figure 24-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 24.8.2 Operation The TWIM has two modes of operation: * Master transmitter mode * Master receiver mode The master is the device which starts and stops a transfer and generates the TWCK clock. These modes are described in the following chapters. 461 32072A-AVR32-03/09 AT32UC3A3 24.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be programmed so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the EXP field in CWGR. f clkpb f prescaled = ------------------------( EXP + 1 ) ) 2 CWGR has the following fields: LOW: Prescaled clock cycles in clock low count. Used to time TLOW. and TBUF. HIGH: Prescaled clock cycles in clock high count. Used to time THIGH. STASTO: Prescaled clock cycles in clock high count. Used to time THD_STA, TSU_STA, TSU_STO. DATA: Prescaled clock cycles for data setup and hold count. Used to time THD_DAT, TSU_DAT. EXP: Specifies the clock prescaler setting. Note that the total clock low time generated is the sum of THD_DAT + TSU_DAT + TLOW. Any slave or other bus master taking part in the transfer may extend the TWCK low period at any time. Figure 24-5. Bus Timing Diagram t LOW t HIGH t LOW S t t HD:STA SU:DAT t HD:DAT t t SU:DAT SU:STO P t SU:STA Sr 24.8.2.2 Setting up and Performing a Transfer Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by programming the Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the SMBus Timing Register (SMBTR) register must also be configured. 2. If a DMA controller is to be used for the transfers, it must be set up. 3. CMDR or NCMDR must be programmed with a value describing the transfer to be performed. 462 32072A-AVR32-03/09 AT32UC3A3 The interrupt system can be set up to give interrupt request on specific events or error conditions, for example when the transfer is complete or if arbitration is lost. The controller will refuse to start a new transfer while ANAK, DNAK or ARBLST is set in the Status Register (SR). This is necessary to avoid a race when the software issues a continuation of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK occur, a STOP condition is sent automatically. The programmer will have to restart the transmission by clearing the errors bit in SR after resolving the cause for the NACK. After a data or address NACK from the slave, a STOP will be transmitted automatically. Note that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR. 24.8.3 Master Transmitter Mode A START condition is transmitted and master transmitter mode is initiated when the bus is free and CMDR has been written with START=1 and READ=0. START and SADR+W will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY indicates the state of THR. Software or a DMA controller must write the data byte to THR. 2. Transmit this data byte 3. Decrement NBYTES 4. If (NBYTES==0) and STOP=1, transmit STOP condition Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, SADR+W, STOP. TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (TWIM_IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of a command is marked by setting the SR.CCOMP bit to one. See Figure 24-6 on page 464 and Figure 24-7 on page 464. 463 32072A-AVR32-03/09 AT32UC3A3 Figure 24-6. Master Write with One Data Byte TWD S DADR W A DATA A P TCOMP TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES= 0) Figure 24-7. Master Write with Multiple Data Bytes TWD S DADR W A DATA n A DATA n+5 A DATA n+m A P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent automatically (ACK received and NBYTES= 0) 24.8.4 Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with START=1 and READ=1. START and SADR+R will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or a DMA controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition. Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, DADR+R, STOP The TWI transfers require the master to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. All data bytes except the last are 464 32072A-AVR32-03/09 AT32UC3A3 acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer is finished. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 24-8. Master Read with One Data Byte TWD S DADR R A DATA N P TCOMP Write START & STOP Bit, NBYTES=1 RXRDY Read RHR Figure 24-9. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TCOMP Write START + STOP Bit NBYTES=m RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Send STOP when NBYTES=0 Read RHR DATA (n+m) 24.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The programmer can set up ring buffers for the DMA controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 24.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit. 4. Wait for the Peripheral DMA Controller end TX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller TXDIS bit. 465 32072A-AVR32-03/09 AT32UC3A3 24.8.5.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit. 4. Wait for the Peripheral DMA Controller end RX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller RXDIS bit. 24.8.6 Multi-master Mode More than one master may access the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who lost arbitration may reinitiate the data transfer. Arbitration is illustrated in Figure 24-11 on page 467. If the user starts a transfer and if the bus is busy, TWIM automatically waits for a STOP condition on the bus before initiating the transfer (see Figure 24-10 on page 466). Note: The state of the bus (busy or free) is not indicated in the user interface. Figure 24-10. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated 466 32072A-AVR32-03/09 AT32UC3A3 Figure 24-11. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated 24.8.7 Combined Transfers CMDR and NCMDR may be used to generate longer sequences of connected transfers, since generation of START and/or STOP conditions is programmable on a per-command basis. Programming NCMDR with START=1 when the previous transfer was programmed with STOP=0 will cause a REPEATED START on the bus. The ability to generate such connected transfers allows arbitrary transfer lengths, since it is legal to program CMDR with both START=0 and STOP=0. If this is done in master receiver mode, the CMDR.ACKLAST bit must also be controlled. As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to the THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see "Using the Peripheral DMA Controller" on page 465 24.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 467 32072A-AVR32-03/09 AT32UC3A3 5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR. 24.8.7.2 Read Followed by Read Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.RXRDY==1, then read third data byte received from RHR. 6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR. If combining several transfers, without any STOP or REPEATED START between them, remember to set the ACKLAST bit in CMDR to keep from ending each of the partial transfers with a NACK. 24.8.7.3 Write Followed by Read Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. Figure 24-12. Combining a Write and Read Transfer TWI_THR DATA0 DATA1 TWD S ADR W A DATA0 A DATA1 NA Sr ADR R A DATA2 A DATA3 A DATA3 P TWI_RHR TXRDY RXRDY DATA2 TCOMP To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5. Wait until SR.RXRDY==1, then read first data byte received from RHR. 6. Wait until SR.RXRDY==1, then read second data byte received from RHR. 24.8.7.4 Read Followed by Write Consider the following transfer: 468 32072A-AVR32-03/09 AT32UC3A3 START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP. Figure 24-13. Combining a Read and Write Transfer TWI_THR DATA2 DATA3 TWD TWI_RHR S SADR R A DATA0 A DATA1 A Sr SADR W A DATA2 A DATA3 NA P DATA0 DATA1 TXRDY RXRDY Read TWI_RHR TCOMP To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 24.8.8 Ten Bit Addressing Setting CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 10:7 of CMDR.ADR must be set appropriately. In Figure 24-14 on page 469 and Figure 24-15 on page 470, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 24.8.8.1 Master Transmitter To perform a master transmitter transfer, 1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the desired address and NBYTES value. Figure 24-14. A Write Transfer with 10-bit Addressing 1 S 1 1 1 0 X X 0 RW A1 SLAVE ADDRESS 2nd byte A2 DATA A DATA AA P SLAVE ADDRESS 1st 7 bits 24.8.8.2 Master Receiver When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be controlled. CMDR.REPSAME must be written to one when the address phase of the transfer should 469 32072A-AVR32-03/09 AT32UC3A3 consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The IC standard specifies that such addressing is required when addressing a slave for reads using 10-bit addressing. To perform a master receiver transfer, 1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0, NBYTES=0 and the desired address. 2. Program NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the desired address and NBYTES value. Figure 24-15. A Read Transfer with 10-bit Addressing 1 S 1 1 1 0 X X 0 RW A1 SLAVE ADDRESS 2nd byte A2 Sr 1 1 1 1 0 X X 1 RW A3 DATA A DATA A P SLAVE ADDRESS 1st 7 bits SLAVE ADDRESS 1st 7 bits 24.8.9 SMBus Mode SMBus mode is enabled and disabled by the SMEN and SMDIS bits in CR. SMBus mode operation is similar to IC operation with the following exceptions: * Only 7-bit addressing can be used. * The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be programmed into SMBTR. * Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). * A dedicated bus line SMBALERT, allows a slave to get a master's attention. * A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. 24.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing CMDR.PECEN to one enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct. In master transmitter mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NACK value. The DNAK bit in SR reflects the state of the last received ACK/NACK value. Some slaves may not be able to check the received PEC in time to return a NACK if an error occurred. In this case, the slave should always return an ACK after the PEC byte, and some other mechanism must be implemented to verify that the transmission was received correctly. In master receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the PECERR bit in SR is set. In master receiver mode, the PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the transfer. 470 32072A-AVR32-03/09 AT32UC3A3 The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if PEC is enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. In combined transfers, the PECEN bit should only be set in the last of the combined transfers. Consider the following transfer: S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P This transfer is generated by writing two commands to the command registers. The first command is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and PECEN=1. Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current byte. No PEC byte will be sent in this case. 24.8.9.2 Timeouts The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is also set. 24.8.9.3 SMBus ALERT Signal A slave can get the master's attention by pulling the TWALM line low. SR.SMBAL will then be set. This can be set up to trigger an interrupt, and software can then take the appropriate action, as defined in the SMBus standard. Identifying Bus Events This chapter lists the different bus events, and how these affects bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 24-5. Event Master transmitter has sent a data byte Master receiver has received a data byte 24.8.10 Bus Events Effect SR.THR is cleared. SR.RHR is set. SR.ANAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.DNAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.ARBLST is set. CMDR.CCOMP not set. CMDR.VALID remains set. TWCK and TWD immediately released to a pulled-up state. SR.SMBAL is set. Start+Sadr sent, no ack received from slave Data byte sent to slave, no ack received from slave Arbitration lost SMBus Alert received 471 32072A-AVR32-03/09 AT32UC3A3 Table 24-5. Event Bus Events Effect SR.SMBTOUT is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.DNAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.PECERR is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.STOP is set. CMDR.CCOMP set. CMDR.VALID remains set. STOP transmitted on bus after current byte transfer has finished. SMBus timeout received Master transmitter receives SMBus PEC Error Master receiver discovers SMBus PEC Error CR.STOP is written by user 472 32072A-AVR32-03/09 AT32UC3A3 24.9 User Interface TWIM Register Memory Map Register Control Clock Waveform Generator SMBus Timing Command Next Command Receive Holding Transmit Holding Status Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Clear Register Parameter Register Version Register Register Name CR CWGR SMBTR CMDR NCMDR RHR THR SR IER IDR IMR SCR PR VR Access Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 (1) (1) Table 24-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 473 32072A-AVR32-03/09 AT32UC3A3 24.9.1 Name: Control Register (CR) CR Write-only 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 STOP 7 SWRST 6 - 5 SMDIS 4 SMEN 3 - 2 - 1 MDIS 0 MEN * STOP: Stop the current transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully sent. Writing a zero to this bit has no effect. * SWRST: Software Reset Writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly violating the bus semantics. Writing a zero to this bit has no effect. * SMDIS: SMBus Disable Writing a one to this bit disables SMBus mode. Writing a zero to this bit has no effect. * SMEN: SMBus Enable Writing a one to this bit enables SMBus mode. Writing a zero to this bit has no effect. * MDIS: Master Disable Writing a one to this bit disables the master interface. Writing a zero to this bit has no effect. * MEN: Master enable Writing a one to this bit enables the master interface. Writing a zero to this bit has no effect. 474 32072A-AVR32-03/09 AT32UC3A3 24.9.2 Name: Clock Waveform Generator Register (CWGR) CWGR Read/Write 0x04 0x00000000 30 29 EXP 28 27 26 DATA 25 24 Access Type: Offset: Reset Value: 31 - 23 22 21 20 STASTO 19 18 17 16 15 14 13 12 HIGH 11 10 9 8 7 6 5 4 LOW 3 2 1 0 * EXP: Clock Prescaler Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula f clkpb f prescaled = ---------------------( EXP + 1 ) 2 * DATA: Data Setup and Hold Cycles Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT. * STASTO: START and STOP Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO * HIGH: Clock High Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH. * LOW: Clock Low Cycles Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF. 475 32072A-AVR32-03/09 AT32UC3A3 24.9.3 Name: SMBus Timing Register (SMBTR) SMBTR Read/Write 0x08 0x00000000 30 EXP 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 23 22 21 20 THMAX 19 18 17 16 15 14 13 12 TLOWM 11 10 9 8 7 6 5 4 TLOWS 3 2 1 0 * EXP: SMBus Timeout Clock prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following formula f clkpb f prescaled, SMBus = ---------------------( EXP + 1 ) 2 * THMAX: Clock High maximum cycles Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX. NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR. * TLOWM: Master Clock stretch maximum cycles Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT * TLOWS: Slave Clock stretch maximum cycles Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT. 476 32072A-AVR32-03/09 AT32UC3A3 24.9.4 Name: Command Register (CMDR) CMDR Read/Write 0x0C 0x00000000 30 29 28 27 26 25 ACKLAST 24 PECEN Access Type: Offset: Reset Value: 31 - 23 22 21 20 NBYTES 19 18 17 16 15 VALID 14 STOP 13 START 12 REPSAME 11 TENBIT 10 9 SADR[9:7] 8 7 6 5 4 SADR[6:0] 3 2 1 0 READ * ACKLAST: ACK Last Master RX Byte Writing this bit to zero causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of ending a master receiver transfer. Writing this bit to one causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more than 255 bytes are to be received in one single transmission. * PECEN: Packet Error Checking Enable Writing this bit to zero causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received. Must be used if SMBus mode is disabled. Writing this bit to one causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will be performed. * NBYTES: Number of data bytes in transfer The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is transmitted if CMDR.STOP is set. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, ie there are NBYTES-1 data bytes and a PEC byte. * VALID: CMDR Valid Writing this to zero indicates that CMDR does not contain a valid command. Writing this to one indicates that CMDR contains a valid command. This bit is cleared when the command is finished. * STOP: Send STOP condition Write this bit to zero to not transmit a STOP condition after the data bytes have been transmitted. Write this bit to one to transmit a STOP condition after the data bytes have been transmitted. * START: Send START condition Write this bit to zero if the transfer in CMDR should not commence with a START or REPEATED START condition. Write this bit to one if the transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command is executed, a START condition is used, if the bus is busy, a REPEATED START is used. * REPSAME: Transfer is to same address as previous address Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode. 477 32072A-AVR32-03/09 AT32UC3A3 Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. * TENBIT: Ten Bit Addressing Mode Write this bit to zero to use 7-bit addressing mode. Write this bit to one to use 10-bit addressing mode. Must not be used when TWIM is in SMBus mode. * SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don't care if 7-bit addressing is used. * READ: Transfer Direction Write this bit to zero to let the master transmit data. Write this bit to one to let the master receive data. 478 32072A-AVR32-03/09 AT32UC3A3 24.9.5 Name: Next Command Register (NCMDR) NCMDR Read/Write 0x10 0x00000000 30 29 28 27 26 25 ACKLAST 24 PECEN Access Type: Offset: Reset Value: 31 - 23 22 21 20 NBYTES 19 18 17 16 15 VALID 14 STOP 13 START 12 REPSAME 11 TENBIT 10 9 SADR[9:7] 8 7 6 5 4 SADR[6:0] 3 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the contents of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the contents are copied immediately. 479 32072A-AVR32-03/09 AT32UC3A3 24.9.6 Name: Receive Holding Register (RHR) RHR Read-only 0x14 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 RXDATA 3 2 1 0 * RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is set, this field contains a byte received from the TWI bus. 480 32072A-AVR32-03/09 AT32UC3A3 24.9.7 Name: Transmit Holding Register (THR) THR Write-only 0x18 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 TXDATA 3 2 1 0 * TXDATA: Data to Transmit Write data to be transferred on the TWI bus here. 481 32072A-AVR32-03/09 AT32UC3A3 24.9.8 Name: Status Register (SR) SR Read-only 0x1C 0x00000002 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 MENB 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY * MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled. * STOP: Stop Request Accepted This bit is set when STOP request caused by setting CR STOP has been accepted, and transfer has stopped. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * PECERR: PEC Error This bit is set when a SMBus PEC error occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * TOUT: Timeout This bit is set when a SMBus timeout occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * SMBALERT: SMBus Alert This bit is set when a SMBus Alert was received. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * ARBLST: Arbitration Lost This bit is set when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority transmission in progress by a different master. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * DNAK: NAK in Data Phase Received This bit is set when no ACK was received form slave during data transmission. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * ANAK: NAK in Address Phase Received This bit is set when no ACK was received from slave during address phase This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * IDLE: Master Interface is Idle This bit is set when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. 482 32072A-AVR32-03/09 AT32UC3A3 * CCOMP: Command Complete This bit is set when the current command has completed successfully and STOP has been transmitted. Not set if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). * CRDY: Ready for More Commands This bit is set when CMDR and/or NCMDR is ready to receive one or more commands. This bit is cleared when this is no longer true. * TXRDY: THR Data Ready This bit is set when THR is ready for one or more data bytes. This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped). * RXRDY: RHR Data Ready This bit is set when RX data are ready to be read from RHR. This bit is cleared when this is no longer true. 483 32072A-AVR32-03/09 AT32UC3A3 24.9.9 Name: Interrupt Enable Register (IER) IER Write-only 0x20 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 484 32072A-AVR32-03/09 AT32UC3A3 24.9.10 Name: Interrupt Disable Register (IDR) IDR Write-only 0x24 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 485 32072A-AVR32-03/09 AT32UC3A3 24.9.11 Name: Interrupt Mask Register (IMR) IMR Read-only 0x28 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 486 32072A-AVR32-03/09 AT32UC3A3 24.9.12 Name: Status Clear Register (SCR) SCR Write-only 0x2C 0x00000000 30 29 28 27 26 25 24 - Access Type : Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 - 3 CCOMP 2 - 1 - 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 487 32072A-AVR32-03/09 AT32UC3A3 24.9.13 Name: Parameter Register (PR) PR Read-only 0x30 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 488 32072A-AVR32-03/09 AT32UC3A3 24.9.14 Name: Version Register (VR) VR Read-only 0x34 Device-specific 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION [11:8] 7 6 5 4 VERSION [7:0] 3 2 1 0 * VARIANT: Variant number Reserved. No functionality associated. * VERSION: Version number Version number of the module. No functionality associated. 489 32072A-AVR32-03/09 AT32UC3A3 24.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 24-7. Module name TWIM0 TWIM1 Module Clock Name Clock name CLK_TWIM0 CLK_TWIM1 Table 24-8. Register VR PR Register Reset Values Reset Value 0x00000100 0x00000000 490 32072A-AVR32-03/09 AT32UC3A3 25. Synchronous Serial Controller (SSC) Rev: 3.2.0.2 25.1 Features * * * * * Provides serial synchronous communication links used in audio and telecom applications Independent receiver and transmitter, common clock divider Interfaced with two Peripheral DMA Controller channels to reduce processor overhead Configurable frame sync and data length Receiver and transmitter can be configured to start automatically or on detection of different events on the frame sync signal * Receiver and transmitter include a data signal, a clock signa,l and a frame synchronization signal 25.2 Overview The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver and the transmitter interface with three signals: * the TX_DATA/RX_DATA signal for data * the TX_CLOCK/RX_CLOCK signal for the clock * the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC's high-level of programmability and its two dedicated Peripheral DMA Controller channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing with low processor overhead to the following: * CODEC's in master or slave mode * DAC through dedicated serial interface, particularly I2S * Magnetic card reader 491 32072A-AVR32-03/09 AT32UC3A3 25.3 Block Diagram Figure 25-1. SSC Block Diagram High Speed Bus Peripheral Bus Bridge Peripheral DMA Controller Peripheral Bus TX_FRAME_SYNC TX_CLOCK Power CLK_SSC Manager TX_DATA SSC Interface I/O Controller RX_FRAME_SYNC RX_CLOCK Interrupt Control RX_DATA SSC Interrupt 25.4 Application Block Diagram Figure 25-2. SSC Application Block Diagram Power Management SSC Serial AUDIO Codec Time Slot Frame Management Management Line Interface Interrupt Management Test Management OS or RTOS Driver 492 32072A-AVR32-03/09 AT32UC3A3 25.5 I/O Lines Description Table 25-1. Pin Name RX_FRAME_SYNC RX_CLOCK RX_DATA TX_FRAME_SYNC TX_CLOCK TX_DATA I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output 25.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 25.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 25.6.2 Clocks The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SSC before disabling the clock, to avoid freezing the SSC in an undefined state. 25.6.3 Interrupts The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt requires the interrupt controller to be programmed first. 25.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data Framing Format, Start, Transmitter, Receiver, and Frame Sync. The receiver and the transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two. 493 32072A-AVR32-03/09 AT32UC3A3 Figure 25-3. SSC Functional Block Diagram Transmitter Clock Output Controller TX_CLOCK TX_CLOCK Input CLK_SSC Clock Divider RX clock TX_FRAME_SYNC RX_FRAME_SYNC Transmit Clock TX clock Controller Frame Sync Controller TX_FRAME_SYNC Start Selector TX_DMA Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TX_DATA Peripheral Bus User Interface Load Shift Receiver Clock Output Controller RX_CLOCK RX_CLOCK Input TX clock TX_FRAME_SYNC RX_FRAME_SYNC Receive Clock RX clock Controller Frame Sync Controller RX_FRAME_SYNC Start Selector RX_DMA Receive Shift Register Receive Holding Register Receive Sync Holding Register RX_DATA DMA Interrupt Control Load Shift Interrupt Controller 25.7.1 Clock Management The transmitter clock can be generated by: * an external clock received on the TX_CLOCK pin * the receiver clock * the internal clock divider The receiver clock can be generated by: * an external clock received on the RX_CLOCK pin * the transmitter clock * the internal clock divider Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and the receiver block can generate an external clock on the RX_CLOCK pin. This allows the SSC to support many Master and Slave Mode data transfers. 494 32072A-AVR32-03/09 AT32UC3A3 25.7.1.1 Clock divider Figure 25-4. Divided Clock Block Diagram Clock Divider CMR CLK_SSC Divided Clock /2 12-bit Counter The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is 4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190. The divided clock is provided to both the receiver and transmitter. When this field is written to zero, the clock divider is not used and remains inactive. When CMR.DIV is written to a value equal to or greater than one, the divided clock has a frequency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the divided clock regardless of whether the CMR.DIV value is even or odd. Figure 25-5. Divided Clock Generation CLK_SSC Divided Clock DIV = 1 Divided Clock Frequency = CLK_SSC/2 CLK_SSC Divided Clock DIV = 3 Divided Clock Frequency = CLK_SSC/6 Table 25-2. Maximum CLK_SSC / 2 Range of Clock Divider Minimum CLK_SSC / 8190 25.7.1.2 Transmitter clock management The transmitter clock is generated from the receiver clock, the divider clock, or an external clock scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The Transmit clock can 495 32072A-AVR32-03/09 AT32UC3A3 be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR (TCMR.CKI). The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register (TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs. Writing 0b10 to the TCMR.CKS field to select TX_CLOCK pin and 0b001 to the TCMR.CKO field to select Continuous Transmit Clock can lead to unpredictable results. Figure 25-6. Transmitter Clock Management TX_CLOCK Clock Output MUX Receiver Clock Tri-state Controller Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 25.7.1.3 Receiver clock management The receiver clock is generated from the transmitter clock, the divider clock, or an external clock scanned on the RX_CLOCK pin. The receive clock is selected by writing to the Receive Clock Selection field in the Receive Clock Mode Register (RCMR.CKS). The receive clock can be inverted independently by writing a one to the Receive Clock Inversion bit in RCMR (RCMR.CKI). The receiver can also drive the RX_CLOCK pin continuously or be limited to the actual data transfer, depending on the Receive Clock Output Mode Selection field in the RCMR register (RCMR.CKO). The RCMR.CKI bit has no effect on the clock outputs. Writing 0b10 to the RCMR.CKS field to select RX_CLOCK pin and 0b001 to the RCMR.CKO field to select Continuous Receive Clock can lead to unpredictable results. 496 32072A-AVR32-03/09 AT32UC3A3 Figure 25-7. Receiver Clock Management RX_CLOCK MUX Transmitter Clock Tri-state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 25.7.1.4 Serial clock ratio considerations The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is: - CLK_SSC divided by two if RX_FRAME_SYNC is input. - CLK_SSC divided by three if RX_FRAME_SYNC is output. In addition, the maximum clock speed allowed on the TX_CLOCK pin is: - CLK_SSC divided by six if TX_FRAME_SYNC is input. - CLK_SSC divided by two if TX_FRAME_SYNC is output. 25.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by writing to the TCMR register. See Section 25.7.4. The frame synchronization is configured by writing to the Transmit Frame Mode Register (TFMR). See Section 25.7.5. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the TCMR register. Data is written by the user to the Transmit Holding Register (THR) then transferred to the shift register according to the data format selected. When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift register, the Transmit Ready bit is set in the SR register (SR.TXREADY) and additional data can be loaded in the THR register. 497 32072A-AVR32-03/09 AT32UC3A3 Figure 25-8. Transmitter Block Diagram CR.TXEN SR.TXEN CR.TXDIS TFMR.DATDEF TCMR.STTDLY TFMR.FSDEN TFMR.DATNB 1 0 TX_DATA TX_FRAME_SYNC RX_FRAME_SYNC Transmitter Clock Start Selector TFMR.MSBF Transmit Shift Register TFMR.FSDEN TCMR.STTDLY TFMR.DATLEN THR 0 1 TSHR TFMR.FSLEN 25.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by writing to the RCMR register. See Section 25.7.4. The frame synchronization is configured by writing to the Receive Frame Mode Register (RFMR). See Section 25.7.5. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the RCMR register. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the Receive Holding Register (RHR), the Receive Ready bit is set in the SR register (SR.RXREADY) and the data can be read in the RHR register. If another transfer occurs before a read of the RHR register, the Receive Overrun bit is set in the SR register (SR.OVRUN) and the receiver shift register is transferred to the RHR register. 498 32072A-AVR32-03/09 AT32UC3A3 Figure 25-9. Receiver Block Diagram RX_C LO CK MUX T ra n sm itte r C lo ck T ri-sta te C o n tro lle r C lo ck O u tp u t D ivid e r C lo ck CKO D a ta T ra n sfe r CKS IN V MUX T ri-sta te C o n tro lle r R e ce ive r C lo ck CKI CKG 25.7.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection field of the TCMR register (TCMR.START) and in the Receive Start Selection field of the RCMR register (RCMR.START). Under the following conditions the start event is independently programmable: * Continuous: in this case, the transmission starts as soon as a word is written to the THR register and the reception starts as soon as the receiver is enabled * Synchronously with the transmitter/receiver * On detection of a falling/rising edge on TX_FRAME_SYNC/RX_FRAME_SYNC * On detection of a low/high level on TX_FRAME_SYNC/RX_FRAME_SYNC * On detection of a level change or an edge on TX_FRAME_SYNC/RX_FRAME_SYNC A start can be programmed in the same manner on either side of the Transmit/Receive Clock Mode Register (TCMR/RCMR). Thus, the start could be on TX_FRAME_SYNC (transmit) or RX_FRAME_SYNC (receive). Moreover, the receiver can start when data is detected in the bit stream with the compare functions. See Section 25.7.6 for more details on receive compare modes. Detection on TX_FRAME_SYNC input/output is done by the Transmit Frame Sync Output Selection field in the TFMR register (TFMR.FSOS). Similarly, detection on RX_FRAME_SYNC input/output is done by the Receive Frame Output Sync Selection field in the RFMR register (RFMR.FSOS). 499 32072A-AVR32-03/09 AT32UC3A3 Figure 25-10. Transmit Start Mode TX_CLOCK (Input) TX_FRAME_SYNC (Input) TX_DATA (Output) Start= Low Level on TX_FRAME_SYNC TX_DATA (Output) Start= Falling Edge on TX_FRAME_SYNC TX_DATA (Output) Start= High Level on TX_FRAME_SYNC TX_DATA (Output) Start= Rising Edge on TX_FRAME_SYNC TX_DATA (Output) Start= Level Change on TX_FRAME_SYNC TX_DATA (Output) Start= Any Edge on TX_FRAME_SYNC X B0 B1 STTDLY X B0 B1 STTDLY X B0 B1 STTDLY X B0 B1 STTDLY X B0 B1 B0 B1 STTDLY X B0 B1 B0 B1 STTDLY Figure 25-11. Receive Pulse/Edge Start Modes RX_CLOCK RX_FRAME_SYNC (Input) RX_DATA (Input) Start = Low Level on RX_FRAME_SYNC RX_DATA (Input) Start = Falling Edge on RX_FRAME_SYNC RX_DATA (Input) Start = High Level on RX_FRAME_SYNC RX_DATA (Input) Start = Rising Edge on RX_FRAME_SYNC RX_DATA (Input) Start = Level Change on RX_FRAME_SYNC RX_DATA (Input) Start = Any Edge on RX_FRAME_SYNC X B0 B1 B0 B1 STTDLY X X X STTDLY X B0 B1 STTDLY B0 B1 STTDLY B0 B1 STTDLY X B0 B1 B0 B1 STTDLY 500 32072A-AVR32-03/09 AT32UC3A3 25.7.5 Frame Sync The transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC, can be programmed to generate different kinds of frame synchronization signals. The RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform. * Programmable low or high levels during data transfer are supported. * Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, in reception, the Receive Frame Sync Length High Part and the Receive Frame Sync Length fields in the RFMR register (RFMR.FSLENHI and RFMR.FSLEN) define the length of the pulse, from 1 bit time up to 256 bit time. Reception Pulse Length = ((16 x FSLENHI ) + FSLEN + 1) receive clock periods Similarly, in transmission, the Transmit Frame Sync Length High Part and the Transmit Frame Sync Length fields in the TFMR register (TFMR.FSLENHI and TFMR.FSLEN) define the length of the pulse, from 1 bit up to 256 bit time. Transmission Pulse Length = ((16 x FSLENHI ) + FSLEN + 1) transmit clock periods The periodicity of the RX_FRAME_SYNC and TX_FRAME_SYNC pulse outputs can be configured respectively through the Receive Period Divider Selection field in the RCMR register (RCMR.PERIOD) and the Transmit Period Divider Selection field in the TCMR register (TCMR.PERIOD). 25.7.5.1 Frame sync data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the receiver can sample the RX_DATA line and store the data in the Receive Sync Holding Register (RSHR) and the transmitter can transfer the Transmit Sync Holding Register (TSHR) in the shifter register. The data length to be sampled in reception during the Frame Sync signal shall be written to the RFMR.FSLENHI and RFMR.FSLEN fields. The data length to be shifted out in transmission during the Frame Sync signal shall be written to the TFMR.FSLENHI and TFMR.FSLEN fields. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the RSHR through the receive shift register. The Transmit Frame Sync operation is performed by the transmitter only if the Frame Sync Data Enable bit in TFMR register (TFMR.FSDEN) is written to one. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the TSHR is transferred in the transmit register, then shifted out. 25.7.5.2 Frame sync edge detection The Frame Sync Edge detection is configured by writing to the Frame Sync Edge Detection bit in the RFMR/TFMR registers (RFMR.FSEDGE and TFMR.FSEDGE). This sets the Receive Sync 501 32072A-AVR32-03/09 AT32UC3A3 and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC). 25.7.6 Receive Compare Modes Figure 25-12. Receive Compare Modes RX_CLOCK RX_DATA (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 {FSLENHI,FSLEN} Up to 256 Bits (4 in This Example) STTDLY DATLEN 25.7.6.1 Compare functions Compare 0 can be one start event of the receiver. In this case, the receiver compares at each new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI, RFMR.FSLEN} lower bits of the data contained in the Compare 0 Register (RC0R). When this start event is selected, the user can program the receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP). Data Framing Format The data framing format of both the transmitter and the receiver are programmable through the TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select: * the event that starts the data transfer (RCMR.START and TCMR.START) * the delay in number of bit periods between the start event and the first data bit (RCMR.STTDLY and TCMR.STTDLY) * the length of the data (RFMR.DATLEN and TFMR.DATLEN) * the number of data to be transferred for each start event (RFMR.DATNB and TFMR.DATLEN) * the length of synchronization transferred for each start event (RFMR.FSLENHI, RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN) * the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to the Frame Sync Data Enable and the Data Default Value bits in the TFMR register (TFMR.FSDEN and TFMR.DATDEF). Table 25-3. Transmitter TCMR TCMR TCMR 25.7.7 Data Framing Format Registers Receiver RCMR RCMR RCMR Bit/Field PERIOD START STTDLY Up to 255 Length Up to 512 Frame size Start selection Size of transmit start delay Comment 502 32072A-AVR32-03/09 AT32UC3A3 Table 25-3. Transmitter TFMR TFMR TFMR TFMR TFMR TFMR Data Framing Format Registers Receiver RFMR RFMR RFMR RFMR Bit/Field DATNB DATLEN {FSLENHI,FSLEN} MSBF FSDEN DATDEF Length Up to 16 Up to 32 Up to 256 Comment Number of words transmitted in frame Size of word Size of Synchro data register Most significant bit first Enable send TSHR Data default value ended Figure 25-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TX_FRAME_SYNC / (1) RX_FRAME_SYNC FSLEN TX_DATA (If FSDEN = 1) TX_DATA (If FSDEN = 0) Sync Data From TSHR Default From DATDEF Data From THR Data From THR Data To RHR DATLEN Data From THR Data From THR Data To RHR DATLEN Default From DATDEF Default From DATDEF Ignored Sync Data Sync Data Start Default From DATDEF RX_DATA Sync Data To RSHR Ignored STTDLY DATNB Note: Example of input on falling edge of TX_FRAME_SYNC/RX_FRAME_SYNC. Figure 25-14. Transmit Frame Format in Continuous Mode Start TX_DATA Data From THR DATLEN Data From THR DATLEN Default Start: 1. TXEMPTY set to one 2. Write into the THR Note: STTDLY is written to zero. In this example, THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. 503 32072A-AVR32-03/09 AT32UC3A3 Figure 25-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RX_DATA Data To RHR DATLEN Data To RHR DATLEN Note: STTDLY is written to zero. 25.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and RX_CLOCK is connected to TX_CLOCK. 25.7.9 Interrupt Most bits in the SR register have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR). These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt controller. Figure 25-16. Interrupt Block Diagram IM R IE R Set ID R C le a r T ra n s m itte r TXRDY TXEM PTY TXSYNC In te rru p t C o n tro l S S C In te rru p t R e c e iv e r RXRDY OVRUN RXSYNC 504 32072A-AVR32-03/09 AT32UC3A3 25.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 25-17. Audio Application Block Diagram Clock SCK TX_CLOCK Word Select WS TX_FRAME_SYNC Data SD TX_DATA SSC RX_DATA RX_FRAME_SYNC RX_CLOCK Clock SCK Word Select WS I2S RECEIVER Data SD MSB Left Channel LSB MSB Right Channel Figure 25-18. Codec Application Block Diagram Serial Data Clock (SCLK) TX_CLOCK Frame sync (FSYNC) TX_FRAME_SYNC Serial Data Out TX_DATA SSC Serial Data In RX_DATA RX_FRAME_SYNC RX_CLOCK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In 505 32072A-AVR32-03/09 AT32UC3A3 Figure 25-19. Time Slot Application Block Diagram SCLK TX_CLOCK FSYNC TX_FRAME_SYNC Data Out TX_DATA SSC RX_DATA RX_FRAME_SYNC RX_CLOCK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out Serial Data In First Time Slot Dstart Second Time Slot Dend 506 32072A-AVR32-03/09 AT32UC3A3 25.9 User Interface SSC Register Memory Map Register Control Register Clock Mode Register Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Receive Synchronization Holding Register Transmit Synchronization Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Register Name CR CMR RCMR RFMR TCMR TFMR RHR THR RSHR TSHR RC0R RC1R SR IER IDR IMR Access Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read-only Read/Write Read/Write Read/Write Read-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000000CC 0x00000000 0x00000000 0x00000000 Table 25-4. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 507 32072A-AVR32-03/09 AT32UC3A3 25.9.1 Name: Control Register CR Write-only 0x00 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SWRST 14 - 13 - 12 - 11 - 10 - 9 TXDIS 8 TXEN 7 - 6 - 5 - 4 - 3 - 2 - 1 RXDIS 0 RXEN * SWRST: Software Reset 1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR. 0: Writing a zero to this bit has no effect. * TXDIS: Transmit Disable 1: Writing a one to this bit will disable the transmission. If a character is currently being transmitted, the disable occurs at the end of the current character transmission. 0: Writing a zero to this bit has no effect. * TXEN: Transmit Enable 1: Writing a one to this bit will enable the transmission if the TXDIS bit is not written to one. 0: Writing a zero to this bit has no effect. * RXDIS: Receive Disable 1: Writing a one to this bit will disable the reception. If a character is currently being received, the disable occurs at the end of current character reception. 0: Writing a zero to this bit has no effect. * RXEN: Receive Enable 1: Writing a one to this bit will enables the reception if the RXDIS bit is not written to one. 0: Writing a zero to this bit has no effect. 508 32072A-AVR32-03/09 AT32UC3A3 25.9.2 Name: Clock Mode Register CMR Read/Write 0x04 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 DIV[11:8] 9 8 7 6 5 4 DIV[7:0] 3 2 1 0 * DIV[11:0]: Clock Divider The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is CLK_SSC/(2 x 4095) = CLK_SSC/8190. The clock divider is not active when DIV equals zero. Divided Clock = CLK_SSC ( DIV x 2) 509 32072A-AVR32-03/09 AT32UC3A3 25.9.3 Name: Receive Clock Mode Register RCMR Read/Write 0x10 0x00000000 Access Type: Offset: Reset value: 31 30 29 28 PERIOD 27 26 25 24 23 22 21 20 STTDLY 19 18 17 16 15 - 14 - 13 - 12 STOP 11 10 START 9 8 7 CKG 6 5 CKI 4 3 CKO 2 1 CKS 0 * PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated. If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods. * STTDLY: Receive Start Delay If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the receiver is programmed to start synchronously with the transmitter, the delay is also applied. Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive Sync Data reception. * STOP: Receive Stop Selection 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new Compare 0. 510 32072A-AVR32-03/09 AT32UC3A3 * START: Receive Start Selection START 0 1 2 3 4 5 6 7 8 Others Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RX_FRAME_SYNC signal Detection of a high level on RX_FRAME_SYNC signal Detection of a falling edge on RX_FRAME_SYNC signal Detection of a rising edge on RX_FRAME_SYNC signal Detection of any level change on RX_FRAME_SYNC signal Detection of any edge on RX_FRAME_SYNC signal Compare 0 Reserved * CKG: Receive Clock Gating Selection CKG 0 1 2 3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RX_FRAME_SYNC is low Receive Clock enabled only if RX_FRAME_SYNC is high Reserved * CKI: Receive Clock Inversion CKI affects only the receive clock and not the output clock signal. 1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is shifted out on receive clock falling edge. 0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is shifted out on receive clock rising edge. * CKO: Receive Clock Output Mode Selection CKO 0 1 2 Others Receive Clock Output Mode None Continuous receive clock Receive clock only during data transfers Reserved RX_CLOCK pin Input-only Output Output * CKS: Receive Clock Selection CKS 0 1 2 3 Selected Receive Clock Divided clock TX_CLOCK clock signal RX_CLOCK pin Reserved 511 32072A-AVR32-03/09 AT32UC3A3 25.9.4 Name: Receive Frame Mode Register RFMR Read/Write 0x14 0x00000000 Access Type: Offset: Reset value: 31 30 FSLENHI 29 28 27 - 26 - 25 - 24 FSEDGE 23 - 22 21 FSOS 20 19 18 FSLEN 17 16 15 - 14 - 13 - 12 - 11 10 DATNB 9 8 7 MSBF 6 - 5 LOOP 4 3 2 DATLEN 1 0 * FSLENHI: Receive Frame Sync Length High Part The four MSB of the FSLEN field. * FSEDGE: Receive Frame Sync Edge Detection Determines which edge on Frame Sync will generate the SR.RXSYN interrupt. FSEDGE 0 1 Frame Sync Edge Detection Positive edge detection Negative edge detection * FSOS: Receive Frame Sync Output Selection FSOS 0 1 2 3 4 5 Others Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RX_FRAME_SYNC Pin Input-only Output Output Output Output Output Undefined * FSLEN: Receive Frame Sync Length This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register. When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. Note: The four most significant bits for this field are located in the FSLENHI field. The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive Frame Sync signal is generated during one receive clock period. 512 32072A-AVR32-03/09 AT32UC3A3 * DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). * MSBF: Most Significant Bit First 1: The most significant bit of the data register is sampled first in the bit stream. 0: The lowest significant bit of the data register is sampled first in the bit stream. * LOOP: Loop Mode 1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK. 0: Normal operating mode. * DATLEN: Data Length The bit stream contains (DATLEN + 1) data bits. This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the receiver. DATLEN 0 1-7 8-15 Others Transfer Size Forbidden value Data transfer are in bytes Data transfer are in halfwords Data transfer are in words 513 32072A-AVR32-03/09 AT32UC3A3 25.9.5 Name: Transmit Clock Mode Register TCMR Read/Write 0x18 0x00000000 Access Type: Offset: Reset value: 31 30 29 28 PERIOD 27 26 25 24 23 22 21 20 STTDLY 19 18 17 16 15 - 14 - 13 - 12 - 11 10 START 9 8 7 CKG 6 5 CKI 4 3 CKO 2 1 CKS 0 * PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal. If equal to zero, no signal is generated. If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods. * STTDLY: Transmit Start Delay If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission. When the transmitter is programmed to start synchronously with the receiver, the delay is also applied. Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission. * START: Transmit Start Selection START 0 1 2 3 4 5 6 7 Others Transmit Start Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TX_FRAME_SYNC signal Detection of a high level on TX_FRAME_SYNC signal Detection of a falling edge on TX_FRAME_SYNC signal Detection of a rising edge on TX_FRAME_SYNC signal Detection of any level change on TX_FRAME_SYNC signal Detection of any edge on TX_FRAME_SYNC signal Reserved 514 32072A-AVR32-03/09 AT32UC3A3 * CKG: Transmit Clock Gating Selection CKG 0 1 2 3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TX_FRAME_SYNC is low Transmit Clock enabled only if TX_FRAME_SYNC is high Reserved * CKI: Transmit Clock Inversion CKI affects only the Transmit Clock and not the output clock signal. 1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is sampled on transmit clock falling edge. 0: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock falling edge. The Frame sync signal input is sampled on transmit clock rising edge. * CKO: Transmit Clock Output Mode Selection CKO 0 1 2 Others Transmit Clock Output Mode None Continuous transmit clock Transmit clock only during data transfers Reserved TX_CLOCK pin Input-only Output Output * CKS: Transmit Clock Selection CKS 0 1 2 3 Selected Transmit Clock Divided Clock RX_CLOCK clock signal TX_CLOCK Pin Reserved 515 32072A-AVR32-03/09 AT32UC3A3 25.9.6 Name: Transmit Frame Mode Register TFMR Read/Write 0x1C 0x00000000 Access Type: Offset: Reset value: 31 30 FSLENHI 29 28 27 - 26 - 25 - 24 FSEDGE 23 FSDEN 22 21 FSOS 20 19 18 FSLEN 17 16 15 - 14 - 13 - 12 - 11 10 DATNB 9 8 7 MSBF 6 - 5 DATDEF 4 3 2 DATLEN 1 0 * FSLENHI: Transmit Frame Sync Length High Part The four MSB of the FSLEN field. * FSEDGE: Transmit Frame Sync Edge Detection Determines which edge on Frame Sync will generate the SR.TXSYN interrupt. FSEDGE 0 1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection * FSDEN: Transmit Frame Sync Data Enable 1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. 0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal. * FSOS: Transmit Frame Sync Output Selection FSOS 0 1 2 3 4 5 Others Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TX_FRAME_SYNC Pin Input-only Output Output Output Output Output Undefined * FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if TFMR.FSDEN is equal to one. Note: The four most significant bits for this field are located in the FSLENHI field. 516 32072A-AVR32-03/09 AT32UC3A3 The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256 transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock period. DATNB: Data Number per Frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1). MSBF: Most Significant Bit First 1: The most significant bit of the data register is shifted out first in the bit stream. 0: The lowest significant bit of the data register is shifted out first in the bit stream. DATDEF: Data Default Value This bit defines the level driven on the TX_DATA pin while out of transmission. Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one. 1: The level driven on the TX_DATA pin while out of transmission is one. 0: The level driven on the TX_DATA pin while out of transmission is zero. DATLEN: Data Length The bit stream contains (DATLEN + 1) data bits. This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter. * * * * DATLEN 0 1-7 8-15 Others Transfer Size Forbidden value (1-bit data length is not supported) Data transfer are in bytes Data transfer are in halfwords Data transfer are in words 517 32072A-AVR32-03/09 AT32UC3A3 25.9.7 Name: Receive Holding Register RHR Read-only 0x20 0x00000000 Access Type: Offset: Reset value: 31 30 29 28 RDAT[31:24] 27 26 25 24 23 22 21 20 RDAT[23:16] 19 18 17 16 15 14 13 12 RDAT[15:8] 11 10 9 8 7 6 5 4 RDAT[7:0] 3 2 1 0 * RDAT: Receive Data Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field. 518 32072A-AVR32-03/09 AT32UC3A3 25.9.8 Name: Transmit Holding Register THR Write-only 0x24 0x00000000 Access Type: Offset: Reset value: 31 30 29 28 TDAT[31:24] 27 26 25 24 23 22 21 20 TDAT[23:16] 19 18 17 16 15 14 13 12 TDAT[15:8] 11 10 9 8 7 6 5 4 TDAT[7:0] 3 2 1 0 * TDAT: Transmit Data Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field. 519 32072A-AVR32-03/09 AT32UC3A3 25.9.9 Name: Receive Synchronization Holding Register RSHR Read-only 0x30 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RSDAT[15:8] 11 10 9 8 7 6 5 4 RSDAT[7:0] 3 2 1 0 * RSDAT: Receive Synchronization Data 520 32072A-AVR32-03/09 AT32UC3A3 25.9.10 Name: Transmit Synchronization Holding Register TSHR Read/Write 0x34 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TSDAT[15:8] 11 10 9 8 7 6 5 4 TSDAT[7:0] 3 2 1 0 * TSDAT: Transmit Synchronization Data 521 32072A-AVR32-03/09 AT32UC3A3 25.9.11 Name: Receive Compare 0 Register RC0R Read/Write 0x38 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 CP0[15:8] 11 10 9 8 7 6 5 4 CP0[7:0] 3 2 1 0 * CP0: Receive Compare Data 0 522 32072A-AVR32-03/09 AT32UC3A3 25.9.12 Name: Receive Compare 1 Register RC1R Read/Write 0x3C 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 CP1[[15:8] 11 10 9 8 7 6 5 4 CP1[7:0] 3 2 1 0 * CP1: Receive Compare Data 1 523 32072A-AVR32-03/09 AT32UC3A3 25.9.13 Name: Status Register SR Read-only 0x40 0x000000CC Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 RXEN 16 TXEN 15 - 14 - 13 - 12 - 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 - 6 - 5 OVRUN 4 RXRDY 3 - 2 - 1 TXEMPTY 0 TXRDY * RXEN: Receive Enable This bit is set when the CR.RXEN bit is written to one. This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one. * TXEN: Transmit Enable This bit is set when the CR.TXEN bit is written to one. This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one. * RXSYN: Receive Sync This bit is set when a Receive Sync has occurred. This bit is cleared when the SR register is read. * TXSYN: Transmit Sync This bit is set when a Transmit Sync has occurred. This bit is cleared when the SR register is read. * CP1: Compare 1 This bit is set when compare 1 has occurred. This bit is cleared when the SR register is read. * CP0: Compare 0 This bit is set when compare 0 has occurred. This bit is cleared when the SR register is read. * OVRUN: Receive Overrun This bit is set when data has been loaded in the RHR register while previous data has not yet been read. This bit is cleared when the SR register is read. * RXRDY: Receive Ready This bit is set when data has been received and loaded in the RHR register. This bit is cleared when the RHR register is empty. * TXEMPTY: Transmit Empty This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR register has been transmitted. This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register. 524 32072A-AVR32-03/09 AT32UC3A3 * TXRDY: Transmit Ready This bit is set when the THR register is empty. This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR register. 525 32072A-AVR32-03/09 AT32UC3A3 25.9.14 Name: Interrupt Enable Register IER Write-only 0x44 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 - 6 - 5 OVRUN 4 RXRDY 3 - 2 - 1 TXEMPTY 0 TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 526 32072A-AVR32-03/09 AT32UC3A3 25.9.15 Name: Interrupt Disable Register IDR Write-only 0x48 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 - 6 - 5 OVRUN 4 RXRDY 3 - 2 - 1 TXEMPTY 0 TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 527 32072A-AVR32-03/09 AT32UC3A3 25.9.16 Name: Interrupt Mask Register IMR Read-only 0x4C 0x00000000 Access Type: Offset: Reset value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 - 6 - 5 OVRUN 4 RXRDY 3 - 2 - 1 TXEMPTY 0 TXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 528 32072A-AVR32-03/09 AT32UC3A3 26. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev.4.2.0.3 26.1 Features * Programmable Baud Rate Generator * 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications - 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode - Parity Generation and Error Detection - Framing Error Detection, Overrun Error Detection - MSB- or LSB-first - Optional Break Generation and Detection - By 8 or by 16 Over-sampling Receiver Frequency - Optional Hardware Handshaking RTS-CTS - Optional Modem Signal Management DTR-DSR-DCD-RI - Receiver Time-out and Transmitter Timeguard - Optional Multidrop Mode with Address Generation and Detection RS485 with Driver Control Signal ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards - NACK Handling, Error Counter with Repetition and Iteration Limit IrDA Modulation and Demodulation - Communication at up to 115.2 Kbps SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 LIN Mode - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the "Synch Break" and the "Synch Field" - The "Synch Break" is detected even if it is partially superimposed with a data byte - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification - Checksum sending and verification can be disabled - Support both "Classic" and "Enhanced" checksum types - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal Test Modes - Remote Loopback, Local Loopback, Automatic Echo Supports Connection of Two Peripheral DMA Controller Channels (PDCA) - Offers Buffer Transfer without Processor Intervention * * * * * * * 26.2 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programma529 32072A-AVR32-03/09 AT32UC3A3 ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485, LIN and SPI buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDCA provides chained buffer management without any intervention of the processor. 530 32072A-AVR32-03/09 AT32UC3A3 26.3 Block Diagram Figure 26-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS INTC USART Interrupt TXD Transmitter CTS DTR CLK_USART CLK_USART/DIV DIV RI CLK Modem Signals Control DSR DCD Power Manager BaudRate Generator User Interface Peripheral bus Table 26-1. PIN RXD TXD RTS CTS SPI Operating Mode USART RXD TXD RTS CTS SPI Slave MOSI MISO - CS SPI Master MISO MOSI CS - 531 32072A-AVR32-03/09 AT32UC3A3 26.4 Application Block Diagram Figure 26-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver LIN Driver SPI Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers LIN Transceiver SPI Bus Serial Port Differential Bus 532 32072A-AVR32-03/09 AT32UC3A3 26.5 I/O Lines Description I/O Lines Description Description Serial Clock Transmit Serial Data or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode Receive Serial Data or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send or Slave Select (NSS) in SPI Slave Mode Request to Send or Slave Select (NSS) in SPI Master Mode Type I/O Output Active Level Table 26-2. Name CLK TXD RXD RI DSR DCD DTR CTS RTS Input Input Input Input Output Input Output Low Low Low Low Low Low 533 32072A-AVR32-03/09 AT32UC3A3 26.6 26.6.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. On USARTs not equipped with the corresponding pins, the associated control bits and statuses have no effect on the behavior of the USART. 26.6.2 Clocks The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USART before disabling the clock, to avoid freezing the USART in an undefined state. 26.6.3 Interrupts The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the INTC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 534 32072A-AVR32-03/09 AT32UC3A3 26.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: * 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * RS485 with driver control signal * ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * InfraRed IrDA Modulation and Demodulation * SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 * LIN Mode - Compliant with LIN 1.3 and LIN 2.0 specifications - Master or Slave - Processing of frames with up to 256 data bytes - Response Data length can be configurable or defined automatically by the Identifier - Self synchronization in Slave node configuration - Automatic processing and verification of the "Synch Break" and the "Synch Field" - The "Synch Break" is detected even if it is partially superimposed with a data byte - Automatic Identifier parity calculation/sending and verification - Parity sending and verification can be disabled - Automatic Checksum calculation/sending and verification - Checksum sending and verification can be disabled - Support both "Classic" and "Enhanced" checksum types 535 32072A-AVR32-03/09 AT32UC3A3 - Full LIN error checking and reporting - Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. - Generation of the Wakeup signal * Test modes - Remote loopback, local loopback, automatic echo 26.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (MR) between: * CLK_USART * a division of CLK_USART, the divider being product dependent, but generally set to 8 * the external clock, available on the CLK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external CLK clock is selected, the duration of the low and high levels of the signal provided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal provided on CLK must be at least 4.5 times lower than CLK_USART. Figure 26-3. Baud Rate Generator USCLKS CD CD 0 1 2 3 0 CLK_USART CLK_USART/DIV CLK Reserved CLK 16-bit Counter >1 1 0 1 1 SYNC USCLKS= 3 Sampling Clock OVER 0 Sampling Divider 0 BaudRate Clock FIDI SYNC 26.7.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. 536 32072A-AVR32-03/09 AT32UC3A3 The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 - Over )CD ) This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the highest possible clock and that OVER is programmed at 1. 26.7.1.2 Baud Rate Calculation Example Table 26-3 on page 537 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 98 114 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06% Error Table 26-3. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000 The baud rate is calculated with the following formula: BaudRate = ( CLKUSART ) CD x 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. 537 32072A-AVR32-03/09 AT32UC3A3 ExpectedBaudRate Error = 1 - -------------------------------------------------- ActualBaudRate 26.7.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 - Over ) CD + FP ----- 8 The modified architecture is presented below: Figure 26-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP CD CLK FIDI >1 1 0 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 Sampling Divider 0 BaudRate Clock OVER SYNC CLK_USART CLK_USART/DIV CLK Reserved 0 1 16-bit Counter 2 3 glitch-free logic 26.7.1.4 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in BRGR. BaudRate = SelectedClock ------------------------------------CD 538 32072A-AVR32-03/09 AT32UC3A3 In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART CLK pin. No division is active. The value written in BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd. 26.7.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- x f Fi where: * B is the bit rate * Di is the bit-rate adjustment factor * Fi is the clock frequency division factor * f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 26-4 on page 539. Table 26-4. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 26-5 on page 539. Table 26-5. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 26-6 on page 539 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 26-6. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 539 32072A-AVR32-03/09 AT32UC3A3 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 26-5 on page 540 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 26-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 26.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (THR). If a timeguard is programmed, it is handled normally. 540 32072A-AVR32-03/09 AT32UC3A3 26.7.3 26.7.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 26-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. Figure 26-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 541 32072A-AVR32-03/09 AT32UC3A3 26.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 26-8 on page 542 illustrates this coding scheme. Figure 26-8. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the MAN register, the field TX_PL is used to configure the preamble length. Figure 26-9 on page 543 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. 542 32072A-AVR32-03/09 AT32UC3A3 Figure 26-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 26-10 on page 544 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in MR register must be set to 1. In this case, the MODSYNC field in MR is bypassed and the sync configuration is held in the TXSYNH in the THR register. The USART character format is modified and includes sync information. 543 32072A-AVR32-03/09 AT32UC3A3 Figure 26-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. Figure 26-11. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 26.7.3.3 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (MR). 544 32072A-AVR32-03/09 AT32UC3A3 The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 26-12 on page 545 and Figure 26-13 on page 545 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 26-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 26-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 545 32072A-AVR32-03/09 AT32UC3A3 26.7.3.4 Manchester Decoder When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in MAN. See Figure 26-9 on page 543 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 26-14 on page 546. The sample pulse rejection mechanism applies. Figure 26-14. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 26-15 on page 547 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in CSR register is raised. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. See Figure 26-16 on page 547 for an example of Manchester error detection during data phase. 546 32072A-AVR32-03/09 AT32UC3A3 Figure 26-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 26-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 26.7.3.5 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 26-17 on page 548. 547 32072A-AVR32-03/09 AT32UC3A3 Figure 26-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 26-18 on page 548 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 26-19 on page 549. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 26-18. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd 548 32072A-AVR32-03/09 AT32UC3A3 Figure 26-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 26.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 26-20 on page 549 illustrates a character reception in synchronous mode. Figure 26-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 26.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. 549 32072A-AVR32-03/09 AT32UC3A3 Figure 26-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR Read RHR RXRDY OVRE 550 32072A-AVR32-03/09 AT32UC3A3 26.7.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (MR). The PAR field also enables the Multidrop mode, see "Multidrop Mode" on page 552. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 26-7 on page 551 shows an example of the parity bit for the character 0x41 (character ASCII "A") depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 26-7. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (CSR). The PARE bit can be cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 26-22 on page 552 illustrates the parity bit status setting and clearing. 551 32072A-AVR32-03/09 AT32UC3A3 Figure 26-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write CR PARE RXRDY 26.7.3.9 Multidrop Mode If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to CR. In this case, the next byte written to THR is transmitted as an address. Any character written in THR without having written the command SENDA is transmitted normally with the parity at 0. 26.7.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 26-23 on page 553, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 552 32072A-AVR32-03/09 AT32UC3A3 Figure 26-23. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write THR TXRDY TXEMPTY Table 26-8 on page 553 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 26-8. Maximum Timeguard Length Depending on Baud Rate Bit time s 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 26.7.3.11 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: * Stop the counter clock until a new character is received. This is performed by writing the Control Register (CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to 553 32072A-AVR32-03/09 AT32UC3A3 handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. * Obtain an interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 26-24 on page 554 shows the block diagram of the Receiver Time-out feature. Figure 26-24. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 26-9 on page 554 gives the maximum time-out period for some standard baud rates. Table 26-9. Maximum Time-out Period Bit Time s 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 554 32072A-AVR32-03/09 AT32UC3A3 Table 26-9. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 26.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 26-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR FRAME RXRDY 26.7.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 555 32072A-AVR32-03/09 AT32UC3A3 The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 26-26 on page 556 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 26-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write CR TXRDY TXEMPTY 26.7.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in CSR. This bit may be cleared by writing the Control Register (CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 26.7.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 26-27 on page 557. 556 32072A-AVR32-03/09 AT32UC3A3 Figure 26-27. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDCA channel for reception. The transmitter can handle hardware handshaking in any case. Figure 26-28 on page 557 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDCA channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDCA clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 26-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write CR RTS RXBUFF RXDIS = 1 Figure 26-29 on page 557 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 26-29. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 557 32072A-AVR32-03/09 AT32UC3A3 26.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 26.7.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see "Baud Rate Generator" on page 536). The USART connects to a smart card as shown in Figure 26-30 on page 558. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the CLK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 26-30. Connection of a Smart Card to the USART USART CLK CLK Smart Card TXD I/O When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to "Mode Register" on page 594 and "PAR: Parity Type" on page 595. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (THR) or after reading it in the Receive Holding Register (RHR). 26.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 26-31 on page 559. 558 32072A-AVR32-03/09 AT32UC3A3 If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 26-32 on page 559. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (RHR). It appropriately sets the PARE bit in the Status Register (SR) so that the software can handle the error. Figure 26-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 26-32. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 26.7.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (NER) register. The NB_ERRORS field can record up to 255 errors. Reading NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (SR). The INACK bit can be cleared by writing the Control Register (CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 26.7.4.4 26.7.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 559 32072A-AVR32-03/09 AT32UC3A3 When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1. 26.7.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 26-33 on page 560. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the MODE field in the Mode Register (MR) to the value 0x8. The IrDA Filter Register (IFR) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 26-33. Connection to IrDA Transceivers 26.7.4.7 26.7.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: * Disable TX and Enable RX * Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). 560 32072A-AVR32-03/09 AT32UC3A3 * Receive data 26.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 26-10 on page 561. Table 26-10. IrDA Pulse Duration Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 s 19.53 s 9.77 s 4.88 s 3.26 s 1.63 s Figure 26-34 on page 561 shows an example of character transmission. Figure 26-34. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 26.7.5.2 IrDA Baud Rate Table 26-11 on page 561 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of 1.87% must be met. Table 26-11. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 CD 2 11 18 22 4 22 36 43 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 561 32072A-AVR32-03/09 AT32UC3A3 Table 26-11. IrDA Baud Rate Error (Continued) Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 26.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in IFR. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the CLK_USART speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with IFR. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 26-35 on page 562 illustrates the operations of the IrDA demodulator. Figure 26-35. IrDA Demodulator Operations CLK_USART RXD Counter Value 6 5 4 3 2 6 6 5 4 3 2 1 0 Pulse Accepted Receiver Input Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 562 32072A-AVR32-03/09 AT32UC3A3 26.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 26-36 on page 563. Figure 26-36. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the MODE field in the Mode Register (MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 26-37 on page 563 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 26-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY RTS 563 32072A-AVR32-03/09 AT32UC3A3 26.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 26-12 on page 564 gives the correspondence of the USART signals with modem connection standards. Table 26-12. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the DTR output pin is performed by writing the Control Register (CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 564 32072A-AVR32-03/09 AT32UC3A3 26.7.8 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master" which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI Slave because it can generate only one NSS signal. The SPI system consists of two data lines and two control lines: * Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave. * Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. * Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for each bit that is transmitted. * Slave Select (NSS): This control line allows the master to select or deselect the slave. 26.7.8.1 Modes of Operation The USART can operate in Master Mode or in Slave Mode. Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: * the MOSI line is driven by the output pin TXD * the MISO line drives the input pin RXD * the CLK line is driven by the output pin CLK * the NSS line is driven by the output pin RTS Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: * the MOSI line drives the input pin RXD * the MISO line is driven by the output pin TXD * the CLK line drives the input pin CLK * the NSS line drives the input pin CTS In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 26.7.9.2 on page 570). 565 32072A-AVR32-03/09 AT32UC3A3 26.7.8.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See "Baud Rate in Synchronous Mode or SPI Mode" on page 538. However, there are some restrictions: In SPI Master Mode: * the external clock CLK must not be selected (USCLKS ... 0x3), and the bit CLKO must be set to "1" in the Mode Register (MR), in order to generate correctly the serial clock on the CLK pin. * to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of must be superior or equal to 4. * if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the internal clock is selected (CLK_USART). In SPI Slave Mode: * the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is provided directly by the signal on the USART CLK pin. * to obtain correct behavior of the receiver and the transmitter, the external clock (CLK) frequency must be at least 4 times lower than the system clock. 566 32072A-AVR32-03/09 AT32UC3A3 26.7.8.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave). Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 26-13. SPI Bus Protocol Mode SPI Bus Protocol Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 1 0 1 0 567 32072A-AVR32-03/09 AT32UC3A3 Figure 26-38. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master ->RXD SPI Slave ->TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master ->RTS SPI Slave ->CTS Figure 26-39. SPI Transfer Format (CPHA=0, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 568 32072A-AVR32-03/09 AT32UC3A3 26.7.8.4 Receiver and Transmitter Control See "Receiver and Transmitter Control" on page 540. Character Transmission The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing the Control Register (CR) with the RTSEN bit at 1. The slave select line (NSS) can be released at high level only by writing the Control Register (CR) with the RTSDIS bit at 1 (for example, when all data have been transferred to the slave device). In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 26.7.8.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 26.7.8.7 Receiver Timeout Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (RTOR). 26.7.8.5 569 32072A-AVR32-03/09 AT32UC3A3 26.7.9 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: * Single Master/Multiple Slaves concept * Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine. * Self synchronization without quartz or ceramic resonator in the slave nodes * Deterministic signal transmission * Low cost single-wire implementation * Speed up to 20 kbit/s LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required. The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor. 26.7.9.1 Modes of operation The USART can act either as a LIN Master node or as a LIN Slave node. The node configuration is chosen by setting the MODE field in the USART3 Mode register (MR): * LIN Master Node (MODE=0xA) * LIN Slave Node (MODE=0xB) In order to avoid unpredicted behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See Section 26.7.9.2 on page 570) 26.7.9.2 Receiver and Transmitter Control See "Receiver and Transmitter Control" on page 540. Character Transmission See "Transmitter Operations" on page 541. Character Reception See "Receiver Operations" on page 549. 26.7.9.3 26.7.9.4 570 32072A-AVR32-03/09 AT32UC3A3 26.7.9.5 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (LINIR). At this moment the flag TXRDY falls. The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other. The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the Identifier corresponds to the character written in the LIN Identifier Register (LINIR). The Identifier parity bits can be automatically computed and sent (see Section 26.7.9.8 on page 574). The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter. Figure 26-40. Header Transmission Baud Rate Clock TXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Write LINIR LINIR TXRDY ID 571 32072A-AVR32-03/09 AT32UC3A3 26.7.9.6 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has not been detected, the USART stays idle and the received data are not taken in account. When a Break Field has been detected, the USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized (see Section 26.7.9.7 on page 572). If the received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see Section 26.7.10 on page 579). After receiving the Synch Field, the USART expects to receive the Identifier Field. When the Identifier has been received, the flag LINID is set to "1". At this moment the field IDCHR in the LIN Identifier register (LINIR) is updated with the received character. The Identifier parity bits can be automatically computed and checked (see Section 26.7.9.8 on page 574). Figure 26-41. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Synch Byte = 0x55 LINID US_LINIR Write US_CR With RSTSTA=1 26.7.9.7 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 26-42. Synch Field Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit Start bit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 26.7.1 on page 536). 572 32072A-AVR32-03/09 AT32UC3A3 When the start bit of the Synch Field is detected the counter is reset. Then during the next 8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new fractional part (FP). When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud Rate Generator register (BRGR). Figure 26-43. Slave Node Synchronization Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINIDRX Reset Synchro Counter BRGR Clcok Divider (CD) BRGR Fractional Part (FP) Initial CD Initial FP 000_0011_0001_0110_1101 0000_0110_0010_1101 101 The accuracy of the synchronization depends on several parameters: * The nominal clock frequency (FNom) (the theoretical slave node clock frequency) * The Baudrate * The oversampling (Over=0 => 16X or Over=0 => 8X) The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (FSLAVE is the real slave node clock frequency). [ x 8 x ( 2 - Over ) + ] x Baudrate Baudrate_deviation = 100 x -------------------------------------------------------------------------------------------- % 8 x F SLAVE [ x 8 x ( 2 - Over ) + ] x Baudrate Baudrate_deviation = 100 x -------------------------------------------------------------------------------------------- % F TOL_UNSYNCH -------------------------------------- xF 8x Nom 100 - 0,5 +0,5 -1 < < +1 FTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed 15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than 2%. This means that the Baudrate_deviation must not exceed 1%. It follows from that, a minimum value for the nominal clock frequency: 573 32072A-AVR32-03/09 AT32UC3A3 [ 0,5 x 8 x ( 2 - Over ) + 1 ] x Baudrate F NOM ( min ) = 100 x ----------------------------------------------------------------------------------------------- Hz - 15 8 x --------- + 1 x 1% 100 Examples: * Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 2.64 MHz * Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 1.47 MHz * Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 132 kHz * Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 74 kHz If the fractional baud rate is not used, the accuracy of the synchronization becomes much lower. When the counter is stopped, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD). This value is rounded by adding the first insignificant bit. The equation of the Baudrate deviation is the same as given above, but the constants are as follows: - 4 +4 -1 < < +1 It follows from that, a minimum value for the nominal clock frequency: [ 4 x 8 x ( 2 - Over ) + 1 ] x Baudrate F (min) = 100 x ------------------------------------------------------------------------------------------ Hz NOM - 15 8 x --------- + 1 x 1% 100 Examples: * Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 19.12 MHz * Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 9.71 MHz * Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 956 kHz * Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 485 kHz 26.7.9.8 Identifier Parity A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can choose between two modes by the PARDIS bit of the LIN Mode register (LINMR): * PARDIS = 0: During header transmission, the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register (LINIR). The bits 6 and 7 of this register are discarded. During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error occurs (see Section 26.7.3.8 on page 551). Only the 6 least significant bits of the IDCHR field are updated with the received Identifier. The bits 6 and 7 are stuck at 0. * PARDIS = 1: During header transmission, all the bits of the IDCHR field of the LIN Identifier register (LINIR) are sent on the bus. During header reception, all the bits of the IDCHR field are updated with the received Identifier. 574 32072A-AVR32-03/09 AT32UC3A3 26.7.9.9 Node Action In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: * PUBLISH: the node sends the response. * SUBSCRIBE: the node receives the response. * IGNORE: the node is not concerned by the response, it does not send and does not receive the response. This configuration is made by the field, Node Action (NACT), in the LINMR register (see Section 26.8.16 on page 613). Example: a LIN cluster that contains a Master and two Slaves: * Data transfer from the Master to the Slave 1 and to the Slave 2: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=SUBSCRIBE * Data transfer from the Master to the Slave 1 only: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=IGNORE * Data transfer from the Slave 1 to the Master: NACT(Master)=SUBSCRIBE NACT(Slave1)=PUBLISH NACT(Slave2)=IGNORE * Data transfer from the Slave1 to the Slave2: NACT(Master)=IGNORE NACT(Slave1)=PUBLISH NACT(Slave2)=SUBSCRIBE * Data transfer from the Slave2 to the Master and to the Slave1: NACT(Master)=SUBSCRIBE NACT(Slave1)=SUBSCRIBE NACT(Slave2)=PUBLISH 575 32072A-AVR32-03/09 AT32UC3A3 26.7.9.10 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode register (LINMR): * DLM = 0: the response data length is configured by the user via the DLC field of the LIN Mode register (LINMR). The response data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. * DLM = 1: the response data length is defined by the Identifier (IDCHR in LINIR) according to the table below. The DLC field of the LIN Mode register (LINMR) is discarded. The response can contain 2 or 4 or 8 data bytes. Table 26-14. Response Data Length if DLM = 1 IDCHR[5] 0 0 1 1 IDCHR[4] 0 1 0 1 Response Data Length [bytes] 2 2 4 8 Figure 26-44. Response Data Length User configuration: 1 - 256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break Sync Field Identifier Field Data Field Data Field Data Field Data Field Checksum Field 576 32072A-AVR32-03/09 AT32UC3A3 26.7.9.11 Checksum The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves. The USART can be configured to: * Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0) * Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1) * Not send/check a checksum (CHKDIS = 1) This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of the LIN Mode register (LINMR). If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see Section 26.7.9.10 on page 576). 577 32072A-AVR32-03/09 AT32UC3A3 26.7.9.12 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum. If the Frame Slot Mode is disabled (FDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately. The TFrame_Maximum is calculated as below: If the Checksum is sent (CHKDIS = 0): * THeader_Nominal = 34 x TBit * TResponse_Nominal = 10 x (NData + 1) x TBit * TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(Note:) * TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) x TBIT * TFrame_Maximum = (77 + 14 x DLC) x TBIT If the Checksum is not sent (CHKDIS = 1): * THeader_Nominal = 34 x TBit * TResponse_Nominal = 10 x NData x TBit * TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1(Note:)) * TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) x TBIT * TFrame_Maximum = (63 + 14 x DLC) x TBIT Note: The term "+1" leads to an integer result for TFrame_Max (LIN Specification 1.3) Figure 26-45. Frame Slot Mode Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY Frame Slot Mode Frame Slot Mode Disabled Enabled Write LINID Write THR LINTC Data 1 Data 2 Data 3 Data N 578 32072A-AVR32-03/09 AT32UC3A3 26.7.10 26.7.10.1 LIN Errors Bit Error This error is generated when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. 26.7.10.2 Inconsistent Synch Field Error This error is generated in Slave node configuration if the Synch Field character received is other than 0x55. Parity Error This error is generated if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). 26.7.10.4 Checksum Error This error is set if the received checksum is wrong. This error can be generated only if the checksum feature is enabled (CHKDIS = 0). Slave Not Responding Error This error is set when the USART expects a response from another node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time frame given by the maximum length of the message frame, TFrame_Maximum (see Section 26.7.9.12 on page 578). This error is disabled if the USART does not expect any message (NACT = PUBLISH or NACT = IGNORE). 26.7.10.3 26.7.10.5 579 32072A-AVR32-03/09 AT32UC3A3 26.7.11 26.7.11.1 LIN Frame Handling Master Node Configuration * Write TXEN and RXEN in CR to enable both the transmitter and the receiver. * Write MODE in MR to select the LIN mode and the Master Node configuration. * Write CD and FP in BRGR to configure the baud rate. * Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FDIS and DLC in LINMR to configure the frame transfer. * Check that TXRDY in CSR is set to "1" * Write IDCHR in LINIR to send the header What comes next depends on the NACT configuration: * Case 1: NACT = PUBLISH, the USART sends the response - Wait until TXRDY in CSR rises - Write TCHR in THR to send a byte - If all the data have not been written, redo the two previous steps - Wait until LINTC in CSR rises - Check the LIN errors * Case 2: NACT = SUBSCRIBE, the USART receives the response - Wait until RXRDY in CSR rises - Read RCHR in RHR - If all the data have not been read, redo the two previous steps - Wait until LINTC in CSR rises - Check the LIN errors * Case 3: NACT = IGNORE, the USART is not concerned by the response - Wait until LINTC in CSR rises - Check the LIN errors 580 32072A-AVR32-03/09 AT32UC3A3 Figure 26-46. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Data3 Response space Interframe space Response Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR Write THR LINTC Data 1 Data 2 Data 3 Data N FSDIS=0 Figure 26-47. Master Node Configuration, NACT=SUBSCRIBE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read RHR LINTC Data 1 Data N-2 Data N-1 Data N 581 32072A-AVR32-03/09 AT32UC3A3 Figure 26-48. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR LINTC FSDIS=0 26.7.11.2 Slave Node Configuration * Write TXEN and RXEN in CR to enable both the transmitter and the receiver. * Write MODE in MR to select the LIN mode and the Slave Node configuration. * Write CD and FP in BRGR to configure the baud rate. * Wait until LINID in CSR rises * Check LINISFE and LINPE errors * Read IDCHR in RHR * Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in LINMR to configure the frame transfer. IMPORTANT: if the NACT configuration for this frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding PDC write transfer request. What comes next depends on the NACT configuration: * Case 1: NACT = PUBLISH, the USART sends the response - Wait until TXRDY in CSR rises - Write TCHR in THR to send a byte - If all the data have not been written, redo the two previous steps - Wait until LINTC in CSR rises - Check the LIN errors * Case 2: NACT = SUBSCRIBE, the USART receives the response - Wait until RXRDY in CSR rises - Read RCHR in RHR - If all the data have not been read, redo the two previous steps - Wait until LINTC in CSR rises - Check the LIN errors 582 32072A-AVR32-03/09 AT32UC3A3 * Case 3: NACT = IGNORE, the USART is not concerned by the response - Wait until LINTC in CSR rises - Check the LIN errors Figure 26-49. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR LINTC Data 1 Data 2 Data 3 Data N Figure 26-50. Slave Node Configuration, NACT = SUBSCRIBE Break TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC Data 1 Data N-2 Data N-1 Data N Synch Protected Identifier Data 1 Data N-1 Data N Checksum Figure 26-51. Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC 583 32072A-AVR32-03/09 AT32UC3A3 26.7.12 LIN Frame Handling With The Peripheral DMA Controller The USART can be used in association with the Peripheral DMA Controller (PDCA) in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The PDCA uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDCA always writes in the Transmit Holding register (THR) and it always reads in the Receive Holding register (RHR). The size of the data written or read by the PDCA in the USART is always a byte. 26.7.12.1 Master Node Configuration The user can choose between two PDCA modes by the PDCM bit in the LIN Mode register (LINMR): * PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDCA in the Transmit Holding register THR (instead of the LIN Mode register LINMR). Because the PDCA transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are written. During the second access the 8-bit DLC field is written. * PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN Mode register (LINMR). The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 26-52. Master Node with PDCA (PDCM=1) WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC NODE ACTION = PUBLISH Peripheral bus PDCA (DMA) DATA 0 RXRDY DATA 0 TXRDY USART3 LIN CONTROLLER IDENTIFIER Peripheral bus PDCA (DMA) USART3 LIN CONTROLLER NODE ACTION = SUBSCRIBE IDENTIFIER READ BUFFER RXRDY | | | | | | | | DATA N DATA N 584 32072A-AVR32-03/09 AT32UC3A3 Figure 26-53. Master Node with PDCA (PDCM=0) WRITE BUFFER WRITE BUFFER IDENTIFIER NODE ACTION = PUBLISH IDENTIFIER NODE ACTION = SUBSCRIBE Peripheral bus READ BUFFER PDCA (DMA) PDCA (DMA) USART3 LIN CONTROLLER DATA 0 Peripheral bus | | | | USART3 LIN CONTROLLER RXRDY DATA 0 RXRDY TXRDY DATA N | | | | DATA N 26.7.12.2 Slave Node Configuration In this configuration, the PDCA transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (LINIR). The LIN mode must be written by the user in the LIN Mode register (LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). IMPORTANT: if the NACT configuration for a frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding PDC write transfer request. Figure 26-54. Slave Node with PDCA WRITE BUFFER READ BUFFER DATA 0 Peripheral bus PDCA (DMA) TXRDY USART3 LIN CONTROLLER DATA 0 Peripheral Bus | | | | NACT = SUBSCRIBE | | | | PDCA (DMA) RXRDY USART3 LIN CONTROLLER DATA N DATA N 585 32072A-AVR32-03/09 AT32UC3A3 26.7.13 Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 s to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits. Whatever the baud rate is, this character respects the specified timings. * Baud rate min = 1 kbit/s -> Tbit = 1ms -> 5 Tbits = 5 ms * Baud rate max = 20 kbit/s -> Tbi t= 50 s -> 5 Tbits = 250 s In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. The user can choose by the WKUPTYP bit in the LIN Mode register (LINMR) either to send a LIN 2.0 wakeup request (WKUPTYP=0) or to send a LIN 1.3 wakeup request (WKUPTYP=1). A wake-up request is transmitted by writing the Control Register (CR) with the LINWKUP bit at 1. Once the transfer is completed, the LINTC flag is asserted in the Status Register (SR). It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. 586 32072A-AVR32-03/09 AT32UC3A3 26.7.14 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a 17-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. If STTTO is performed, the counter clock is stopped until a first character is received. If RETTO is performed, the counter starts counting down immediately from the value TO. Table 26-15. Receiver Time-out programming LIN Specification Baud Rate 1 000 bit/s 2 400 bit/s 2.0 9 600 bit/s 19 200 bit/s 20 000 bit/s 1.3 25 000 Tbits 4s Time-out period TO 4 000 9 600 38 400 76 800 80 000 25 000 587 32072A-AVR32-03/09 AT32UC3A3 26.7.15 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 26.7.15.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 26-55. Normal Mode Configuration RXD Receiver TXD Transmitter 26.7.15.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 26-56 on page 588. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 26-56. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 26.7.15.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 26-57 on page 588. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 26-57. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 588 32072A-AVR32-03/09 AT32UC3A3 26.7.15.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 26-58 on page 589. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 26-58. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 589 32072A-AVR32-03/09 AT32UC3A3 26.7.16 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the USART Write Protect Mode Register (WPMR) with the appropriate access key, WPKEY. The protected registers are: * "Mode Register" on page 594 * "Baud Rate Generator Register" on page 605 * "Receiver Time-out Register" on page 606 * "Transmitter Timeguard Register" on page 607 * "FI DI RATIO Register" on page 608 * "IrDA FILTER Register" on page 610 * "Manchester Configuration Register" on page 611 590 32072A-AVR32-03/09 AT32UC3A3 26.8 User Interface Table 26-16. USART Register Memory Map Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0040 0x0044 0x004C 0x0050 0x0054 0x0058 0xE4 0xE8 0xFC Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register FI DI Ratio Register Number of Errors Register IrDA Filter Register Manchester Encoder Decoder Register LIN Mode Register LIN Identifier Register Write Protect Mode Register Write Protect Status Register Version Register Note: Note: Name CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IFR MAN LINMR LINIR WPMR WPSR VERSION Write is possible only in LIN Master node configuration. Values in the Version Register vary with the version of the IP block implementation. Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write Read-write Read-only Read-write Read-write Read-write Read-write (Note:) Reset - 0x00000000 - - 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000174 0x00000000 0x00000000 0x30011004 0x00000000 0x00000000 0x00000000 0x00000000 0x-(Note:) Read-write Read-only Read-only 591 32072A-AVR32-03/09 AT32UC3A3 26.8.1 Name: Control Register CR Write-only 0x0 30 - 22 - 14 RSTNACK 6 TXEN 29 - 21 LINWKUP 13 RSTIT 5 RXDIS 28 - 20 LINABT 12 SENDA 4 RXEN 27 - 19 RTSDIS/RCS 11 STTTO 3 RSTTX 26 - 18 RTSEN/FCS 10 STPBRK 2 RSTRX 25 - 17 DTRDIS 9 STTBRK 1 - 24 - 16 DTREN 8 RSTSTA 0 - Access Type: Offset: Reset Value: 31 - 23 - 15 RETTO 7 TXDIS * LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus. LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select If USART does not operate in SPI Master Mode (MODE ... 0xE): 0: No effect. 1: Drives the pin RTS to 1. If USART operates in SPI Master Mode (MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). RTSEN/FCS: Request to Send Enable/Force SPI Chip Select If USART does not operate in SPI Master Mode (MODE ... 0xE): 0: No effect. 1: Drives the pin RTS to 0. If USART operates in SPI Master Mode (MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. RETTO: Rearm Time-out 0: No effect 1: Restart Time-out * * * * * * 592 32072A-AVR32-03/09 AT32UC3A3 * RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in CSR. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled. SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set. STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR. STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINSFE, LINIPE, LINCE, LINSNRE and RXBRK in CSR. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. * * * * * * * * * * * * 593 32072A-AVR32-03/09 AT32UC3A3 26.8.2 Name: Mode Register MR Read-write 0x4 30 MODSYNC 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 - 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: Offset: Reset Value: 31 ONEBIT 23 - 15 18 CLKO 10 PAR 2 MODE 16 MSBF/CPOL 8 SYNC/CPHA 0 1 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into THR register. DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. * * * * * * * * 594 32072A-AVR32-03/09 AT32UC3A3 * CLKO: Clock Output Select 0: The USART does not drive the CLK pin. 1: The USART drives the CLK pin if USCLKS does not select the external clock CLK. * MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. * MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode (MODE ... 0xE and 0xF): MSBF = 0: Least Significant Bit is sent/received first. MSBF = 1: Most Significant Bit is sent/received first. If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero. CPOL = 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. * CHMODE: Channel Mode Table 26-17. CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. * NBSTOP: Number of Stop Bits Table 26-18. NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved * PAR: Parity Type Table 26-19. PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode 595 32072A-AVR32-03/09 AT32UC3A3 * SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase If USART does not operate in SPI Mode (MODE is ... 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. If USART operates in SPI Mode (MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CHRL: Character Length. Table 26-20. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits * USCLKS: Clock Selection Table 26-21. USCLKS 0 0 1 1 0 1 0 1 Selected Clock CLK_USART CLK_USART/DIV (DIV = xx) Reserved CLK * MODE Table 26-22. MODE 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 Others 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 0 1 Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA LIN Master LIN Slave SPI Master SPI Slave Reserved 596 32072A-AVR32-03/09 AT32UC3A3 26.8.3 Name: Interrupt Enable Register IER Write-only 0x8 30 - 22 - 14 LINiD 6 FRAME 29 LINSNRE 21 - 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 - 27 LINIPE 19 CTSIC 11 - 3 - 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 - 23 - 15 LINTC 7 PARE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect. 597 32072A-AVR32-03/09 AT32UC3A3 26.8.4 Name: Interrupt Disable Register IDR Write-only 0xC 30 - 22 - 14 LINID 6 FRAME 29 LINSNRE 21 - 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 - 27 LINIPE 19 CTSIC 11 - 3 - 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 - 23 - 15 LINTC 7 PARE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has the same effect. 598 32072A-AVR32-03/09 AT32UC3A3 26.8.5 Name: Interrupt Mask Register IMR Read-only 0x10 30 - 22 - 14 LINID 6 FRAME 29 LINSNRE 21 - 13 NACK/LINBK 5 OVRE 28 LINCE 20 MANE 12 RXBUFF 4 - 27 LINIPE 19 CTSIC 11 - 3 - 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANEA 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 - 23 - 15 LINTC 7 PARE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is cleared when the corresponding bit in IER is written to one. For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other has the same effect. 599 32072A-AVR32-03/09 AT32UC3A3 26.8.6 Name: Channel Status Register CSR Read-only 0x14 30 - 22 DCD 14 LINID 6 FRAME 29 LINSNRE 21 DSR 13 NACK/LINBK 5 OVRE 28 LINCE 20 RI 12 RXBUFF 4 - 27 LINIPE 19 CTSIC 11 - 3 - 26 LINISFE 18 DCDIC 10 ITER/UNRE 2 RXBRK 25 LINBE 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANERR 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 - 23 CTS 15 LINTC 7 PARE * LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA. LINCE: LIN Checksum Error 0: No LIN Checksum Error has been detected since the last RSTSTA. 1: A LIN Checksum Error has been detected since the last RSTSTA. LINIPE: LIN Identifier Parity Error 0: No LIN Identifier Parity Error has been detected since the last RSTSTA. 1: A LIN Identifier Parity Error has been detected since the last RSTSTA. LINISFE: LIN Inconsistent Synch Field Error 0: No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA 1: The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last RSTSTA. LINBE: LIN Bit Error 0: No Bit Error has been detected since the last RSTSTA. 1: A Bit Error has been detected since the last RSTSTA. MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. * * * * * * * * 600 32072A-AVR32-03/09 AT32UC3A3 * RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of CSR. 1: At least one input change has been detected on the CTS pin since the last read of CSR. DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of CSR. 1: At least one input change has been detected on the DCD pin since the last read of CSR. DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of CSR. 1: At least one input change has been detected on the DSR pin since the last read of CSR. RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of CSR. 1: At least one input change has been detected on the RI pin since the last read of CSR. LINTC: LIN Transfer Completed 0: The USART is idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA. LINIR: LIN Identifier Received 0: No LIN Identifier Received 1: The USART is configured as a Slave node and a LIN Identifier has been received since the last RSTSTA. NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDCA channel is inactive. 1: The signal Buffer Full from the Receive PDCA channel is active. ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error If USART does not operate in SPI Slave Mode (MODE ... 0xF): ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA. ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA. If USART operates in SPI Slave Mode (MODE = 0xF): UNRE = 0: No SPI underrun error has occurred since the last RSTSTA. UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in THR, nor in the Transmit Shift Register. TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in CR). PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. RXBRK: Break Received/End of Break * * * * * * * * * * * * * * * 601 32072A-AVR32-03/09 AT32UC3A3 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. * TXRDY: Transmitter Ready 0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the THR. * RXRDY: Receiver Ready 0: No complete character has been received since the last read of RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and RHR has not yet been read. 602 32072A-AVR32-03/09 AT32UC3A3 26.8.7 Name: Receive Holding Register RHR Read-only 0x18 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 RXCHR 0 Access Type: Offset: Reset Value: 31 - 23 - 15 RXSYNH 7 * RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. * RXCHR: Received Character Last character received if RXRDY is set. 603 32072A-AVR32-03/09 AT32UC3A3 26.8.8 Name: USART Transmit Holding Register THR Write-only 0x1C 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 TXCHR 0 Access Type: Offset: Reset Value: 31 - 23 - 15 TXSYNH 7 * TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 604 32072A-AVR32-03/09 AT32UC3A3 26.8.9 Name: Baud Rate Generator Register BRGR Read-write 0x20 0x00000000 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CD 7 6 5 4 CD 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 FP 9 24 - 16 Access Type: Offset: Reset Value: 31 - 23 - 15 10 8 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. * CD: Clock Divider Table 26-23. MODE ISO7816 SYNC = 1 or MODE = SPI (Master or Slave) OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO MODE = ISO7816 SYNC = 0 CD 0 1 to 65535 OVER = 0 605 32072A-AVR32-03/09 AT32UC3A3 26.8.10 Name: Receiver Time-out Register RTOR Read-write 0x24 0x00000000 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TO 7 6 5 4 TO 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 TO 8 Access Type: Offset: Reset Value: 31 - 23 - 15 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 606 32072A-AVR32-03/09 AT32UC3A3 26.8.11 Name: Transmitter Timeguard Register TTGR Read-write 0x28 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TG 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 607 32072A-AVR32-03/09 AT32UC3A3 26.8.12 Name: FI DI RATIO Register FIDI Read-write 0x40 0x00000174 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FI_DI_RATIO 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FI_DI_RATIO 1 24 - 16 - 8 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 2 0 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on CLK divided by FI_DI_RATIO. 608 32072A-AVR32-03/09 AT32UC3A3 26.8.13 Name: Number of Errors Register NER Read-only 0x44 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 NB_ERRORS 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 * NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 609 32072A-AVR32-03/09 AT32UC3A3 26.8.14 Name: IrDA FILTER Register IFR Read-write 0x4C 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IRDA_FILTER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 610 32072A-AVR32-03/09 AT32UC3A3 26.8.15 Name: Manchester Configuration Register MAN Read-write 0x50 0x30011004 30 DRIFT 22 - 14 - 6 - 29 1 21 - 13 - 5 - 28 RX_MPOL 20 - 12 TX_MPOL 4 - 27 - 19 26 - 18 RX_PL 11 - 3 10 - 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 - This register can only be written if the WPEN bit is cleared in "Write Protect Mode Register" on page 616. * DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. * RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. * RX_PP: Receiver Preamble Pattern detected Table 26-24. RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO * RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period * TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. 611 32072A-AVR32-03/09 AT32UC3A3 * TX_PP: Transmitter Preamble Pattern Table 26-25. TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO * TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period 612 32072A-AVR32-03/09 AT32UC3A3 26.8.16 Name: LIN Mode Register LINMR Read-write 0x54 0x00000000 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 3 CHKDIS 2 PARDIS 1 NACT 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 PDCM 8 Access Type: Offset: Reset Value: 31 - 23 - 15 * PDCM: PDCA Mode 0: The LIN mode register LINMR is not written by the PDCA. 1: The LIN mode register LINMR (excepting that flag) is written by the PDCA. DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes. WKUPTYP: Wakeup Signal Type 0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. FDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. DLM: Data Length Mode 0: The response data length is defined by the field DLC of this register. 1: The response data length is defined by the bits 5 and 6 of the Identifier (IDCHR in LINIR). CHKTYP: Checksum Type 0: LIN 2.0 "Enhanced" Checksum 1: LIN 1.3 "Classic" Checksum CHKDIS: Checksum Disable 0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum is checked automatically. 1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked. PARDIS: Parity Disable 0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configuration, the parity is checked automatically. 1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked. * * * * * * * 613 32072A-AVR32-03/09 AT32UC3A3 * NACT: LIN Node Action Table 1. NACT 0 0 1 1 0 1 0 1 Mode Description PUBLISH: The USART transmits the response. SUBSCRIBE: The USART receives the response. IGNORE: The USART does not transmit and does not receive the response. Reserved 614 32072A-AVR32-03/09 AT32UC3A3 26.8.17 Name: LIN Identifier Register LINIR Read-write or Read-only 0x58 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IDCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 * IDCHR: Identifier Character If MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted. if MODE=0xB (Slave node configuration): IDCHR is Read-only and its value is the last Identifier character that has been received. 615 32072A-AVR32-03/09 AT32UC3A3 26.8.18 Write Protect Mode Register Register Name: WPMR Access Type: Offset: Reset Value: 31 Read-write 0xE4 See Table 26-16 on page 591 30 29 28 WPKEY 27 26 25 24 23 22 21 20 WPKEY 19 18 17 16 15 14 13 12 WPKEY 11 10 9 8 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 WPEN * WPKEY: Write Protect KEY Should be written at value 0x858365 ("USA" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. * WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ASCII). Protects the registers: * "Mode Register" on page 594 * "Baud Rate Generator Register" on page 605 * "Receiver Time-out Register" on page 606 * "Transmitter Timeguard Register" on page 607 * "FI DI RATIO Register" on page 608 * "IrDA FILTER Register" on page 610 * "Manchester Configuration Register" on page 611 616 32072A-AVR32-03/09 AT32UC3A3 26.8.19 Write Protect Status Register Register Name: WPSR Access Type: Offset: Reset Value: 31 -- 23 Read-only 0xE8 See Table 26-16 on page 591 30 -- 22 29 -- 21 28 -- 20 WPVSRC 27 -- 19 26 -- 18 25 -- 17 24 -- 16 15 14 13 12 WPVSRC 11 10 9 8 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 WPVS * WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. * WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the WPSR register. 1 = A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. Note: Reading WPSR automatically clears all fields. 617 32072A-AVR32-03/09 AT32UC3A3 26.8.20 Name: Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 Version Register VERSION Read-only 0xFC 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 VERSION 27 - 19 26 - 18 VARIANT 11 10 VERSION 3 2 1 0 9 8 25 - 17 24 - 16 * VARIANT Reserved. No functionality associated. * VERSION Version of the module. No functionality associated. 618 32072A-AVR32-03/09 AT32UC3A3 26.9 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 26-26. Module Configuration Feature SPI Logic LIN Logic Manchester Logic Modem Logic IRDA Logic Fractional Baudrate ISO7816 DIV USART0 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 USART1 Implemented Implemented Implemented Implemented Implemented Implemented Implemented 8 USART2 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 USART3 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented 8 Table 26-27. Module Clock Name Module name USART0 USART1 USART2 USART3 Clock name CLK_USART0 CLK_USART1 CLK_USART2 CLK_USART3 Table 26-28. Register Reset Values Module name VERSION Reset Value 0x00000420 619 32072A-AVR32-03/09 AT32UC3A3 27. Hi-Speed USB On-The-Go Interface (USBB) Rev: 3.2.0.1 27.1 Features * Compatible with the USB 2.0 specification * Supports High (480Mbps), Full (12Mbps) and Low (1.5Mbps) speed communication and On-TheGo * * * * * * nine pipes/endpoints 2368 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) Flexible Pipe/Endpoint configuration and management with dedicated DMA channels On-Chip UTMI transceiver including Pull-Ups/Pull-downs On-Chip OTG pad including VBUS analog comparator 27.2 Overview The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0 specification, in all speeds. Each pipe/endpoint can be configured in one of several transfer types. It can be associated with one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If several banks are used ("ping-pong" mode), then one DPRAM bank is read or written by the CPU or the DMA while the other is read or written by the USBB core. This feature is mandatory for isochronous pipes/endpoints. Table 27-1 on page 620 describes the hardware configuration of the USB MCU device. Table 27-1. Description of USB Pipes/Endpoints Mnemonic PEP0 PEP1 PEP2 PEP3 PEP4 PEP5 PEP6 PEP7 Max. Size 64 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes Max. Nb. Banks 1 2 2 2 2 2 2 2 DMA N Y Y Y Y Y Y Y Type Control Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Isochronous/Bulk/Interrupt Pipe/Endpoint 0 1 2 3 4 5 6 7 The theoretical maximal pipe/endpoint configuration (458752) exceeds the real DPRAM size (2368). The user needs to be aware of this when configuring pipes/endpoints. To fully use the 620 32072A-AVR32-03/09 AT32UC3A3 2368 of DPRAM, the user could for example use the configuration described inTable 27-2 on page 621. Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM Mnemonic PEP0 PEP1 PEP2 PEP3 Size 64 bytes 512 bytes 512 bytes 256 bytes Nb. Banks 1 2 2 1 Pipe/Endpoint 0 1 2 3 27.3 Block Diagram The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480MHz PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB differential data at 480Mbps. Figure 27-1. USBB Block Diagram HSB Slave Slave Local HSB Slave Interface HSB0 DPRAM HSB Mux Master Master DMA HSB1 PEP Allocation OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS PB User Interface USB 2.0 Core I/O Controller UTMI DMHS DPHS GCLK_USBB 621 32072A-AVR32-03/09 AT32UC3A3 27.4 Application Block Diagram Depending on the USB operating mode (device-only, reduced-host or OTG mode) and the power source (bus-powered or self-powered), there are different typical hardware implementations. 27.4.1 27.4.1.1 Device Mode Bus-Powered device Figure 27-2. Bus-Powered Device Application Block Diagram VDD 3.3 V Regulator OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB Connector VBus ID 39 ohms 39 ohms USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 622 32072A-AVR32-03/09 AT32UC3A3 27.4.1.2 Self-Powered device Figure 27-3. Self-powered Device Application Block Diagram USB Connector VBus ID 39 ohms 39 ohms OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 27.4.2 Host and OTG Modes Figure 27-4. Host and OTG Application Block Diagram VDD 5V DC/DC Generator OTG USB_VBUS USB_ID USB_VBOF DMFS DPFS USB Connector VBus ID 39 ohms 39 ohms USB 2.0 Core I/O Controller DD+ GND UTMI DMHS DPHS 623 32072A-AVR32-03/09 AT32UC3A3 27.5 I/O Lines Description I/O Lines Description Pin Description USB VBus On/Off: Bus Power Control Port VBus: Bus Power Measurement Port FS Data -: Full-Speed Differential Data Line - Port FS Data +: Full-Speed Differential Data Line + Port HS Data -: Hi-Speed Differential Data Line - Port HS Data +: Hi-Speed Differential Data Line + Port USB Identification: Mini Connector Identification Port Type Output Input Input/Output Input/Output Input/Output Input/Output Input Low: Mini-A plug High Z: Mini-B plug Active Level VBUSPO Table 27-3. PIn Name USB_VBOF USB_VBUS DMF DPF DMH DPH USB_ID 624 32072A-AVR32-03/09 AT32UC3A3 27.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 27.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to assign them to their USB peripheral functions. If USB_ID is used, the I/O Controller must be configured to enable the internal pull-up resistor of its pin. If USB_VBOF or USB_ID is not used by the application, the corresponding pin can be used for other purposes by the I/O Controller or by other peripherals. 27.6.2 Clocks The clock for the USBB bus interface (CLK_USBB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USBB before disabling the clock, to avoid freezing the USBB in an undefined state. The UTMI transceiver needs a 12MHz clock as a clock reference for its internal 480MHz PLL. Before using the USB, the user must ensure that this 12 MHz clock is available. The 12 MHz input is connected to a Generic Clock (GCLK_USBB) provided by the Power Manager. 27.6.3 Interrupts The USBB interrupt request line is connected to the interrupt controller. Using the USBB interrupt requires the interrupt controller to be programmed first. 625 32072A-AVR32-03/09 AT32UC3A3 27.7 27.7.1 27.7.1.1 Functional Description USB General Operation Introduction After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device mode or in host mode according to the ID detection. If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by the I/O Controller) and device mode is engaged. The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host mode is then engaged. 27.7.1.2 Power-On and reset Figure 27-5 on page 626 describes the USBB main states. Figure 27-5. General States Macro off: USBE = 0 Clock stopped: FRZCLK = 1 Reset USBE = 0 HW RESET USBE = 1 ID = 1 USBE = 0 USBE = 1 ID = 0 USBE = 0 Device Host After a hardware reset, the USBB is in the Reset state. In this state: * The macro is disabled. The USBB Enable bit in the General Control register (USBCON.USBE) is zero. * The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock bit in USBCON (USBON.FRZCLK) is set. * The UTMI is in suspend mode. * The internal states and registers of the device and host modes are reset. * The DPRAM is not cleared and is accessible. * The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of the USB_ID and USB_VBUS input pins. * The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be written by software, so that the user can program pads and speed before enabling the macro, but their value is only taken into account once the macro is enabled and unfrozen. 626 32072A-AVR32-03/09 AT32UC3A3 After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according to the ID detection) in idle state. The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO, FRZCLK, UIDE, UIMOD and, LS bits are not reset. 27.7.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 27-6 on page 628 shows the structure of the USB interrupt system. 627 32072A-AVR32-03/09 AT32UC3A3 Figure 27-6. Interrupt System USBSTA.IDTI USBCON.IDTE USBSTA.VBUSTI USBCON.VBUSTE UESTAX.TXINI UECONX.TXINE UESTAX.RXOUTI UECONX.RXOUTE UESTAX.RXSTPI UECONX.RXSTPE UESTAX.UNDERFI UECONX.UNDERFE UESTAX.NAKOUTI UECONX.NAKOUTE UESTAX.HBISOINERRI UECONX.HBISOINERRE UESTAX.NAKINI UECONX.NAKINE UESTAX.HBISOFLUSHI UECONX.HBISOFLUSHE UESTAX.OVERFI UECONX.OVERFE UESTAX.STALLEDI UECONX.STALLEDE UESTAX.CRCERRI UECONX.CRCERRE UESTAX.SHORTPACKET UECONX.SHORTPACKETE UESTAX.DTSEQ=MDATA & UESTAX.RXOUTI UECONX.MDATAE UESTAX.DTSEQ=DATAX & UESTAX.RXOUTI UECONX.DATAXE UESTAX.TRANSERR UECONX.TRANSERRE UESTAX.NBUSYBK UECONX.NBUSYBKE UDINT.WAKEUP UDINTE.WAKEUPE UDINT.EORSM UDINTE.EORSME UDINT.UPRSM UDDMAX_STATUS.EOT_STA UDDMAX_CONTROL.EOT_IRQ_EN UDDMAX_STATUS.EOCH_BUFF_STA UDDMAX_CONTROL.EOBUFF_IRQ_EN UDDMAX_STATUS.DESC_LD_STA UDDMAX_CONTROL.DESC_LD_IRQ_EN UPSTAX.RXINI UPCONX.RXINE UPSTAX.TXOUTI UPCONX.TXOUTE UPSTAX.TXSTPI UPCONX.TXSTPE UPSTAX.UNDERFI UPCONX.UNDERFIE UPSTAX.PERRI UPCONX.PERRE UPSTAX.NAKEDI UPCONX.NAKEDE UPSTAX.OVERFI UPCONX.OVERFIE UPSTAX.RXSTALLDI UPCONX.RXSTALLDE UPSTAX.CRCERRI UPCONX.CRCERRE UPSTAX.SHORTPACKETI UPCONX.SHORTPACKETIE UPSTAX.NBUSYBK UPCONX.NBUSYBKE UHDMAX_STATUS.EOT_STA UHDMAX_CONTROL.EOT_IRQ_EN UHDMAX_STATUS.EOCH_BUFF_STA UHDMAX_CONTROL.EOBUFF_IRQ_EN UHDMAX_STATUS.DESC_LD_STA UHDMAX_CONTROL.DESC_LD_IRQ_EN UHINT.DMAXINT USB Host DMA Channel X Interrupt UHINT.HWUPI UHINTE.HWUPIE UHINT.PXINT UHINTE.PXINTE UHINTE.DMAXINTE USB Host Pipe X Interrupt UHINT.RSMEDI UHINTE.RSMEDIE UHINT.RXRSMI UHINTE.RXRSMIE UHINT.HSOFI UHINTE.HSOFIE USB Host Interrupt UHINT.RSTI UHINTE.RSTIE UHINT.DDISCI UHINTE.DDISCIE UHINT.DCONNI UHINTE.DCONNIE USB Device DMA Channel X Interrupt UDINT.DMAXINT UDINTE.DMAXINTE UDINTE.UPRSME UDINT.EPXINT UDINTE.EPXINTE USB Device Interrupt UDINT.EORST UDINTE.EORSTE UDINT.SOF UDINTE.SOFE USB Interrupt UDINT.SUSP UDINTE.SUSPE UDINT.MSOF UDINTE.MSOFE USB Device Endpoint X Interrupt USBSTA.SRPI USBCON.SRPE USBSTA.VBERRI USBCON.VBERRE USBSTA.BCERRI USBCON.BCERRE USBSTA.ROLEEXI USBCON.ROLEEXE USBSTA.HNPERRI USBCON.HNPERRE USBSTA.STOI USBCON.STOE USB General Interrupt Asynchronous interrupt source See Section 27.7.2.19 and Section 27.7.3.13 for further details about device and host interrupts. There are two kinds of general interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). 628 32072A-AVR32-03/09 AT32UC3A3 The processing general interrupts are: * The ID Transition Interrupt (IDTI) * The VBus Transition Interrupt (VBUSTI) * The SRP Interrupt (SRPI) * The Role Exchange Interrupt (ROLEEXI) The exception general interrupts are: * The VBus Error Interrupt (VBERRI) * The B-Connection Error Interrupt (BCERRI) * The HNP Error Interrupt (HNPERRI) * The Suspend Time-Out Interrupt (STOI) 27.7.1.4 MCU Power modes *Run mode In this mode, all MCU clocks can run, including the USB clock. *Idle mode In this mode, the CPU is halted, i.e. the CPU clock is stopped. The Idle mode is entered whatever the state of the USBB. The MCU wakes up on any USB interrupt. *Frozen mode Same as the Idle mode, except that the HSB module is stopped, so the USB DMA, which is an HSB master, can not be used. Moreover, the USB DMA must be stopped before entering this sleep mode in order to avoid erratic behavior. The MCU wakes up on any USB interrupt. *Standby, Stop, DeepStop and Static modes Same as the Frozen mode, except that the USB generic clock and other clocks are stopped, so the USBB is frozen. In the current version of the MCU, no USB interrupt can wake up the MCU in these modes, even the asynchronous interrupt sources. *USB clock frozen In the run, idle and frozen MCU modes, the USBB can be frozen when the USB line is in the suspend mode, by writing a one to the FRZCLK bit, what reduces power consumption. In this case, it is still possible to access the following elements, but only in Run mode: * The OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits in the USBCON register * The DPRAM (through the USB Pipe/Endpoint n FIFO Data (USBFIFOnDATA) registers, but not through USB bus transfers which are frozen) Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger the USB interrupt: * The ID Transition Interrupt (IDTI) * The VBus Transition Interrupt (VBUSTI) 629 32072A-AVR32-03/09 AT32UC3A3 * The Wake-up Interrupt (WAKEUP) * The Host Wake-up Interrupt (HWUPI) *USB Suspend mode In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the transceiver is automatically set in suspend mode to reduce the consumption.The 480MHz internal PLL is stopped. The USBSTA.CLKUSABLE bit is cleared. 27.7.1.5 Speed control *Device mode When the USB interface is in device mode, the speed selection (full-speed or high-speed) is performed automatically by the USBB during the USB reset according to the host speed capability. At the end of the USB reset, the USBB enables or disables high-speed terminations and pull-up. It is possible to restraint the USBB to full-speed or low-speed mode by handling the LS and the Speed Configuration (SPDCONF) bits in UDCON. *Host mode When the USB interface is in host mode, internal pull-down resistors are connected on both D+ and D- and the interface detects the speed of the connected device, which is reflected by the Speed Status (SPEED) field in USBSTA. 27.7.1.6 DPRAM management Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the last pipe/endpoint to be allocated). The user shall therefore configure them in the same order. The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1 pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) do not slide. Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register (UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTOKEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the Pipe Interrupt Request Frequency (INTFRQ) field in the Pipe n Configuration (UPCFGn) register/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction (EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn). To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory windows (from n+2) does not slide. Figure 27-7 on page 631 illustrates the allocation and reorganization of the DPRAM in a typical example. 630 32072A-AVR32-03/09 AT32UC3A3 Figure 27-7. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory Free Memory PEP5 PEP5 PEP5 PEP5 PEP4 Conflict PEP4 PEP3 PEP4 PEP3 (ALLOC stays at 1) PEP2 PEP4 Lost Memory PEP4 PEP3 (larger size) PEP2 PEP2 PEP2 PEP1 PEP1 PEP1 PEP1 PEP0 PEP0 PEP0 PEP0 U(P/E)RST.(E)PENn = 1 U(P/E)CFGn.ALLOC = 1 U(P/E)RST.(E)PEN3 = 0 U(P/E)CFG3.ALLOC = 0 U(P/E)RST.(E)PEN3 = 1 U(P/E)CFG3.ALLOC = 1 Pipes/Endpoints 0..5 Activated Pipe/Endpoint 3 Disabled Pipe/Endpoint 3 Memory Freed Pipe/Endpoint 3 Activated 1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each pipe/endpoint then owns a memory area in the DPRAM. 2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller. 3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 memory window slides down, but the pipe/endpoint 5 does not move. 4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller allocates a memory area after the pipe/endpoint 2 memory area and automatically slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5 overlap. The data of these pipes/endpoints is potentially lost. Note that: * There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as memory allocation and de-allocation may affect only higher pipes/endpoints. * Deactivating then reactivating a same pipe/endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first pipe/endpoint. * When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint and to the maximal FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory allocation conflicts. 27.7.1.7 Pad Suspend Figure 27-8 on page 632 shows the pad behavior. 631 32072A-AVR32-03/09 AT32UC3A3 Figure 27-8. Pad Behavior Idle USBE = 1 & DETACH = 0 & Suspend USBE = 0 | DETACH = 1 | Suspend Active * In the Idle state, the pad is put in low power consumption mode. * In the Active state, the pad is working. Figure 27-9 on page 632 illustrates the pad events leading to a PAD state change. Figure 27-9. Pad Events SUSP Suspend detected Cleared on wake-up WAKEUP Wake-up detected Cleared by software to acknowledge the interrupt PAD State Active Idle Active The SUSP bit is set and the Wake-Up Interrupt (WAKEUP) bit in UDINT is cleared when a USB "Suspend" state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state. The detection of a non-idle event sets WAKEUP, clears SUSP and wakes up the USB pad. Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to one. It returns to the Active state when USBE is written to one and DETACH is written to zero. 632 32072A-AVR32-03/09 AT32UC3A3 27.7.1.8 Customizing of OTG timers It is possible to refine some OTG timers thanks to the Timer Page (TIMPAGE) and Timer Value (TIMVALUE) fields in USBCON, as shown by Table 27-4 on page 633. Customizing of OTG Timers TIMPAGE 0b00 AWaitVrise Time-Out (see OTG Standard(1) Section 6.6.5.1) TIMVALUE 00b 01b 10b 11b 20 ms 50 ms 70 ms 100 ms 0b01 VbBusPulsing Time-Out (see OTG Standard(1) Section5.3.4) 15 ms 23 ms 31 ms 40 ms 0b10 PdTmOutCnt Time-Out (see OTG Standard(1) Section 5.3.2) 93 ms 105 ms 118 ms 131 ms 0b11 SRPDetTmOut Time-Out (see OTG Standard(1) Section 5.3.3) 10 s 100 s 1 ms 11 ms Table 27-4. Note: 1. "On-The-Go Supplement to the USB 2.0 Specification Revision 1.0a". TIMPAGE is used to select the OTG timer to access while TIMVALUE indicates the time-out value of the selected timer. TIMPAGE and TIMVALUE can be read or written. Before writing them, the user shall unlock write accesses by writing a one to the Timer Access Unlock (UNLOCK) bit in USBCON. This is not required for read accesses, except before accessing TIMPAGE if it has to be written in order to read the TIMVALUE field of another OTG timer. 27.7.1.9 Plug-In detection The USB connection is detected from the USB_VBUS pad. Figure 27-10 on page 633 shows the architecture of the plug-in detector. Figure 27-10. Plug-In Detection Input Block Diagram VDD VBus_pulsing RPU Session_valid Logic USB_VBUS RPD Va_Vbus_valid VBUS USBSTA VBUSTI USBSTA VBus_discharge GND Pad Logic The control logic of the USB_VBUS pad outputs two signals: * The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 1.4V. * The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or equal to 4.4V. In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output: 633 32072A-AVR32-03/09 AT32UC3A3 * It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V. * It is cleared when the voltage on the VBUS pad is lower than 1.4V. In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and Va_Vbus_valid: * It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V. * It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V. The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USBSTA.VBUS bit. The USBSTA.VBUS bit is effective whether the USBB is enabled or not. 27.7.1.10 ID detection Figure 27-11 on page 634 shows how the ID transitions are detected. Figure 27-11. ID Detection Input Block Diagram VDD RPU 1 USB_ID 0 ID USBSTA IDTI USBSTA UIMOD USBCON UIDE USBCON I/O Controller The USB mode (device or host) can be either detected from the USB_ID pin or software selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be used as a general purpose I/O pin even when the USB interface is enabled. By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode (UBSTA.ID is one), what corresponds to the case where no Mini-A plug is connected, i.e. no plug or a Mini-B plug is connected and the USB_ID pin is kept high by the internal pull-up resistor from the I/O Controller (which must be enabled if USB_ID is used). The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug (device mode) is connected or disconnected. The USBSTA.ID bit is effective whether the USBB is enabled or not. 634 32072A-AVR32-03/09 AT32UC3A3 27.7.2 27.7.2.1 USB Device Operation Introduction In device mode, the USBB supports full- and low-speed data transfers. In addition to the default control endpoint, eight endpoints are provided, which can be configured with the types isochronous, bulk or interrupt, as described in .Table 27-1 on page 620. The device mode starts in the Idle state, so the pad consumption is reduced to the minimum. 27.7.2.2 Power-On and reset Figure 27-12 on page 635 describes the USBB device mode main states. Figure 27-12. Device Mode States USBE = 0 | ID = 0 USBE = 0 | ID = 0 Reset HW RESET USBE = 1 & ID = 1 Idle After a hardware reset, the USBB device mode is in the Reset state. In this state: * The macro clock is stopped in order to minimize power consumption (FRZCLK is written to one). * The internal registers of the device mode are reset. * The endpoint banks are de-allocated. * Neither D+ nor D- is pulled up (DETACH is written to one). D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written to zero and VBus is present. See "Device mode" for further details. When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode state goes to the Idle state with minimal power consumption. This does not require the USB clock to be activated. The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing a zero to USBE) or when host mode is engaged (ID is zero). 27.7.2.3 USB reset The USB bus reset is managed by hardware. It is initiated by a connected host. When a USB reset is detected on the USB line, the following operations are performed by the controller: * All the endpoints are disabled, except the default control endpoint. 635 32072A-AVR32-03/09 AT32UC3A3 * The default control endpoint is reset (see Section 27.7.2.4 for more details). * The data toggle sequence of the default control endpoint is cleared. * At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set. * During a reset, the USBB automatically switches to the Hi-Speed mode if the host is HiSpeed capable (the reset is called a Hi-Speed reset). The user should observe the USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one). 27.7.2.4 Endpoint reset An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in the UERST register. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This resets: * The internal state machine of this endpoint. * The receive and transmit bank FIFO counters. * All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn) register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data Toggle Sequence (DTSEQ) field of the UESTAn register. Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus reset has been received. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the Reset Data Toggle (RSTD) bit in UECONn). In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to start using the FIFO. 27.7.2.5 Endpoint activation The endpoint is maintained inactive and reset (see Section 27.7.2.4 for more details) as long as it is disabled (EPENn is written to zero). DTSEQ is also reset. The algorithm represented on Figure 27-13 on page 637 must be followed in order to activate an endpoint. 636 32072A-AVR32-03/09 AT32UC3A3 Figure 27-13. Endpoint Activation Algorithm Endpoint Activation Enable the endpoint. Configure the endpoint: - type - direction - size - number of banks Allocate the configured DPRAM banks. Test if the endpoint configuration is correct. EPENn = 1 UECFGn EPTYPE EPDIR EPSIZE EPBK ALLOC CFGOK == 1? Yes Endpoint Activated No ERROR As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not acknowledge the packets sent by the host to this endpoint. The CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the endpoint (see Table 27-1 on page 620) and to the maximal FIFO size (i.e. the DPRAM size). See Section 27.7.1.6 for more details about DPRAM management. 27.7.2.6 Address setup The USB device address is set up according to the USB protocol. * After all kinds of resets, the USB device address is 0. * The host starts a SETUP transaction with a SET_ADDRESS(addr) request. * The user write this address to the USB Address (UADD) field in UDCON, and write a zero to the Address Enable (ADDEN) bit in UDCON, so the actual address is still 0. * The user sends a zero-length IN packet from the control endpoint. * The user enables the recorded USB device address by writing a one to ADDEN. Once the USB device address is configured, the controller filters the packets to only accept those targeting the address stored in UADD. UADD and ADDEN shall not be written all at once. UADD and ADDEN are cleared: * On a hardware reset. * When the USBB is disabled (USBE written to zero). * When a USB reset is detected. When UADD or ADDEN is cleared, the default device address 0 is used. 637 32072A-AVR32-03/09 AT32UC3A3 27.7.2.7 Suspend and wake-up When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP) interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power consumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power consumption. To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to FRZCLK. As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are thus independent of each other except that one bit is cleared when the other is set. 27.7.2.8 Detach The reset value of the DETACH bit is one. It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH. DETACH acts on the pull-up connections of the D+ and D- pads. See "Device mode" for further details. 27.7.2.9 Remote wake-up The Remote Wake-Up request (also known as Upstream Resume) is the only one the device may send on its own initiative, but the device should have beforehand been allowed to by a DEVICE_REMOTE_WAKEUP request from the host. * First, the USBB must have detected a "Suspend" state on the bus, i.e. the Remote Wake-Up request can only be sent after a SUSP interrupt has been set. * The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an upstream resume to the host for a remote wake-up. This will automatically be done by the controller after 5ms of inactivity on the USB bus. * When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared. * RMWKUP is cleared at the end of the upstream resume. * If the controller detects a valid "End of Resume" signal from the host, the End of Resume (EORSM) interrupt is set. 27.7.2.10 STALL request For each endpoint, the STALL management is performed using: * The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request. * The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been sent. To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI, etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is done when a new SETUP packet is received (for control endpoints) or when the STALL Request Clear (STALLRQC) bit is written to one. Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT interrupt is set. 638 32072A-AVR32-03/09 AT32UC3A3 *Special considerations for control endpoints If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are cleared. The SETUP has to be ACKed. This management simplifies the enumeration process management. If a command is not supported or contains an error, the user requests a STALL and can return to the main task, waiting for the next SETUP request. *STALL handshake and retry mechanism The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the STALLRQ bit is set and if there is no retry required. 27.7.2.11 Management of control endpoints *Overview A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set, but not the Received OUT Data Interrupt (RXOUTI) bit. The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these endpoints. When read, their value are always zero. Control endpoints are managed using: * The RXSTPI bit which is set when a new SETUP packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank. * The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared by firmware to acknowledge the packet and to free the bank. * The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to accept a new IN packet and which shall be cleared by firmware to send the packet. *Control write Figure 27-14 on page 640 shows a control write transaction. During the status stage, the controller will not necessarily send a NAK on the first IN token: * If the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status stage and send a zero-length packet after the next IN token. * Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the bytes have been sent by the host and that the transaction is now in the status stage. 639 32072A-AVR32-03/09 AT32UC3A3 Figure 27-14. Control Write SETUP USB Bus RXSTPI RXOUTI TXINI SETUP HW SW DATA OUT OUT IN NAK STATUS IN HW SW HW SW SW *Control read Figure 27-15 on page 640 shows a control read transaction. The USBB has to manage the simultaneous write requests from the CPU and the USB host. Figure 27-15. Control Read SETUP USB Bus RXSTPI RXOUTI TXINI Wr Enable HOST Wr Enable CPU SW HW DATA IN SW STATUS IN OUT NAK OUT SETUP HW HW SW SW A NAK handshake is always generated on the first status stage command. When the controller detects the status stage, all the data written by the CPU are lost and clearing TXINI has no effect. The user checks if the transmission or the reception is complete. The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the following software algorithm: set TXINI wait for RXOUTI OR TXINI if RXOUTI, then clear bit and return if TXINI, then continue Once the OUT status stage has been received, the USBB waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO reset when a SETUP is received. The user has to take care of the fact that the byte counter is reset when a zero-length OUT packet is received. 640 32072A-AVR32-03/09 AT32UC3A3 27.7.2.12 Management of IN endpoints *Overview IN packets are sent by the USB device controller upon IN requests from the host. All the data can be written which acknowledges or not the bank when it is full. The endpoint must be configured first. The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one. TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then writes into the FIFO and write a one to the FIFO Control Clear (FIFOCONC) bit in UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are updated in accordance with the status of the next bank. TXINI shall always be cleared before clearing FIFOCON. The RWALL bit is set when the current bank is not full, i.e. the software can write further data into the FIFO. Figure 27-16. Example of an IN Endpoint with 1 Data Bank NAK IN DATA (bank 0) ACK IN HW TXINI SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 0 SW Figure 27-17. Example of an IN Endpoint with 2 Data Banks IN DATA (bank 0) ACK IN DATA (bank 1) ACK HW TXINI SW SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 1 SW write data to CPU BANK0 641 32072A-AVR32-03/09 AT32UC3A3 *Detailed description The data is written, following the next flow: * When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if TXINE is one. * The user acknowledges the interrupt by clearing TXINI. * The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data (USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case RWALL is cleared and the Byte Count (BYCT) field in UESTAn reaches the endpoint size). * The user allows the controller to send the bank and switches to the next bank (if any) by clearing FIFOCON. If the endpoint uses several banks, the current one can be written while the previous one is being read by the host. Then, when the user clears FIFOCON, the following bank may already be free and TXINI is set immediately. An "Abort" stage can be produced when a zero-length OUT packet is received during an IN stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is used to kill the last written bank. The best way to manage this abort is to apply the algorithm represented on Figure 27-18 on page 642. Figure 27-18. Abort Algorithm Endpoint Abort TXINEC = 1 Disable the TXINI interrupt. NBUSYBK == 0? Yes EPRSTn = 1 No Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent KILLBKS = 1 Kill the last written bank. Yes KILLBK == 1? No Wait for the end of the procedure Abort Done 27.7.2.13 Management of OUT endpoints *Overview OUT packets are sent by the host. All the data can be read which acknowledges or not the bank when it is empty. The endpoint must be configured first. 642 32072A-AVR32-03/09 AT32UC3A3 The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is one. RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear (RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated in accordance with the status of the next bank. RXOUTI shall always be cleared before clearing FIFOCON. The RWALL bit is set when the current bank is not empty, i.e. the software can read further data from the FIFO. Figure 27-19. Example of an OUT Endpoint with one Data Bank OUT DATA (bank 0) ACK NAK OUT DATA (bank 0) ACK HW RXOUTI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 0 Figure 27-20. Example of an OUT Endpoint with two Data Banks OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW RXOUTI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 1 *Detailed description The data is read, following the next flow: * When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if RXOUTE is one. * The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI. 643 32072A-AVR32-03/09 AT32UC3A3 * The user can read the byte count of the current bank from BYCT to know how many bytes to read, rather than polling RWALL. * The user reads the data from the current bank by using the USBFIFOnDATA register, until all the expected data frame is read or the bank is empty (in which case RWALL is cleared and BYCT reaches zero). * The user frees the bank and switches to the next bank (if any) by clearing FIFOCON. If the endpoint uses several banks, the current one can be read while the following one is being written by the host. Then, when the user clears FIFOCON, the following bank may already be ready and RXOUTI is set immediately. In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current packet is acknowledged but there is no room for the next one. For double bank, the USBB responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted the data successfully and has room for another data payload (the second bank is free). 27.7.2.14 Underflow This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt (UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable (UNDERFE) bit is one. An underflow can occur during IN stage if the host attempts to read from an empty bank. A zerolength packet is then automatically sent by the USBB. An underflow can not occur during OUT stage on a CPU action, since the user may read only if the bank is not empty (RXOUTI is one or RWALL is one). An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. An underflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one). 27.7.2.15 Overflow This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one. An overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in. An overflow can not occur during IN stage on a CPU action, since the user may write only if the bank is not full (TXINI is one or RWALL is one). 27.7.2.16 HB IsoIn error This error exists only for high-bandwidth isochronous IN endpoints. At the end of the micro-frame, if at least one packet has been sent to the host, if less banks than expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Bandwidth Isochronous IN Error Interrupt Enable (HBISOINERRORE) bit is one. For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint (NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are 644 32072A-AVR32-03/09 AT32UC3A3 filled by the CPU (three expected) for the current micro-frame. Then, the HBISOINERRI interrupt is generated at the end of the micro-frame. Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in the case of a missing IN token. 27.7.2.17 HB IsoFlush This error exists only for high-bandwidth isochronous IN endpoints. At the end of the micro-frame, if at least one packet has been sent to the host, if there is missing IN token during this micro-frame, the bank(s) destined to this micro-frame is/are flushed out to ensure a good data synchronization between the host and the device. For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token (among 3) is well received by the USBB, then the two last banks will be discarded. 27.7.2.18 CRC error This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI) bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE) bit is one. A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set). 27.7.2.19 Interrupts See the structure of the USB device interrupt system on Figure 27-6 on page 628. There are two kinds of device interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). *Global interrupts The processing device global interrupts are: * The Suspend (SUSP) interrupt * The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero) * The Micro Start of Frame (MSOF) interrupt with no CRC error. * The End of Reset (EORST) interrupt * The Wake-Up (WAKEUP) interrupt * The End of Resume (EORSM) interrupt * The Upstream Resume (UPRSM) interrupt * The Endpoint n (EPnINT) interrupt * The DMA Channel n (DMAnINT) interrupt The exception device global interrupts are: * The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) * The Micro Start of Frame (MSOF) interrupt with a CRC error *Endpoint interrupts The processing device endpoint interrupts are: * The Transmitted IN Data Interrupt (TXINI) 645 32072A-AVR32-03/09 AT32UC3A3 * The Received OUT Data Interrupt (RXOUTI) * The Received SETUP Interrupt (RXSTPI) * The Short Packet (SHORTPACKET) interrupt * The Number of Busy Banks (NBUSYBK) interrupt * The Received OUT isochronous Multiple Data Interrupt (MDATAI) * The Received OUT isochronous DataX Interrupt (DATAXI) The exception device endpoint interrupts are: * The Underflow Interrupt (UNDERFI) * The NAKed OUT Interrupt (NAKOUTI) * The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) * The NAKed IN Interrupt (NAKINI) * The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) * The Overflow Interrupt (OVERFI) * The STALLed Interrupt (STALLEDI) * The CRC Error Interrupt (CRCERRI) * The Transaction error (ERRORTRANS) interrupt *DMA interrupts The processing device DMA interrupts are: * The End of USB Transfer Status (EOTSTA) interrupt * The End of Channel Buffer Status (EOCHBUFFSTA) interrupt * The Descriptor Loaded Status (DESCLDSTA) interrupt There is no exception device DMA interrupt. 646 32072A-AVR32-03/09 AT32UC3A3 27.7.3 27.7.3.1 USB Host Operation Description of pipes For the USBB in host mode, the term "pipe" is used instead of "endpoint" (used in device mode). A host pipe corresponds to a device endpoint, as described by the Figure 27-21 on page 647 from the USB specification. Figure 27-21. USB Communication Flow In host mode, the USBB associates a pipe to a device endpoint, considering the device configuration descriptors. 27.7.3.2 Power-On and reset Figure 27-22 on page 647 describes the USBB host mode main states. Figure 27-22. Host Mode States Macro off Clock stopped Idle Device Disconnection Device Connection Device Disconnection Ready SOFE = 0 SOFE = 1 Suspend After a hardware reset, the USBB host mode is in the Reset state. When the USBB is enabled (USBE is one) in host mode (ID is zero), its host mode state goes to the Idle state. In this state, the controller waits for device connection with minimal power con- 647 32072A-AVR32-03/09 AT32UC3A3 sumption. The USB pad should be in the Idle state. Once a device is connected, the macro enters the Ready state, what does not require the USB clock to be activated. The controller enters the Suspend state when the USB bus is in a "Suspend" state, i.e., when the host mode does not generate the "Start of Frame (SOF)". In this state, the USB consumption is minimal. The host mode exits the Suspend state when starting to generate the SOF over the USB line. 27.7.3.3 Device detection A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the VBUSRQS bit). The device disconnection is detected by the host controller when both D+ and D- are pulled down. 27.7.3.4 USB reset The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt register (UHINT.RSTI) is set when the USB reset has been sent. In this case, all the pipes are disabled and de-allocated. If the bus was previously in a "Suspend" state (the Start of Frame Generation Enable (SOFE) bit in UHCON is zero), the USBB automatically switches it to the "Resume" state, the Host WakeUp Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs or micro SOFs immediately after the USB reset. At the end of the reset, the user should check the USBSTA.SPEED field to know the speed running according to the peripheral capability (LS.FS/HS) 27.7.3.5 Pipe reset A pipe can be reset at any time by writing a one to the Pipe n Reset (PRSTn) bit in the UPRST register. This is recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets: * The internal state machine of this pipe * The receive and transmit bank FIFO counters * All the registers of this pipe (UPCFGn, UPSTAn, UPCONn), except its configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle Sequence field in the Pipe n Status register (UPSTAn.DTSEQ). The pipe configuration remains active and the pipe is still enabled. The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT) (by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register (UPCONnSET.RSTDTS)). In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to start using the FIFO. 648 32072A-AVR32-03/09 AT32UC3A3 27.7.3.6 Pipe activation The pipe is maintained inactive and reset (see Section 27.7.3.5 for more details) as long as it is disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset. The algorithm represented on Figure 27-23 on page 649 must be followed in order to activate a pipe. Figure 27-23. Pipe Activation Algorithm Pipe Activation PENn = 1 Enable the pipe. Configure the pipe: - interrupt request frequency - endpoint number - type - size - number of banks Allocate the configured DPRAM banks. UPCFGn INTFRQ PEPNUM PTYPE PTOKEN PSIZE PBK ALLOC CFGOK == 1? Yes Pipe Activated No Test if the pipe configuration is correct. ERROR As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not send packets to the device through this pipe. The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct compared to their maximal allowed values for the pipe (see Table 27-1 on page 620) and to the maximal FIFO size (i.e. the DPRAM size). See Section 27.7.1.6 for more details about DPRAM management. Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ fields can be written by software. INTFRQ is meaningless for non-interrupt pipes. When starting an enumeration, the user gets the device descriptor by sending a GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the default control pipe with this size parameter. 27.7.3.7 Address setup Once the device has answered the first host requests with the default device address 0, the host assigns a new address to the device. The host controller has to send an USB reset to the device and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the user writes the new address into the USB Host Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All following requests, on all pipes, will be performed using this new address. 649 32072A-AVR32-03/09 AT32UC3A3 When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the following host requests will be performed using the default device address 0. 27.7.3.8 Remote wake-up The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to zero. No more "Start of Frame" is sent on the USB bus and the USB device enters the Suspend state 3ms later. The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature). When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up interrupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no effect. 27.7.3.9 Management of control pipes A control transaction is composed of three stages: * SETUP * Data (IN or OUT) * Status (OUT or IN) The user has to change the pipe token according to each stage. For the control pipe, and only for it, each token is assigned a specific initial data toggle sequence: * SETUP: Data0 * IN: Data1 * OUT: Data1 27.7.3.10 Management of IN pipes IN packets are sent by the USB device controller upon IN requests from the host. All the data can be read which acknowledges or not the bank when it is empty. The pipe must be configured first. When the host requires data from the device, the user has to select beforehand the IN request mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE): * When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before freezing the pipe. * When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe is not frozen by the user. The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE) field in UPCONn is zero). The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Control (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one. 650 32072A-AVR32-03/09 AT32UC3A3 RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then reads from the FIFO and clears the FIFOCON bit (by writing a one to the FIFO Control Clear (FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks, this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance with the status of the next bank. RXINI shall always be cleared before clearing FIFOCON. The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e., the software can read further data from the FIFO. Figure 27-24. Example of an IN Pipe with 1 Data Bank IN DATA (bank 0) ACK IN DATA (bank 0) ACK HW RXINI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 0 Figure 27-25. Example of an IN Pipe with 2 Data Banks IN DATA (bank 0) ACK IN DATA (bank 1) ACK HW RXINI SW HW SW FIFOCON read data from CPU BANK 0 SW read data from CPU BANK 1 27.7.3.11 Management of OUT pipes OUT packets are sent by the host. All the data can be written which acknowledges or not the bank when it is full. The pipe must be configured and unfrozen first. The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFOCON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data Interrupt Enable (TXOUTE) bit in UPCONn is one. 651 32072A-AVR32-03/09 AT32UC3A3 TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the pipe FIFO. The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and FIFOCON bits are updated in accordance with the status of the next bank. TXOUTI shall always be cleared before clearing FIFOCON. The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. Note that if the user decides to switch to the Suspend state (by writing a zero to the UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and the bank is sent. Note that in High-Speed operating mode, the host controller automatically manages the PING protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction (BINTERVALL) field in UPCFGn. See the Section 27.8.3.13 for more details. Figure 27-26. Example of an OUT Pipe with one Data Bank OUT DATA (bank 0) ACK OUT HW TXOUTI SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 0 SW Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW SW SW FIFOCON write data to CPU SW BANK 0 write data to CPU BANK 1 SW write data to CPU BANK0 652 32072A-AVR32-03/09 AT32UC3A3 Figure 27-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW SW SW FIFOCON write data to CPU BANK 0 SW write data to CPU BANK 1 SW write data to CPU BANK0 27.7.3.12 CRC error This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit, what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in UPCONn is one. A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN packet is stored in the bank as if no CRC error had occurred (RXINI is set). 27.7.3.13 Interrupts See the structure of the USB host interrupt system on Figure 27-6 on page 628. There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). *Global interrupts The processing host global interrupts are: * The Device Connection Interrupt (DCONNI) * The Device Disconnection Interrupt (DDISCI) * The USB Reset Sent Interrupt (RSTI) * The Downstream Resume Sent Interrupt (RSMEDI) * The Upstream Resume Received Interrupt (RXRSMI) * The Host Start of Frame Interrupt (HSOFI) * The Host Wake-Up Interrupt (HWUPI) * The Pipe n Interrupt (PnINT) * The DMA Channel n Interrupt (DMAnINT) There is no exception host global interrupt. *Pipe interrupts The processing host pipe interrupts are: * The Received IN Data Interrupt (RXINI) 653 32072A-AVR32-03/09 AT32UC3A3 * The Transmitted OUT Data Interrupt (TXOUTI) * The Transmitted SETUP Interrupt (TXSTPI) * The Short Packet Interrupt (SHORTPACKETI) * The Number of Busy Banks (NBUSYBK) interrupt The exception host pipe interrupts are: * The Underflow Interrupt (UNDERFI) * The Pipe Error Interrupt (PERRI) * The NAKed Interrupt (NAKEDI) * The Overflow Interrupt (OVERFI) * The Received STALLed Interrupt (RXSTALLDI) * The CRC Error Interrupt (CRCERRI) *DMA interrupts The processing host DMA interrupts are: * The End of USB Transfer Status (EOTSTA) interrupt * The End of Channel Buffer Status (EOCHBUFFSTA) interrupt * The Descriptor Loaded Status (DESCLDSTA) interrupt There is no exception host DMA interrupt. 654 32072A-AVR32-03/09 AT32UC3A3 27.7.4 USB DMA Operation USB packets of any length may be transferred when required by the USBB. These transfers always feature sequential addressing. These two characteristics mean that in case of high USBB throughput, both HSB ports will benefit from "incrementing burst of unspecified length" since the average access latency of HSB slaves can then be reduced. The DMA uses word "incrementing burst of unspecified length" of up to 256 beats for both data transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte boundary crossing. Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus bandwidth performance boost with paged memories. This is because these memories row (or bank) changes, which are very clock-cycle consuming, will then likely not occur or occur once instead of dozens of times during a single big USB packet DMA transfer in case other HSB masters address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints. This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size (PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA Channel n Control (UDDMAnCONTROL) register. The USBB average throughput may be up to nearly 1.5 Mbps. Its average access latency decreases as burst length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four compared to native byte access. If at least 0 wait-state word burst capability is also provided by the other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth allocation for full USB bandwidth usage at 33MHz, and less than 0.6% at 66MHz. Figure 27-29. Example of DMA Chained List Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address Next Descriptor Address HSB Address Control HSB Address Control Status Transfer Descriptor Next Descriptor Address HSB Address Control Transfer Descriptor Next Descriptor Address HSB Address Control NULL Memory Area Data Buffer 1 Data Buffer 2 Data Buffer 3 655 32072A-AVR32-03/09 AT32UC3A3 27.8 User Interface USBB Register Memory Map Register Device General Control Register Device Global Interrupt Register Device Global Interrupt Clear Register Device Global Interrupt Set Register Device Global Interrupt Enable Register Device Global Interrupt Enable Clear Register Device Global Interrupt Enable Set Register Endpoint Enable/Reset Register Device Frame Number Register Endpoint 0 Configuration Register Endpoint 1 Configuration Register Endpoint 2 Configuration Register Endpoint 3 Configuration Register Endpoint 4 Configuration Register Endpoint 5 Configuration Register Endpoint 6 Configuration Register Endpoint 7Configuration Register Endpoint 8Configuration Register Endpoint 0 Status Register Endpoint 1 Status Register Endpoint 2 Status Register Endpoint 3 Status Register Endpoint 4 Status Register Endpoint 5 Status Register Endpoint 6 Status Register Endpoint 7Status Register Endpoint 8Status Register Endpoint 0 Status Clear Register Endpoint 1 Status Clear Register Endpoint 2 Status Clear Register Endpoint 3 Status Clear Register Endpoint 4 Status Clear Register Endpoint 5 Status Clear Register Endpoint 6 Status Clear Register Endpoint 7 Status Clear Register Name UDCON UDINT UDINTCLR UDINTSET UDINTE UDINTECLR UDINTESET UERST UDFNUM UECFG0 UECFG1 UECFG2 UECFG3 UECFG4 UECFG5 UECFG6 UECFG7 UECFG8 UESTA0 UESTA1 UESTA2 UESTA3 UESTA4 UESTA5 UESTA6 UESTA7 UESTA8 UESTA0CLR UESTA1CLR UESTA2CLR UESTA3CLR UESTA4CLR UESTA5CLR UESTA6CLR UESTA7CLR Access Read/Write Read-Only Write-Only Write-Only Read-Only Write-Only Write-Only Read/Write Read-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Reset Value 0x00000100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000100 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 27-5. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120 0x0130 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C 0x0150 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178 0x017C 656 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0180 0x0190 0x0194 0x0198 0x019C 0x01A0 0x01A4 0x01A8 0x01AC 0x01B0 0x01C0 0x01C4 0x01C8 0x01CC 0x01D0 0x01D4 0x01D8 0x01DC 0x01E0 0x01F0 0x01F4 0x01F8 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0210 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C USBB Register Memory Map Register Endpoint 8 Status Clear Register Endpoint 0 Status Set Register Endpoint 1 Status Set Register Endpoint 2 Status Set Register Endpoint 3 Status Set Register Endpoint 4 Status Set Register Endpoint 5 Status Set Register Endpoint 6 Status Set Register Endpoint 7 Status Set Register Endpoint 8 Status Set Register Endpoint 0 Control Register Endpoint 1 Control Register Endpoint 2 Control Register Endpoint 3 Control Register Endpoint 4 Control Register Endpoint 5 Control Register Endpoint 6 Control Register Endpoint 7 Control Register Endpoint 8 Control Register Endpoint 0 Control Set Register Endpoint 1 Control Set Register Endpoint 2 Control Set Register Endpoint 3 Control Set Register Endpoint 4 Control Set Register Endpoint 5 Control Set Register Endpoint 6 Control Set Register Endpoint 7 Control Set Register Endpoint 8 Control Set Register Endpoint 0 Control Clear Register Endpoint 1 Control Clear Register Endpoint 2 Control Clear Register Endpoint 3 Control Clear Register Endpoint 4 Control Clear Register Endpoint 5 Control Clear Register Endpoint 6 Control Clear Register Endpoint 7 Control Clear Register Name UESTA8CLR UESTA0SET UESTA1SET UESTA2SET UESTA3SET UESTA4SET UESTA5SET UESTA6SET UESTA7SET UESTA8SET UECON0 UECON1 UECON2 UECON3 UECON4 UECON5 UECON6 UECON7 UECON8 UECON0SET UECON1SET UECON2SET UECON3SET UECON4SET UECON5SET UECON6SET UECON7SET UECON8SET UECON0CLR UECON1CLR UECON2CLR UECON3CLR UECON4CLR UECON5CLR UECON6CLR UECON7CLR Access Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 657 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0240 0x0310 0x0314 0x0318 0x031C 0x0320 0x0324 0x0328 0x032C 0x0330 0x0334 0x0338 0x033C 0x0340 0x0344 0x0348 0x034C 0x0350 0x0354 0x0358 0x035C 0x0360 USBB Register Memory Map Register Endpoint 8 Control Clear Register Device DMA Channel 1 Next Descriptor Address Register Device DMA Channel 1 HSB Address Register Device DMA Channel 1 Control Register Device DMA Channel 1 Status Register Device DMA Channel 2 Next Descriptor Address Register Device DMA Channel 2 HSB Address Register Device DMA Channel 2 Control Register Device DMA Channel 2 Status Register Device DMA Channel 3 Next Descriptor Address Register Device DMA Channel 3 HSB Address Register Device DMA Channel 3 Control Register Device DMA Channel 3 Status Register Device DMA Channel 4 Next Descriptor Address Register Device DMA Channel 4 HSB Address Register Device DMA Channel 4 Control Register Device DMA Channel 4 Status Register Device DMA Channel 5 Next Descriptor Address Register Device DMA Channel 5 HSB Address Register Device DMA Channel 5 Control Register Device DMA Channel 5 Status Register Device DMA Channel 6 Next Descriptor Address Register Name UECON8CLR UDDMA1 NEXTDESC UDDMA1 ADDR UDDMA1 CONTROL UDDMA1 STATUS UDDMA2 NEXTDESC UDDMA2 ADDR UDDMA2 CONTROL UDDMA2 STATUS UDDMA3 NEXTDESC UDDMA3 ADDR UDDMA3 CONTROL UDDMA3 STATUS UDDMA4 NEXTDESC UDDMA4 ADDR UDDMA4 CONTROL UDDMA4 STATUS UDDMA5 NEXTDESC UDDMA5 ADDR UDDMA5 CONTROL UDDMA5 STATUS UDDMA6 NEXTDESC Access Write-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 658 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0364 0x0368 0x036C 0x0370 0x0374 0x0378 0x037C 0x0380 0x0384 0x0388 0x038C 0x0400 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 0x0041C 0x0420 0x0424 0x0428 0x042C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 USBB Register Memory Map Register Device DMA Channel 6 HSB Address Register Device DMA Channel 6 Control Register Device DMA Channel 6 Status Register Device DMA Channel 7 Next Descriptor Address Register Device DMA Channel 7 HSB Address Register Device DMA Channel 7 Control Register Device DMA Channel 7Status Register Device DMA Channel 8 Next Descriptor Address Register Device DMA Channel 8 HSB Address Register Device DMA Channel 8 Control Register Device DMA Channel 8 Status Register Host General Control Register Host Global Interrupt Register Host Global Interrupt Clear Register Host Global Interrupt Set Register Host Global Interrupt Enable Register Host Global Interrupt Enable Clear Register Host Global Interrupt Enable Set Register Pipe Enable/Reset Register Host Frame Number Register Host Address 1 Register Host Address 2 Register Host Address 3 Register Pipe 0 Configuration Register Pipe 1 Configuration Register Pipe 2 Configuration Register Pipe 3 Configuration Register Pipe 4 Configuration Register Pipe 5 Configuration Register Name UDDMA6 ADDR UDDMA6 CONTROL UDDMA6 STATUS UDDMA7 NEXTDESC UDDMA7 ADDR UDDMA7 CONTROL UDDMA7 STATUS UDDMA8 NEXTDESC UDDMA8 ADDR UDDMA8 CONTROL UDDMA8 STATUS UHCON UHINT UHINTCLR UHINTSET UHINTE UHINTECLR UHINTESET UPRST UHFNUM UHADDR1 UHADDR2 UHADDR3 UPCFG0 UPCFG1 UPCFG2 UPCFG3 UPCFG4 UPCFG5 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Write-Only Write-Only Read-Only Write-Only Write-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 659 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0518 0x051C 0x0520 0x0530 0x0534 0x0538 0x053C 0x0540 0x0544 0x0548 0x054C 0x0550 0x0560 0x0564 0x0568 0x056C 0x0570 0x0574 0x0578 0x057C 0x0580 0x0590 0x0594 0x0598 0x059C 0x05A0 0x05A4 0x05A8 0x05AC 0x05B0 0x05C0 0x05C4 0x05C8 0x05CC 0x05D0 0x05D4 USBB Register Memory Map Register Pipe 6 Configuration Register Pipe 7 Configuration Register Pipe 8 Configuration Register Pipe 0 Status Register Pipe 1 Status Register Pipe 2 Status Register Pipe 3 Status Register Pipe 4 Status Register Pipe 5 Status Register Pipe 6 Status Register Pipe 7Status Register Pipe 8 Status Register Pipe 0 Status Clear Register Pipe 1 Status Clear Register Pipe 2 Status Clear Register Pipe 3 Status Clear Register Pipe 4 Status Clear Register Pipe 5 Status Clear Register Pipe 6 Status Clear Register Pipe 7 Status Clear Register Pipe 8 Status Clear Register Pipe 0 Status Set Register Pipe 1 Status Set Register Pipe 2 Status Set Register Pipe 3 Status Set Register Pipe 4 Status Set Register Pipe 5 Status Set Register Pipe 6 Status Set Register Pipe 7 Status Set Register Pipe 8 Status Set Register Pipe 0 Control Register Pipe 1 Control Register Pipe 2 Control Register Pipe 3 Control Register Pipe 4 Control Register Pipe 5 Control Register Name UPCFG6 UPCFG7 UPCFG8 UPSTA0 UPSTA1 UPSTA2 UPSTA3 UPSTA4 UPSTA5 UPSTA6 UPSTA7 UPSTA8 UPSTA0CLR UPSTA1CLR UPSTA2CLR UPSTA3CLR UPSTA4CLR UPSTA5CLR UPSTA6CLR UPSTA7CLR UPSTA8CLR UPSTA0SET UPSTA1SET UPSTA2SET UPSTA3SET UPSTA4SET UPSTA5SET UPSTA6SET UPSTA7SET UPSTA8SET UPCON0 UPCON1 UPCON2 UPCON3 UPCON4 UPCON5 Access Read/Write Read/Write Read/Write Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 660 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x05D8 0x05DC 0x05E0 0x05F0 0x05F4 0x05F8 0x05FC 0x0600 0x0604 0x0608 0x060C 0x0610 0x0620 0x0624 0x0628 0x062C 0x0630 0x0634 0x0638 0x063C 0x0640 0x0650 0x0654 0x0658 0x065C 0x0660 0x0664 0x0668 0x066C 0x0670 0x0680 0x0684 0x0688 0x068C 0x0690 0x0694 USBB Register Memory Map Register Pipe 6 Control Register Pipe 7 Control Register Pipe 8 Control Register Pipe 0 Control Set Register Pipe 1 Control Set Register Pipe 2 Control Set Register Pipe 3 Control Set Register Pipe 4 Control Set Register Pipe 5 Control Set Register Pipe 6 Control Set Register Pipe 7 Control Set Register Pipe 8 Control Set Register Pipe 0 Control Clear Register Pipe 1 Control Clear Register Pipe 2 Control Clear Register Pipe 3 Control Clear Register Pipe 4 Control Clear Register Pipe 5 Control Clear Register Pipe 6 Control Clear Register Pipe 7 Control Clear Register Pipe 8 Control Clear Register Pipe 0 IN Request Register Pipe 1 IN Request Register Pipe 2 IN Request Register Pipe 3 IN Request Register Pipe 4 IN Request Register Pipe 5 IN Request Register Pipe 6 IN Request Register Pipe 7 IN Request Register Pipe 8 IN Request Register Pipe 0 Error Register Pipe 1 Error Register Pipe 2 Error Register Pipe 3 Error Register Pipe 4 Error Register Pipe 5 Error Register Name UPCON6 UPCON7 UPCON8 UPCON0SET UPCON1SET UPCON2SET UPCON3SET UPCON4SET UPCON5SET UPCON6SET UPCON7SET UPCON8SET UPCON0CLR UPCON1CLR UPCON2CLR UPCON3CLR UPCON4CLR UPCON5CLR UPCON6CLR UPCON7CLR UPCON8CLR UPINRQ0 UPINRQ1 UPINRQ2 UPINRQ3 UPINRQ4 UPINRQ5 UPINRQ6 UPINRQ7 UPINRQ8 UPERR0 UPERR1 UPERR2 UPERR3 UPERR4 UPERR5 Access Read-Only Read-Only Read-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Write-Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 661 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0698 0x069C 0x0670 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0x072C 0x0730 0x0734 0x0738 0x073C 0x0740 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C USBB Register Memory Map Register Pipe 6 Error Register Pipe 7 Error Register Pipe 8 Error Register Host DMA Channel 1 Next Descriptor Address Register Host DMA Channel 1 HSB Address Register Host DMA Channel 1 Control Register Host DMA Channel 1 Status Register Host DMA Channel 2 Next Descriptor Address Register Host DMA Channel 2 HSB Address Register Host DMA Channel 2 Control Register Host DMA Channel 2 Status Register Host DMA Channel 3 Next Descriptor Address Register Host DMA Channel 3 HSB Address Register Host DMA Channel 3 Control Register Host DMA Channel 3Status Register Host DMA Channel 4 Next Descriptor Address Register Host DMA Channel 4 HSB Address Register Host DMA Channel 4 Control Register Host DMA Channel 4 Status Register Host DMA Channel 5 Next Descriptor Address Register Host DMA Channel 5 HSB Address Register Host DMA Channel 5 Control Register Host DMA Channel 5 Status Register Name UPERR6 UPERR7 UPERR8 UHDMA1 NEXTDESC UHDMA1 ADDR UHDMA1 CONTROL UHDMA1 STATUS UHDMA2 NEXTDESC UHDMA2 ADDR UHDMA2 CONTROL UHDMA2 STATUS UHDMA3 NEXTDESC UHDMA3 ADDR UHDMA3 CONTROL UHDMA3 STATUS UHDMA4 NEXTDESC UHDMA4 ADDR UHDMA4 CONTROL UHDMA4 STATUS UHDMA5 NEXTDESC UHDMA5 ADDR UHDMA5 CONTROL UHDMA5 STATUS Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 662 32072A-AVR32-03/09 AT32UC3A3 Table 27-5. Offset 0x0760 0x0764 0x0768 0x076C 0x0770 0x0774 0x0778 0x077C 0x0780 0x0784 0x0788 0x078C 0x0800 0x0804 0x0808 0x080C 0x0818 0x081C 0x0820 0x0824 0x0828 0x082C USBB Register Memory Map Register Host DMA Channel 6 Next Descriptor Address Register Host DMA Channel 6 HSB Address Register Host DMA Channel 6 Control Register Host DMA Channel 6 Status Register Host DMA Channel 7 Next Descriptor Address Register Host DMA Channel 7 HSB Address Register Host DMA Channel 7 Control Register Host DMA Channel 7 Status Register Host DMA Channel 8 Next Descriptor Address Register Host DMA Channel 8 HSB Address Register Host DMA Channel 8 Control Register Host DMA Channel 8 Status Register General Control Register General Status Register General Status Clear Register General Status Set Register IP Version Register IP Features Register IP PB Address Size Register IP Name Register 1 IP Name Register 2 USB Finite State Machine Status Register Name UHDMA6 NEXTDESC UHDMA6 ADDR UHDMA6 CONTROL UHDMA6 STATUS UHDMA7 NEXTDESC UHDMA7 ADDR UHDMA7 CONTROL UHDMA7 STATUS UHDMA8 NEXTDESC UHDMA8 ADDR UHDMA8 CONTROL UHDMA8 STATUS USBCON USBSTA USBSTACLR USBSTASET UVERS UFEATURES UADDRSIZE UNAME1 UNAME2 USBFSM Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-Only Write-Only Write-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x03004000 0x00000400 0x00000000 0x00000000 -(1) -(1) -(1) -(1) -(1) 0x00000009 663 32072A-AVR32-03/09 AT32UC3A3 Table 27-6. Offset 0x00000 0x0FFFC 0x10000 0x1FFFC 0x20000 0x2FFFC 0x30000 0x3FFFC 0x40000 0x4FFFC 0x50000 0x5FFFC 0x60000 0x6FFFC 0x70000 0x7FFFC 0x80000 0x8FFFC Note: USB HSB Memory Map Register Pipe/Endpoint 0 FIFO Data Register Pipe/Endpoint 1 FIFO Data Register Pipe/Endpoint 2 FIFO Data Register Pipe/Endpoint 3 FIFO Data Register Pipe/Endpoint 4 FIFO Data Register Pipe/Endpoint 5 FIFO Data Register Pipe/Endpoint 6 FIFO Data Register Pipe/Endpoint 7 FIFO Data Register Pipe/Endpoint 8 FIFO Data Register Name USB FIFO0DATA USB FIFO1DATA USB FIFO2DATA USB FIFO3DATA USB FIFO4DATA USB FIFO5DATA USB FIFO6DATA USB FIFO7DATA USB FIFO8DATA Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 664 32072A-AVR32-03/09 AT32UC3A3 27.8.1 27.8.1.1 Name: USB General Registers General Control Register USBCON Read/Write 0x0800 0x03004000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 UIMOD 24 UIDE 23 - 22 UNLOCK 21 TIMPAGE 20 19 - 18 - 17 TIMVALUE 16 15 USBE 14 FRZCLK 13 VBUSPO 12 OTGPADE 11 HNPREQ 10 SRPREQ 9 SRPSEL 8 VBUSHWC 7 STOE 6 HNPERRE 5 ROLEEXE 4 BCERRE 3 VBERRE 2 SRPE 1 VBUSTE 0 IDTE * UIMOD: USBB Mode This bit has no effect when UIDE is one (USB_ID input pin activated). 0: The module is in USB host mode. 1: The module is in USB device mode. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. UIDE: USB_ID Pin Enable 0: The USB mode (device/host) is selected from the UIMOD bit. 1: The USB mode (device/host) is selected from the USB_ID input pin. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. UNLOCK: Timer Access Unlock 1: The TIMPAGE and TIMVALUE fields are unlocked. 0: The TIMPAGE and TIMVALUE fields are locked. The TIMPAGE and TIMVALUE fields can always be read, whatever the value of UNLOCK. TIMPAGE: Timer Page This field contains the page value to access a special timer register. TIMVALUE: Timer Value This field selects the timer value that is written to the special time register selected by TIMPAGE. See Section 27.7.1.8 for details. USBE: USBB Enable Writing a zero to this bit will reset the USBB, disable the USB transceiver and, disable the USBB clock inputs. Unless explicitly stated, all registers then will become read-only and will be reset. 1: The USBB is enabled. 0: The USBB is disabled. This bit can be written even if FRZCLK is one. FRZCLK: Freeze USB Clock 1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all registers then become read-only. * * * * * * 665 32072A-AVR32-03/09 AT32UC3A3 0: The clock inputs are enabled. This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value. * VBUSPO: VBus Polarity 1: The USB_VBOF output signal is inverted (active low). 0: The USB_VBOF output signal is in its default mode (active high). To be generic. May be useful to control an external VBus power module. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. * OTGPADE: OTG Pad Enable 1: The OTG pad is enabled. 0: The OTG pad is disabled. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. * HNPREQ: HNP Request When the controller is in device mode: Writing a one to this bit will initiate a HNP (Host Negociation Protocol). Writing a zero to this bit has no effect. This bit is cleared when the controller has initiated an HNP. When the controller is in host mode: Writing a one to this bit will accept a HNP. Writing a zero to this bit will reject a HNP. SRPREQ: SRP Request Writing a one to this bit will initiate an SRP when the controller is in device mode. Writing a zero to this bit has no effect. This bit is cleared when the controller has initiated an SRP. SRPSEL: SRP Selection 1: VBus pulsing is selected as SRP method. 0: Data line pulsing is selected as SRP method. VBUSHWC: VBus Hardware Control 1: The hardware control over the USB_VBOF output pin is disabled. 0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS problem occurs. STOE: Suspend Time-Out Interrupt Enable 1: The Suspend Time-Out Interrupt (STOI) is enabled. 0: The Suspend Time-Out Interrupt (STOI) is disabled. HNPERRE: HNP Error Interrupt Enable 1: The HNP Error Interrupt (HNPERRI) is enabled. 0: The HNP Error Interrupt (HNPERRI) is disabled. ROLEEXE: Role Exchange Interrupt Enable 1: The Role Exchange Interrupt (ROLEEXI) is enabled. 0: The Role Exchange Interrupt (ROLEEXI) is disabled. BCERRE: B-Connection Error Interrupt Enable 1: The B-Connection Error Interrupt (BCERRI) is enabled. 0: The B-Connection Error Interrupt (BCERRI) is disabled. VBERRE: VBus Error Interrupt Enable 1: The VBus Error Interrupt (VBERRI) is enabled. 0: The VBus Error Interrupt (VBERRI) is disabled. SRPE: SRP Interrupt Enable 1: The SRP Interrupt (SRPI) is enabled. 0: The SRP Interrupt (SRPI) is disabled. VBUSTE: VBus Transition Interrupt Enable 1: The VBus Transition Interrupt (VBUSTI) is enabled. 0: The VBus Transition Interrupt (VBUSTI) is disabled. IDTE: ID Transition Interrupt Enable 1: The ID Transition interrupt (IDTI) is enabled. 0: The ID Transition interrupt (IDTI) is disabled. * * * * * * * * * * * 666 32072A-AVR32-03/09 AT32UC3A3 27.8.1.2 General Status Register Register Name: USBSTA Access Type: Offset: Reset Value: Read-Only 0x0804 0x00000400 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 CLKUSABLE 13 SPEED 12 11 VBUS 10 ID 9 VBUSRQ 8 - 7 STOI 6 HNPERRI 5 ROLEEXI 4 BCERRI 3 VBERRI 2 SRPI 1 VBUSTI 0 IDTI * CLKUSABLE: UTMI Clock Usable This bit is set when the UTMI 30MHz is usable. This bit is cleared when the UTMI 30MHz is not usable. * SPEED: Speed Status This field is set according to the controller speed mode. This field shall only be used in device mode. SPEED 0 1 0 1 0 0 1 1 Speed Status Full-Speed mode Low-Speed mode High-Speed mode Reserved * VBUS: VBus Level This bit is set when the VBus line level is high, even if USBE is zero. This bit is cleared when the VBus line level is low, even if USBE is zero. This bit can be used in device mode to monitor the USB bus connection state of the application. * ID: USB_ID Pin State This bit is cleared when the USB_ID level is low, even if USBE is zero. This bit is set when the USB_ID level is high, event if USBE is zero. * VBUSRQ: VBus Request This bit is set when the USBSTASET.VBUSRQS bit is written to one. This bit is cleared when the USBSTACLR.VBUSRQC bit is written to one or when a VBus error occurs and VBUSHWC is zero. 1: The USB_VBOF output pin is driven high to enable the VBUS power supply generation. 0: The USB_VBOF output pin is driven low to disable the VBUS power supply generation. This bit shall only be used in host mode. 667 32072A-AVR32-03/09 AT32UC3A3 * STOI: Suspend Time-Out Interrupt This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if STOE is one. This bit is cleared when the UBSTACLR.STOIC bit is written to one. This bit shall only be used in host mode. HNPERRI: HNP Error Interrupt This bit is set when an error has been detected during a HNP negotiation. This triggers a USB interrupt if HNPERRE is one. This bit is cleared when the UBSTACLR.HNPERRIC bit is written to one. This bit shall only be used in device mode. ROLEEXI: Role Exchange Interrupt This bit is set when the USBB has successfully switched its mode because of an HNP negotiation (host to device or device to host). This triggers a USB interrupt if ROLEEXE is one. This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one. BCERRI: B-Connection Error Interrupt This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one. This bit is cleared when the UBSTACLR.BCERRIC bit is written to one. This bit shall only be used in host mode. VBERRI: VBus Error Interrupt This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one. This bit is cleared when the UBSTACLR.VBERRIC bit is written to one. This bit shall only be used in host mode. If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of VBUSHWC is one. SRPI: SRP Interrupt This bit is set when an SRP has been detected. This triggers a USB interrupt if SRPE is one. This bit is cleared when the UBSTACLR.SRPIC bit is written to one. This bit shall only be used in host mode. VBUSTI: VBus Transition Interrupt This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB interrupt if VBUSTE is one. This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one. This interrupt is generated even if the clock is frozen by the FRZCLK bit. IDTI: ID Transition Interrupt This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB interrupt if IDTE is one. This bit is cleared when the UBSTACLR.IDTIC bit is written to one. This interrupt is generated even if the clock is frozen by the FRZCLK bit. * * * * * * * 668 32072A-AVR32-03/09 AT32UC3A3 27.8.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Offset: Read Value: Write-Only 0x0808 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 VBUSRQC 8 - 7 STOIC 6 HNPERRIC 5 ROLEEXIC 4 BCERRIC 3 VBERRIC 2 SRPIC 1 VBUSTIC 0 IDTIC Writing a one to a bit in this register will clear the corresponding bit in UBSTA. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 669 32072A-AVR32-03/09 AT32UC3A3 27.8.1.4 General Status Set Register Register Name: USBSTASET Access Type: Offset: Read Value: Write-Only 0x080C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 VBUSRQS 8 - 7 STOIS 6 HNPERRIS 5 ROLEEXIS 4 BCERRIS 3 VBERRIS 2 SRPIS 1 VBUSTIS 0 IDTIS Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 670 32072A-AVR32-03/09 AT32UC3A3 27.8.1.5 Version Register Register Name: UVERS Access Type: Offset: Read Value: Read-Only 0x0818 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associated. 671 32072A-AVR32-03/09 AT32UC3A3 27.8.1.6 Features Register Register Name: UFEATURES Access Type: Offset: Read Value: Read-Only 0x081C - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 ENHBISO7 22 ENHBISO6 21 ENHBISO5 20 ENHBISO4 19 ENHBISO3 18 ENHBISO2 17 ENHBISO1 16 DATABUS 15 BYTEWRITE DPRAM 14 13 FIFOMAXSIZE 12 11 10 9 8 DMAFIFOWORDDEPTH 7 DMABUFFE RSIZE 6 5 DMACHANNELNBR 4 3 2 EPTNBRMAX 1 0 * ENHBISOn: High Bandwidth Isochronous Feature for Endpoint n 1: The high bandwidth isochronous is supported. 1: The high bandwidth isochronous is not supported. * DATABUS: Data Bus 16-8 1: The UTMI data bus is a 16-bit data path at 30MHz. 0: The UTMI data bus is a 8-bit data path at 60MHz. * BYTEWRITEDPRAM: DPRAM Byte-Write Capability 1: The DPRAM is natively byte-write capable. 0: The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface. * FIFOMAXSIZE: Maximal FIFO Size This field indicates the maximal FIFO size, i.e., the DPRAM size: FIFOMAXSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Maximal FIFO Size < 256 bytes < 512 bytes < 1024 bytes < 2048 bytes < 4096 bytes < 8192 bytes < 16384 bytes >= 16384 bytes 672 32072A-AVR32-03/09 AT32UC3A3 * DMAFIFOWORDDEPTH: DMA FIFO Depth in Words This field indicates the DMA FIFO depth controller in words: DMAFIFOWORDDEPTH 0 0 0 0 0 0 0 0 1 0 1 0 DMA FIFO Depth in Words 16 1 2 ... 1 1 1 1 15 * DMABUFFERSIZE: DMA Buffer Size 1: The DMA buffer size is 24bits. 0: The DMA buffer size is 16bits. * DMACHANNELNBR: Number of DMA Channels This field indicates the number of hardware-implemented DMA channels: DMACHANNELNBR 0 0 0 0 0 1 0 1 0 Number of DMA Channels Reserved 1 2 ... 1 1 1 7 * EPTNBRMAX: Maximal Number of Pipes/Endpoints This field indicates the number of hardware-implemented pipes/endpoints: EPTNBRMAX 0 0 0 0 0 0 0 0 1 0 1 0 Maximal Number of Pipes/Endpoints 16 1 2 ... 1 1 1 1 15 673 32072A-AVR32-03/09 AT32UC3A3 27.8.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Offset: Read Value: Read-Only 0x0820 - 31 30 29 28 27 26 25 24 UADDRSIZE[31:24] 23 22 21 20 19 18 17 16 UADDRSIZE[23:16] 15 14 13 12 11 10 9 8 UADDRSIZE[15:8] 7 6 5 4 3 2 1 0 UADDRSIZE[7:0] * UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBB IP interface. 674 32072A-AVR32-03/09 AT32UC3A3 27.8.1.8 Name Register 1 Register Name: UNAME1 Access Type: Offset: Read Value: Read-Only 0x0824 - 31 30 29 28 27 26 25 24 UNAME1[31:24] 23 22 21 20 19 18 17 16 UNAME1[23:16] 15 14 13 12 11 10 9 8 UNAME1[15:8] 7 6 5 4 UNAME1[7:0] 3 2 1 0 * UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBB IP. 675 32072A-AVR32-03/09 AT32UC3A3 27.8.1.9 Name Register 2 Register Name: UNAME2 Access Type: Offset: Read Value: Read-Only 0x0828 31 30 29 28 27 26 25 24 UNAME2[31:24] 23 22 21 20 19 18 17 16 UNAME2[23:16] 15 14 13 12 11 10 9 8 UNAME2[15:8] 7 6 5 4 UNAME2[7:0] 3 2 1 0 * UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBB IP. 676 32072A-AVR32-03/09 AT32UC3A3 27.8.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Offset: Read Value: Read-Only 0x082C 0x00000009 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 DRDSTATE 1 0 * DRDSTATE This field indicates the state of the USBB. Refer to the OTG specification for more details. DRDSTATE 0 1 2 3 4 5 6 7 8 9 10 11 Description a_idle state: this is the start state for A-devices (when the ID pin is 0) a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the Adevice VBus Valid threshold (4.4 V). a_wait_bcon: In this state, the A-device waits for the B-device to signal a connection. a_host: In this state, the A-device that operates in Host mode is operational. a_suspend: The A-device operating as a host is in the suspend mode. a_peripheral: The A-device operates as a peripheral. a_wait_vfall: In this state, the A-device waits for the voltage on VBus to drop below the Adevice Session Valid threshold (1.4 V). a_vbus_err: In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. a_wait_discharge: In this state, the A-device waits for the data usb line to discharge (100 us). b_idle: this is the start state for B-device (when the ID pin is 1). b_peripheral: In this state, the B-device acts as the peripheral. b_wait_begin_hnp: In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. 677 32072A-AVR32-03/09 AT32UC3A3 DRDSTATE 12 13 14 15 Description b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host. b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. b_host: In this state, the B-device acts as the Host. b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol. 678 32072A-AVR32-03/09 AT32UC3A3 27.8.2 USB Device Registers 27.8.2.1 Device General Control Register Register Name: UDCON Access Type: Offset: Reset Value: Read/Write 0x0000 0x00000100 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 OPMODE2 15 TSTPCKT 14 TSTK 13 TSTJ 12 LS 11 SPDCONF 10 9 RMWKUP 8 DETACH 7 ADDEN 6 5 4 3 UADD 2 1 0 * OPMODE2: Specific Operational mode * * * * 1: The UTMI transceiver is in the disable bit stuffing and NRZI encoding operational mode for test purpose. 0: The UTMI transceiver is in normal operation mode. TSTPCKT: Test packet mode 1: The UTMI transceiver generates test packets for test purpose. 0: The UTMI transceiver is in normal operation mode. TSTK: Test mode K 1: The UTMI transceiver generates high-speed K state for test purpose. 0: The UTMI transceiver is in normal operation mode. TSTJ: Test mode J 1: The UTMI transceiver generates high-speed J state for test purpose. 0: The UTMI transceiver is in normal operation mode. LS: Low-Speed Mode Force 1: The low-speed mode is active. 0: The full-speed mode is active. This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit. 679 32072A-AVR32-03/09 AT32UC3A3 * SPDCONF: Speed Configuration This field contains the peripheral speed. SPDCONF 0 0 1 1 0 1 0 1 Speed Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. reserved, do not use this configuration reserved, do not use this configuration Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability. * RMWKUP: Remote Wake-Up Writing a one to this bit will send an upstream resume to the host for a remote wake-up. Writing a zero to this bit has no effect. This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent. * DETACH: Detach Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-). Writing a zero to this bit will reconnect the device. * ADDEN: Address Enable Writing a one to this bit will activate the UADD field (USB address). Writing a zero to this bit has no effect. This bit is cleared when a USB reset is received. * UADD: USB Address This field contains the device address. This field is cleared when a USB reset is received. 680 32072A-AVR32-03/09 AT32UC3A3 27.8.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Offset: Reset Value: Read-Only 0x0004 0x00000000 31 DMA7INT 30 DMA6INT 29 DMA5INT 28 DMA4INT 27 DMA3INT 26 DMA2INT 25 DMA1INT 24 - 23 - 22 - 21 - 20 EP8INT 19 EP7INT 18 EP6INT 17 EP5INT 16 EP4INT 15 EP3INT 14 EP2INT 13 EP1INT 12 EP0INT 11 - 10 - 9 - 8 - 7 - 6 UPRSM 5 EORSM 4 WAKEUP 3 EORST 2 SOF 1 MSOF 0 SUSP * DMAnINT: DMA Channel n Interrupt * This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one. This bit is cleared when the UDDMAnSTATUS interrupt source is cleared. EPnINT: Endpoint n Interrupt This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is one. This bit is cleared when the interrupt source is serviced. UPRSM: Upstream Resume Interrupt This bit is set when the USBB sends a resume signal called "Upstream Resume". This triggers a USB interrupt if UPRSME is one. This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before). EORSM: End of Resume Interrupt This bit is set when the USBB detects a valid "End of Resume" signal initiated by the host. This triggers a USB interrupt if EORSME is one. This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt. WAKEUP: Wake-Up Interrupt This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is one. This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before). This bit is cleared when the Suspend (SUSP) interrupt bit is set. This interrupt is generated even if the clock is frozen by the FRZCLK bit. EORST: End of Reset Interrupt This bit is set when a USB "End of Reset" has been detected. This triggers a USB interrupt if EORSTE is one. This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt. SOF: Start of Frame Interrupt This bit is set when a USB "Start of Frame" PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared. This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt. * * * * * 681 32072A-AVR32-03/09 AT32UC3A3 * MSOF: Micro Start of Frame Interrupt This bit is set in High-speed mode when a USB "Micro Start of Frame" PID (SOF) has been detected (every 125 us). This triggers a USB interrupt if MSOFE is one. The MFNUM field is updated. The FNUM field is unchanged. This bit is cleared when the UDINTCLR.MSOFC bit is written to one to acknowledge the interrupt. * SUSP: Suspend Interrupt This bit is set when a USB "Suspend" idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one. This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt. This bit is cleared when the Wake-Up (WAKEUP) interrupt bit is set. 682 32072A-AVR32-03/09 AT32UC3A3 27.8.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Offset: Read Value: Write-Only 0x0008 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 UPRSMC 5 EORSMC 4 WAKEUPC 3 EORSTC 2 SOFC 1 MSOFC 0 SUSPC Writing a one to a bit in this register will clear the corresponding bit in UDINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 683 32072A-AVR32-03/09 AT32UC3A3 27.8.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Offset: Read Value: Write-Only 0x000C 0x00000000 31 DMA7INTS 30 DMA6INTS 29 DMA5INTS 28 DMA4INTS 27 DMA3INTS 26 DMA2INTS 25 DMA1INTS 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 UPRSMS 5 EORSMS 4 WAKEUPS 3 EORSTS 2 SOFS 1 MSOFS 0 SUSPS Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 684 32072A-AVR32-03/09 AT32UC3A3 27.8.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Offset: Reset Value: Read-Only 0x0010 0x00000000 31 DMA7INTE 30 DMA6INTE 29 DMA5INTE 28 DMA4INTE 27 DMA3INTE 26 DMA2INTE 25 DMA1INTE 24 - 23 - 22 - 21 - 20 EP8INTE 19 EP7INTE 18 EP6INTE 17 EP5INTE 16 EP4INTE 15 EP3INTE 14 EP2INTE 13 EP1INTE 12 EP0INTE 11 - 10 - 9 - 8 - 7 - 6 UPRSME 5 EORSME 4 WAKEUPE 3 EORSTE 2 SOFE 1 MSOFE 0 SUSPE 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled. A bit in this register is set when the corresponding bit in UDINTESET is written to one. A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one. 685 32072A-AVR32-03/09 AT32UC3A3 27.8.2.6 Device Global Interrupt Enable Clear Register Register Name: UDINTECLR Access Type: Offset: Read Value: Write-Only 0x0014 0x00000000 31 DMA7INTEC 30 DMA6INTEC 29 DMA5INTEC 28 DMA4INTEC 27 DMA3INTEC 26 DMA2INTEC 25 DMA1INTEC 24 - 23 - 22 - 21 - 20 EP8INTEC 19 EP7INTEC 18 EP6INTEC 17 EP5INTEC 16 EP4INTEC 15 EP3INTEC 14 EP2INTEC 13 EP1INTEC 12 EP0INTEC 11 - 10 - 9 - 8 - 7 - 6 UPRSMEC 5 EORSMEC 4 WAKEUPEC 3 EORSTEC 2 SOFEC 1 MSOFEC 0 SUSPEC Writing a one to a bit in this register will clear the corresponding bit in UDINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 686 32072A-AVR32-03/09 AT32UC3A3 27.8.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Offset: Read Value: Write-Only 0x0018 0x00000000 31 DMA7INTES 30 DMA6INTES 29 DMA5INTES 28 DMA4INTES 27 DMA3INTES 26 DMA2INTES 25 DMA1INTES 24 - 23 - 22 - 21 - 20 EP8INTES 19 EP7INTES 18 EP6INTES 17 EP5INTES 16 EP4INTES 15 EP3INTES 14 EP2INTES 13 EP1INTES 12 EP0INTES 11 - 10 - 9 - 8 - 7 - 6 UPRSMES 5 EORSMES 4 WAKEUPES 3 EORSTES 2 SOFES 1 MSOFES 0 SUSPES Writing a one to a bit in this register will set the corresponding bit in UDINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 687 32072A-AVR32-03/09 AT32UC3A3 27.8.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Offset: Reset Value: Read/Write 0x001C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 EPRST8 23 EPRST7 22 EPRST6 21 EPRST5 20 EPRST4 19 EPRST3 18 EPRST2 17 EPRST1 16 EPRST0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 EPEN8 7 EPEN7 6 EPEN6 5 EPEN5 4 EPEN4 3 EPEN3 2 EPEN2 1 EPEN1 0 EPEN0 * EPRSTn: Endpoint n Reset Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE). All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field (DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit). The endpoint configuration remains active and the endpoint is still enabled. Writing a zero to this bit will complete the reset operation and start using the FIFO. This bit is cleared upon receiving a USB reset. * EPENn: Endpoint n Enable 1: The endpoint n is enabled. 0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE). 688 32072A-AVR32-03/09 AT32UC3A3 27.8.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Offset: Reset Value: Read-Only 0x0020 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 FNCERR 14 - 13 12 11 FNUM[10:5] 10 9 8 7 6 5 FNUM[4:0] 4 3 2 1 MFNUM 0 * FNCERR: Frame Number CRC Error This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time. This bit is cleared upon receiving a USB reset. * FNUM: Frame Number This field contains the 11-bit frame number information. It is provided in the last received SOF packet. This field is cleared upon receiving a USB reset. FNUM is updated even if a corrupted SOF is received. * MFNUM: Micro Frame Number This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet. This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset. MFNUM is updated even if a corrupted MSOF is received. 689 32072A-AVR32-03/09 AT32UC3A3 27.8.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0100 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 NBTRANS 13 12 EPTYPE 11 10 - 9 AUTOSW 8 EPDIR 7 - 6 5 EPSIZE 4 3 EPBK 2 1 ALLOC 0 - * NBTRANS: Number of transaction per microframe for isochronous endpoint This field shall be written to the number of transaction per microframe to perform high-bandwidth isochronous transfer This field can be written only for endpoint that have this capability (see UFEATURES register, ENHBISOn bit). This field is 0 otherwise. This field is irrelevant for non-isochronous endpoint. NBTRANS 0 0 1 1 0 1 0 1 Number of transaction reserved to endpoint that does not have the high-bandwidth isochronous capability. default value: one transaction per micro-frame. 2 transactions per micro-frame. This endpoint should be configured as double-bank. 3 transactions per micro-frame. This endpoint should be configured as triple-bank. * EPTYPE: Endpoint Type This field shall be written to select the endpoint type: EPTYPE 0 0 1 1 0 1 0 1 Endpoint Type Control Isochronous Bulk Interrupt This field is cleared upon receiving a USB reset. 690 32072A-AVR32-03/09 AT32UC3A3 * AUTOSW: Automatic Switch This bit is cleared upon receiving a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. * EPDIR: Endpoint Direction This bit is cleared upon receiving a USB reset. 1: The endpoint direction is IN (nor for control endpoints). 0: The endpoint direction is OUT. * EPSIZE: Endpoint Size This field shall be written to select the size of each endpoint bank: EPSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Endpoint Size 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0). * EPBK: Endpoint Banks This field shall be written to select the number of banks for the endpoint: EPBK 0 0 1 1 0 1 0 1 Endpoint Banks 1 (single-bank endpoint) 2 (double-bank endpoint) 3 (triple-bank endpoint) Reserved For control endpoints, a single-bank endpoint (0b00) shall be selected. This field is cleared upon receiving a USB reset (except for the endpoint 0). * ALLOC: Endpoint Memory Allocate Writing a one to this bit will allocate the endpoint memory. The user should check the CFGOK bit to know whether the allocation of this endpoint is correct. Writing a zero to this bit will free the endpoint memory. This bit is cleared upon receiving a USB reset (except for the endpoint 0). 691 32072A-AVR32-03/09 AT32UC3A3 27.8.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x0100 0x0130 + (n * 0x04) 0x00000100 31 - 30 29 28 27 BYCT 26 25 24 23 22 BYCT 21 20 19 - 18 CFGOK 17 CTRLDIR 16 RWALL 15 CURRBK 14 13 NBUSYBK 12 11 - 10 ERRORTRANS 9 DTSEQ 8 7 SHORT PACKET 6 STALLEDI/ CRCERRI 5 OVERFI 4 NAKINI/ HBISOFLUSHI 3 NAKOUTI/ HBISOINERRI 2 RXSTPI/ UNDERFI 1 RXOUTI 0 TXINI * BYCT: Byte Count This field is set with the byte count of the FIFO. For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host. For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software from the endpoint. This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. * CFGOK: Configuration OK Status This bit is updated when the ALLOC bit is written to one. This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size). If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register. * CTRLDIR: Control Direction This bit is set after a SETUP packet to indicate that the following packet is an IN packet. This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet. Writing a zero or a one to this bit has no effect. * RWALL: Read/Write Allowed This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO. This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO. This bit is never set if STALLRQ is one or in case of error. This bit is cleared otherwise. This bit shall not be used for control endpoints. 692 32072A-AVR32-03/09 AT32UC3A3 * CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: CURRBK 0 0 1 1 0 1 0 1 Current Bank Bank0 Bank1 Bank2 Reserved This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. * NBUSYBK: Number of Busy Banks This field is set to indicate the number of busy banks: NBUSYBK 0 0 1 1 0 1 0 1 Number of Busy Banks 0 (all banks free) 1 2 3 For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers an EPnINT interrupt if NBUSYBKE is one. For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers an EPnINT interrupt if NBUSYBKE is one. When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank. An EPnINT interrupt is triggered if: - for IN endpoint, NBUSYBKE is one and all the banks are free. - for OUT endpoint, NBUSYBKE is one and all the banks are busy. * ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one. This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the next n-transactions (next micro-frame). * DTSEQ: Data Toggle Sequence This field is set to indicate the PID of the current bank: DTSEQ 0 0 1 1 0 1 0 1 Data Toggle Sequence Data0 Data1 Data2 (for high-bandwidth isochronous endpoint) MData (for high-bandwidth isochronous endpoint) For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the current bank. For OUT transfers, this value indicates the last data toggle sequence received on the current bank. By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0. For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if: - MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one). 693 32072A-AVR32-03/09 AT32UC3A3 - DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one) * SHORTPACKET: Short Packet Interrupt This bit is set for non-control OUT endpoints, when a short packet has been received. This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and the Automatic Switch (AUTOSW) bit are written to one. This triggers an EPnINT interrupt if SHORTPACKETE is one. This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt. STALLEDI: STALLed Interrupt This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one. This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt. CRCERRI: CRC Error Interrupt This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one. This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt. OVERFI: Overflow Interrupt This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one. For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in. This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt. NAKINI: NAKed IN Interrupt This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT interrupt if NAKINE is one. This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt. HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT interrupt if HBISOFLUSHE is one. This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt. NAKOUTI: NAKed OUT Interrupt This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT interrupt if NAKOUTE is one. This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt. HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINERRE is one. This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt. UNDERFI: Underflow Interrupt This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if UNDERFE is one. An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBB. An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt. This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints. * * * * * * * * 694 32072A-AVR32-03/09 AT32UC3A3 * RXSTPI: Received SETUP Interrupt This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT interrupt if RXSTPE is one. Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank. This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints. * RXOUTI: Received OUT Data Interrupt This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the bank. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the next bank. RXOUTI shall always be cleared before clearing FIFOCON. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints. * TXINI: Transmitted IN Data Interrupt This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt if TXINE is one. This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet. This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free. This triggers an EPnINT interrupt if TXINE is one. This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance with the status of the next bank. TXINI shall always be cleared before clearing FIFOCON. This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints. 695 32072A-AVR32-03/09 AT32UC3A3 27.8.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0160 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SHORT PACKETC 6 STALLEDIC/ CRCERRIC 5 OVERFIC 4 NAKINIC/ HBISOFLUSHIC 3 NAKOUTIC/ HBISOINERRIC 2 RXSTPIC/ UNDERFIC 1 RXOUTIC 0 TXINIC Writing a one to a bit in this register will clear the corresponding bit in UESTA. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 696 32072A-AVR32-03/09 AT32UC3A3 27.8.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0190 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 NBUSYBKS 11 - 10 - 9 8 - 7 SHORT PACKETS 6 STALLEDIS/ CRCERRIS 5 OVERFIS 4 NAKINIS/ HBISOFLUSHIS 3 NAKOUTIS/ HBISOINERRIS 2 RXSTPIS/ UNDERFIS 1 RXOUTIS 0 TXINIS Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 697 32072A-AVR32-03/09 AT32UC3A3 27.8.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x01C0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQ 18 RSTDT 17 NYETDIS 16 EPDISHDMA 15 - 14 FIFOCON 13 KILLBK 12 NBUSYBKE 11 - 10 ERRORTRANSE 9 DATAXE 8 MDATAE 7 SHORT PACKETE 6 STALLEDE/ CRCERRE 5 OVERFE 4 NAKINE/ HBISOFLUSHE 3 NAKOUTE/ HBISOINERRE 2 RXSTPE/ UNDERFE 1 RXOUTE 0 TXINE * STALLRQ: STALL Request * This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host. This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero. RSTDT: Reset Data Toggle This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet. This bit is cleared instantaneously. The user does not have to wait for this bit to be cleared. NYETDIS: NYET token disable This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in highspeed mode. This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following the usb 2.0 standard. EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE). The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a one to the EPDISHDMAC bit) in order to complete the DMA transfer. In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer will not start (not requested). If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may occur at any time and may immediately pause the current DMA transfer. This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a DMA transfer by software after reception of a short packet, etc. FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0. For IN endpoints: * * * 698 32072A-AVR32-03/09 AT32UC3A3 This bit is set when the current bank is free, at the same time as TXINI. This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank. For OUT endpoints: This bit is set when the current bank is full, at the same time as RXOUTI. This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank. KILLBK: Kill IN Bank This bit is set when the KILLBKS bit is written to one. This will kill the last written bank. This bit is cleared when the bank is killed. Caution: The bank is really cleared when the "kill packet" procedure is accepted by the USBB core. This bit is automatically cleared after the end of the procedure: The bank is really killed: NBUSYBK is decremented. The bank is not cleared but sent (IN transfer): NBUSYBK is decremented. The bank is not cleared because it was empty. The user shall wait for this bit to be cleared before trying to kill another packet. This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed. NBUSYBKE: Number of Busy Banks Interrupt Enable This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK). This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt (NBUSYBK). ERRORTRANSE: Transaction Error Interrupt Enable This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS). This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt (ERRORTRANS). DATAXE: DataX Interrupt Enable This bit is set when the DATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits) This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt. MDATAE: MData Interrupt Enable This bit is set when the MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits) This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt. SHORTPACKETE: Short Packet Interrupt Enable This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET). This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt (SHORTPACKET). STALLEDE: STALLed Interrupt Enable This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI). This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI). CRCERRE: CRC Error Interrupt Enable This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI). This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI). OVERFE: Overflow Interrupt Enable This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI). This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI). NAKINE: NAKed IN Interrupt Enable This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI). This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI). HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt Enable This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt. This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt. NAKOUTE: NAKed OUT Interrupt Enable This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI). This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI). HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt. This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt. * * * * * * * * * * * * * 699 32072A-AVR32-03/09 AT32UC3A3 * RXSTPE: Received SETUP Interrupt Enable This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI). This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI). * UNDERFE: Underflow Interrupt Enable This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI). This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI). * RXOUTE: Received OUT Data Interrupt Enable This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT). This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT). * TXINE: Transmitted IN Data Interrupt Enable This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI). This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI). 700 32072A-AVR32-03/09 AT32UC3A3 27.8.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0220 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQC 18 - 17 NYETDISC 16 EPDISHDMAC 15 - 14 FIFOCONC 13 - 12 NBUSYBKEC 11 - 10 ERRORTRANSEC 9 DATAXEC 8 MDATEC 7 SHORT PACKETEC 6 STALLEDEC /CRCERREC 5 OVERFEC 4 NAKINEC/ HBISOFLUSHEC 3 NAKOUTEC/ HBISOINERREC 2 RXSTPEC/ UNDERFEC 1 RXOUTEC 0 TXINEC Writing a one to a bit in this register will clear the corresponding bit in UECONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 701 32072A-AVR32-03/09 AT32UC3A3 27.8.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x01F0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 STALLRQS 18 RSTDTS 17 NYETDISS 16 EPDISHDMAS 15 - 14 - 13 KILLBKS 12 NBUSYBKES 11 - 10 ERRORTRANSES 9 DATAXES 8 MDATES 7 SHORT PACKETES 6 STALLEDES /CRCERRES 5 OVERFES 4 NAKINES/ HBISOFLUSHES 3 NAKOUTES/ HBISOINERRES 2 RXSTPES/ UNDERFES 1 RXOUTES 0 TXINES Writing a one to a bit in this register will set the corresponding bit in UECONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 702 32072A-AVR32-03/09 AT32UC3A3 27.8.2.17 Device DMA Channel n Next Descriptor Address Register Register Name: UDDMAnNEXTDESC, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0310 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 NXTDESCADDR[31:24] 23 22 21 20 19 18 17 16 NXTDESCADDR[23:16] 15 14 13 12 11 10 9 8 NXTDESCADDR[15:8] 7 6 5 4 3 - 2 - 1 - 0 - NXTDESCADDR[7:4] * NXTDESCADDR: Next Descriptor Address This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed. This field is written either or by descriptor loading. 703 32072A-AVR32-03/09 AT32UC3A3 27.8.2.18 Device DMA Channel n HSB Address Register Register Name: UDDMAnADDR, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0314 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 HSBADDR[31:24] 23 22 21 20 19 18 17 16 HSBADDR[23:16] 15 14 13 12 11 10 9 8 HSBADDR[15:8] 7 6 5 4 3 2 1 0 HSBADDR[7:0] * HSBADDR: HSB Address This field determines the HSB bus current address of a channel transfer. The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e., HSBADDR[1:0] is considered as 0b00 since only word accesses are performed. Channel HSB start and end addresses may be aligned on any byte boundary. The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared. This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access byte-width. The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set. 704 32072A-AVR32-03/09 AT32UC3A3 27.8.2.19 Device DMA Channel n Control Register Register Name: UDDMAnCONTROL, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0318 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTELENGTH[15:8] 23 22 21 20 19 18 17 16 CHBYTELENGTH[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 BURSTLOCKEN 6 DESCLDIRQEN 5 EOBUFFIRQEN 4 EOTIRQEN 3 DMAENDEN 2 BUFFCLOSE INEN 1 LDNXTCH DESCEN 0 CHEN * CHBYTELENGTH: Channel Byte Length This field determines the total number of bytes to be transferred for this buffer. The maximum channel transfer size 64kB is reached when this field is zero (default value). If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero. This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is ignored. BURSTLOCKEN: Burst Lock Enable 1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration. 0: The DMA never locks the HSB access. DESCLDIRQEN: Descriptor Loaded Interrupt Enable 1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system bus. 0: The Descriptor Loaded interrupt is disabled. EOBUFFIRQEN: End of Buffer Interrupt Enable 1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero. 0: The end of buffer interrupt is disabled. EOTIRQEN: End of USB Transfer Interrupt Enable 1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set. 0: The end of usb OUT data transfer interrupt is disabled. DMAENDEN: End of DMA Buffer Output Enable Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer. For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the USB line to properly closed the usb transfer at the end of the dma transfer. For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer. * * * * * 705 32072A-AVR32-03/09 AT32UC3A3 * BUFFCLOSEINEN: Buffer Close Input Enable For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB OUT data transfer (received short packet). For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero. For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA transfer is closed when the received PID packet is not MDATA. Writing a zero to this bit to disable this feature. * LDNXTCHDESCEN: Load Next Channel Descriptor Enable 1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit is reset. 0: no channel register is loaded after the end of the channel transfer. If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN endpoint, or endpoint is full for OUT endpoint). LDNXTCHDES CEN 0 0 1 1 CHEN 0 1 0 1 Current Bank stop now Run and stop at end of buffer Load next descriptor now Run and link at end of buffer * CHEN: Channel Enable Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both UDDMAnSTATUS.CHEN and CHACTIVE bits are zero. Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer. This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed. If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the UDDMAnSTATUS.CHEN bit is cleared. If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 706 32072A-AVR32-03/09 AT32UC3A3 27.8.2.20 Device DMA Channel n Status Register Register Name: UDDMAnSTATUS, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x031C + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTECNT[15:8] 23 22 21 20 19 18 17 16 CHBYTECNT[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 DESCLD STA 5 EOCHBUFF STA 4 EOTSTA 3 - 2 - 1 CHACTIVE 0 CHEN * CHBYTECNT: Channel Byte Count This field contains the current number of bytes still to be transferred for this buffer. This field is decremented at each dma access. This field is reliable (stable) only if the CHEN bit is zero. DESCLDSTA: Descriptor Loaded Status This bit is set when a Descriptor has been loaded from the HSB bus. This bit is cleared when read by the user. EOCHBUFFSTA: End of Channel Buffer Status This bit is set when the Channel Byte Count counts down to zero. This bit is automatically cleared when read by software. EOTSTA: End of USB Transfer Status This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if UDDMAnCONTROL.BUFFCLOSEINEN is one. This bit is automatically cleared when read by software. CHACTIVE: Channel Active 0: the DMA channel is no longer trying to source the packet data. 1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any) and potentially until USB packet transfer completion, if allowed by the new descriptor. When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running (the endpoint is free for IN transaction, the endpoint is full for OUT transaction). CHEN: Channel Enabled This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded. This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end. 0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN bit is zero. 1: the DMA channel is currently enabled and transfers data upon request. If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared. * * * * * 707 32072A-AVR32-03/09 AT32UC3A3 27.8.3 USB Host Registers 27.8.3.1 Host General Control Register Register Name: UHCON Access Type: Offset: Reset Value: Read/Write 0x0400 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 SPDCONF 12 11 - 10 RESUME 9 RESET 8 SOFE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - * SPDCONF: Speed Configuration This field contains the host speed capability. SPDCONF 0 0 1 1 0 1 0 1 Speed Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. reserved, do not use this configuration reserved, do not use this configuration Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability. * RESUME: Send USB Resume Writing a one to this bit will generate a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. Writing a zero to this bit has no effect. This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one). * RESET: Send USB Reset Writing a one to this bit will generate a USB Reset on the USB bus. This bit is cleared when the USB Reset has been sent. It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset is being sent. * SOFE: Start of Frame Generation Enable Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode. Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state. This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.TXRSMI). 708 32072A-AVR32-03/09 AT32UC3A3 27.8.3.2 Host Global Interrupt Register Register Name: UHINT Access Type: Offset: Reset Value: Read-Only 0x0404 0x00000000 31 DMA7INT 30 DMA6INT 29 DMA5INT 28 DMA4INT 27 DMA3INT 26 DMA2INT 25 DMA1INT 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 P8INT 15 P7INT 14 P6INT 13 P5INT 12 P4INT 11 P3INT 10 P2INT 9 P1INT 8 P0INT 7 - 6 HWUPI 5 HSOFI 4 RXRSMI 3 RSMEDI 2 RSTI 1 DDISCI 0 DCONNI * DMAnINT: DMA Channel n Interrupt This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding DMAnINTE is one (UHINTE register). This bit is cleared when the UHDMAnSTATUS interrupt source is cleared. PnINT: Pipe n Interrupt This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe interrupt enable bit is one (UHINTE register). This bit is cleared when the interrupt source is served. HWUPI: Host Wake-Up Interrupt This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is detected. This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected. This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated), and an OTG SRP event initiated by the peripheral is detected (USBSTA.SRPI is one). This interrupt is generated even if the clock is frozen by the FRZCLK bit. HSOFI: Host Start of Frame Interrupt This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the host controller in low speed mode, this bit is also set when a keep-alive is sent. This bit is cleared when the HSOFIC bit is written to one. RXRSMI: Upstream Resume Received Interrupt This bit is set when an Upstream Resume has been received from the Device. This bit is cleared when the RXRSMIC is written to one. RSMEDI: Downstream Resume Sent Interrupt This bit set when a Downstream Resume has been sent to the Device. This bit is cleared when the RSMEDIC bit is written to one. RSTI: USB Reset Sent Interrupt This bit is set when a USB Reset has been sent to the device. This bit is cleared when the RSTIC bit is written to one. DDISCI: Device Disconnection Interrupt This bit is set when the device has been removed from the USB bus. This bit is cleared when the DDISCIC bit is written to one. * * * * * * * 709 32072A-AVR32-03/09 AT32UC3A3 * DCONNI: Device Connection Interrupt This bit is set when a new device has been connected to the USB bus. This bit is cleared when the DCONNIC bit is written to one. 710 32072A-AVR32-03/09 AT32UC3A3 27.8.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Offset: Read Value: Write-Only 0x0408 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 HWUPIC 5 HSOFIC 4 RXRSMIC 3 RSMEDIC 2 RSTIC 1 DDISCIC 0 DCONNIC Writing a one to a bit in this register will clear the corresponding bit in UHINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 711 32072A-AVR32-03/09 AT32UC3A3 27.8.3.4 Host Global Interrupt Set Register Register Name: UHINTSET Access Type: Offset: Read Value: Write-Only 0x040C 0x00000000 31 DMA7INTS 30 DMA6INTS 29 DMA5INTS 28 DMA4INTS 27 DMA3INTS 26 DMA2INTS 25 DMA1INTS 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 HWUPIS 5 HSOFIS 4 RXRSMIS 3 RSMEDIS 2 RSTIS 1 DDISCIS 0 DCONNIS Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 712 32072A-AVR32-03/09 AT32UC3A3 27.8.3.5 Host Global Interrupt Enable Register Register Name: UHINTE Access Type: Offset: Reset Value: Read-Only 0x0410 0x00000000 31 DMA7INTE 30 DMA6INTE 29 DMA5INTE 28 DMA4INTE 27 DMA3INTE 26 DMA2INTE 25 DMA1INTE 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 P8INTE 15 P7INTE 14 P6INTE 13 P5INTE 12 P4INTE 11 P3INTE 10 P2INTE 9 P1INTE 8 P0INTE 7 - 6 HWUPIE 5 HSOFIE 4 RXRSMIE 3 RSMEDIE 2 RSTIE 1 DDISCIE 0 DCONNIE * DMAnINTE: DMA Channel n Interrupt Enable * * * * * * * * This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT). This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT). PnINTE: Pipe n Interrupt Enable This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT). This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT). HWUPIE: Host Wake-Up Interrupt Enable This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI). This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI). HSOFIE: Host Start of Frame Interrupt Enable This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI). This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI). RXRSMIE: Upstream Resume Received Interrupt Enable This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI). This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI). RSMEDIE: Downstream Resume Sent Interrupt Enable This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI). This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI). RSTIE: USB Reset Sent Interrupt Enable This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI). This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI). DDISCIE: Device Disconnection Interrupt Enable This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI). This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI). DCONNIE: Device Connection Interrupt Enable This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI). This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI). 713 32072A-AVR32-03/09 AT32UC3A3 27.8.3.6 Host Global Interrupt Enable Clear Register Register Name: UHINTECLR Access Type: Offset: Read Value: Write-Only 0x0414 0x00000000 31 DMA7INTEC 30 DMA6INTEC 29 DMA5INTEC 28 DMA4INTEC 27 DMA3INTEC 26 DMA2INTEC 25 DMA1INTEC 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 P8INTEC 15 P7INTEC 14 P6INTEC 13 P5INTEC 12 P4INTEC 11 P3INTEC 10 P2INTEC 9 P1INTEC 8 P0INTEC 7 - 6 HWUPIEC 5 HSOFIEC 4 RXRSMIEC 3 RSMEDIEC 2 RSTIEC 1 DDISCIEC 0 DCONNIEC Writing a one to a bit in this register will clear the corresponding bit in UHINTE. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 714 32072A-AVR32-03/09 AT32UC3A3 27.8.3.7 Host Global Interrupt Enable Set Register Register Name: UHINTESET Access Type: Offset: Read Value: Write-Only 0x0418 0x00000000 31 DMA7INTES 30 DMA6INTES 29 DMA5INTES 28 DMA4INTES 27 DMA3INTES 26 DMA2INTES 25 DMA1INTES 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 P8INTES 15 P7INTES 14 P6INTES 13 P5INTES 12 P4INTES 11 P3INTES 10 P2INTES 9 P1INTES 8 P0INTES 7 - 6 HWUPIES 5 HSOFIES 4 RXRSMIES 3 RSMEDIES 2 RSTIES 1 DDISCIES 0 DCONNIES Writing a one to a bit in this register will set the corresponding bit in UHINT. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 715 32072A-AVR32-03/09 AT32UC3A3 27.8.3.8 Host Frame Number Register Register Name: UHFNUM Access Type: Offset: Reset Value: Read/Write 0x0420 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 FLENHIGH 19 18 17 16 15 - 14 - 13 12 11 FNUM[10:5] 10 9 8 7 6 5 FNUM[4:0] 4 3 2 1 MFNUM 0 * FLENHIGH: Frame Length In Full speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 30000 to ensure a SOF generation every 1 ms). In High speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 3750 to ensure a SOF generation every 125 us). * FNUM: Frame Number This field contains the current SOF number. This field can be written. In this case, the MFNUM field is reset to zero. * MFNUM: Micro Frame Number This field contains the current Micro Frame number (can vary from 0 to 7) updated every 125us. When operating in full-speed mode, this field is tied to zero. 716 32072A-AVR32-03/09 AT32UC3A3 27.8.3.9 USB Host Frame Number Register (UHADDR1) Register Name: UHADDR1 Access Type: Offset: Reset Value: Read/Write 0x0424 0x00000000 31 - 30 29 28 27 UHADDRP3 26 25 24 23 - 22 21 20 19 UHADDRP2 18 17 16 15 - 14 13 12 11 UHADDRP1 10 9 8 7 - 6 5 4 3 UHADDRP0 2 1 0 * UHADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP2: USB Host Address This field contains the address of the Pipe2 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP1: USB Host Address This field contains the address of the Pipe1 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP0: USB Host Address This field contains the address of the Pipe0 of the USB Device. This field is cleared when a USB reset is requested. 717 32072A-AVR32-03/09 AT32UC3A3 27.8.3.10 Host Frame Number Register Register Name: UHADDR2 Access Type: Offset: Reset Value: Read/Write 0x0428 0x00000000 31 - 30 29 28 27 UHADDRP7 26 25 24 23 - 22 21 20 19 UHADDRP6 18 17 16 15 - 14 13 12 11 UHADDRP5 10 9 8 7 - 6 5 4 3 UHADDRP4 2 1 0 * UHADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP6: USB Host Address This field contains the address of the Pipe6 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP5: USB Host Address This field contains the address of the Pipe5 of the USB Device. This field is cleared when a USB reset is requested. * UHADDRP4: USB Host Address This field contains the address of the Pipe4 of the USB Device. This field is cleared when a USB reset is requested. 718 32072A-AVR32-03/09 AT32UC3A3 27.8.3.11 Host Frame Number Register Register Name: UHADDR3 Access Type: Offset: Reset Value: Read/Write 0x042C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 UHADDRP8 2 1 0 * UHADDRP8: USB Host Address This field contains the address of the Pipe8 of the USB Device. This field is cleared when a USB reset is requested. 719 32072A-AVR32-03/09 AT32UC3A3 27.8.3.12 Pipe Enable/Reset Register Register Name: UPRST Access Type: Offset: Reset Value: Read/Write 0x0041C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 PRST8 23 PRST7 22 PRST6 21 PRST5 20 PRST4 19 PRST3 18 PRST2 17 PRST1 16 PRST0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 PEN8 7 PEN7 6 PEN6 5 PEN5 4 PEN4 3 PEN3 2 PEN2 1 PEN1 0 PEN0 * PRSTn: Pipe n Reset Writing a one to this bit will reset the Pipe n FIFO. This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ). All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management. The endpoint configuration remains active and the endpoint is still enabled. Writing a zero to this bit will complete the reset operation and allow to start using the FIFO. * PENn: Pipe n Enable Writing a one to this bit will enable the Pipe n. Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn, UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE). 720 32072A-AVR32-03/09 AT32UC3A3 27.8.3.13 Pipe n Configuration Register Register Name: UPCFGn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0500 + (n * 0x04) 0x00000000 31 30 29 28 27 26 25 24 INTFRQ/BINTERVAL 23 - 22 - 21 - 20 PINGEN 19 18 PEPNUM 17 16 15 - 14 - 13 PTYPE 12 11 - 10 AUTOSW 9 PTOKEN 8 7 - 6 5 PSIZE 4 3 PBK 2 1 ALLOC 0 - * INTFRQ: Pipe Interrupt Request Frequency This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe. This field is cleared upon sending a USB reset. BINTERVAL: bInterval parameter for the Bulk-Out/Ping transaction This field contains the Ping/Bulk-out period. If BINTERVAL>0 and PINGEN=1, one PING token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral. If BINTERVAL=0 and PINGEN=1, multiple consecutive PING token is sent in the same micro-frame until it is ACKed. If BINTERVAL>0 and PINGEN=0, one OUT token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral. If BINTERVAL=0 and PINGEN=0, multiple consecutive OUT token is sent in the same micro-frame until it is ACKed. This value must be in the range from 0 to 255. PINGEN: Ping Enable This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status stage). Writing a zero to this bit will disable the ping protocol. Writing a one to this bit will enable the ping mechanism according to the usb 2.0 standard. This bit is cleared upon sending a USB reset. PEPNUM: Pipe Endpoint Number This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 15. This field is cleared upon sending a USB reset. PTYPE: Pipe Type This field contains the pipe type. PTYPE 0 0 1 1 0 1 0 1 Pipe Type Control Isochronous Bulk Interrupt * * * * 721 32072A-AVR32-03/09 AT32UC3A3 This field is cleared upon sending a USB reset. * AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 1: The automatic bank switching is enabled. 0: The automatic bank switching is disabled. * PTOKEN: Pipe Token This field contains the endpoint token. PTOKEN 00 01 10 11 Endpoint Direction SETUP IN OUT reserved * PSIZE: Pipe Size This field contains the size of each pipe bank. PSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Endpoint Size 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes This field is cleared upon sending a USB reset. * PBK: Pipe Banks This field contains the number of banks for the pipe. PBK 0 0 1 1 0 1 0 1 Endpoint Banks 1 (single-bank pipe) 2 (double-bank pipe) 3 (triple-bank pipe) Reserved For control endpoints, a single-bank pipe (0b00) should be selected. This field is cleared upon sending a USB reset. * ALLOC: Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory. Writing a zero to this bit will free the pipe memory. This bit is cleared when a USB Reset is requested. Refer to the DPRAM Management chapter for more details. 722 32072A-AVR32-03/09 AT32UC3A3 27.8.3.14 Pipe n Status Register Register Name: UPSTAn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x0530 + (n * 0x04) 0x00000000 31 - 30 29 28 27 PBYCT[10:4] 26 25 24 23 22 PBYCT[3:0] 21 20 19 - 18 CFGOK 17 - 16 RWALL 15 CURRBK 14 13 NBUSYBK 12 11 - 10 - 9 DTSEQ 8 7 SHORT PACKETI 6 RXSTALLDI/ CRCERRI 5 OVERFI 4 NAKEDI 3 PERRI 2 TXSTPI/ UNDERFI 1 TXOUTI 0 RXINI * PBYCT: Pipe Byte Count This field contains the byte count of the FIFO. For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral. For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. * CFGOK: Configuration OK Status This bit is set/cleared when the UPCFGn.ALLOC bit is set. This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register. * RWALL: Read/Write Allowed For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO. This bit is cleared otherwise. This bit is also cleared when the RXSTALL or the PERR bit is one. * CURRBK: Current Bank For non-control pipe, this field indicates the number of the current bank. CURRBK 0 0 1 1 0 1 0 1 Current Bank Bank0 Bank1 Bank2 Reserved This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit. 723 32072A-AVR32-03/09 AT32UC3A3 * NBUSYBK: Number of Busy Banks This field indicates the number of busy bank. For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one. For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one. NBUSYBK 0 0 1 1 0 1 0 1 Number of busy bank All banks are free. 1 busy bank 2 busy banks reserved * DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. DTSEQ 0 0 1 1 0 1 0 1 Data toggle sequence Data0 Data1 reserved reserved * * * * * * * For OUT pipe, this field indicates the data toggle of the next packet that will be sent. For IN pipe, this field indicates the data toggle of the received packet stored in the current bank. SHORTPACKETI: Short Packet Interrupt This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field). This bit is cleared when the SHORTPACKETIC bit is written to one. RXSTALLDI: Received STALLed Interrupt This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe. The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one. This bit is cleared when the RXSTALLDIC bit is written to one. CRCERRI: CRC Error Interrupt This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if the TXSTPE bit is one. This bit is cleared when the CRCERRIC bit is written to one. OVERFI: Overflow Interrupt This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if the OVERFIE bit is one. This bit is cleared when the OVERFIC bit is written to one. NAKEDI: NAKed Interrupt This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one. This bit is cleared when the NAKEDIC bit written to one. PERRI: Pipe Error Interrupt This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to the UPERRn register to determine the source of the error. This bit is cleared when the error source bit is cleared. TXSTPI: Transmitted SETUP Interrupt This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the TXSTPE bit is one. This bit is cleared when the TXSTPIC bit is written to one. 724 32072A-AVR32-03/09 AT32UC3A3 * UNDERFI: Underflow Interrupt This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE bit is one. This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can't send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of. This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current bank of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the overflowed packet is ACKed to respect the USB standard. This bit is cleared when the UNDERFIEC bit is written to one. * TXOUTI: Transmitted OUT Data Interrupt This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one. This bit is cleared when the TXOUTIC bit is written to one. * RXINI: Received IN Data Interrupt This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is one. This bit is cleared when the RXINIC bit is written to one. 725 32072A-AVR32-03/09 AT32UC3A3 27.8.3.15 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0560 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SHORT PACKETIC 6 RXSTALLDI C/ CRCERRIC 5 OVERFIC 4 NAKEDIC 3 - 2 TXSTPIC/ UNDERFIC 1 TXOUTIC 0 RXINIC Writing a one to a bit in this register will clear the corresponding bit in UPSTAn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 726 32072A-AVR32-03/09 AT32UC3A3 27.8.3.16 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0590 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 NBUSYBKS 11 - 10 - 9 - 8 - 7 SHORT PACKETIS 6 RXSTALLDIS/ 5 OVERFIS 4 NAKEDIS 3 PERRIS 2 TXSTPIS/ UNDERFIS 1 TXOUTIS 0 RXINIS CRCERRIS Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 727 32072A-AVR32-03/09 AT32UC3A3 27.8.3.17 Pipe n Control Register Register Name: UPCONn, n in [0..7] Access Type: Offset: Reset Value: Read-Only 0x05C0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 RSTDT 17 PFREEZE 16 PDISHDMA 15 - 14 FIFOCON 13 - 12 NBUSYBKE 11 - 10 - 9 - 8 - 7 SHORT PACKETIE 6 RXSTALLDE /CRCERRE 5 OVERFIE 4 NAKEDE 3 PERRE 2 TXSTPE/ UNDERFIE 1 TXOUTE 0 RXINE * RSTDT: Reset Data Toggle * This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe. This bit is cleared when proceed. PFREEZE: Pipe Freeze This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe requests generation. This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation. PDISHDMA: Pipe Interrupts Disable HDMA Request Enable See the UECONn.EPDISHDMA bit description. FIFOCON: FIFO Control For OUT and SETUP Pipe: This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI. This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank. For IN Pipe: This bit is set when a new IN message is stored in the current bank, at the same time than RXINI. This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank. NBUSYBKE: Number of Busy Banks Interrupt Enable This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE). This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE). SHORTPACKETIE: Short Packet Interrupt Enable This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE). This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT (SHORTPACKETE). * * * * 728 32072A-AVR32-03/09 AT32UC3A3 * RXSTALLDE: Received STALLed Interrupt Enable This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE). This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXSTALLDE). CRCERRE: CRC Error Interrupt Enable This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE). This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE). OVERFIE: Overflow Interrupt Enable This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE). This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE). NAKEDE: NAKed Interrupt Enable This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE). This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE). PERRE: Pipe Error Interrupt Enable This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE). This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE). TXSTPE: Transmitted SETUP Interrupt Enable This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE). This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE). UNDERFIE: Underflow Interrupt Enable This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE). This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UNDERFIE). TXOUTE: Transmitted OUT Data Interrupt Enable This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE). This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE). RXINE: Received IN Data Interrupt Enable This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE). This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE). * * * * * * * * 729 32072A-AVR32-03/09 AT32UC3A3 27.8.3.18 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x0620 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 PFREEZEC 16 PDISHDMAC 15 - 14 FIFOCONC 13 - 12 NBUSYBKEC 11 - 10 - 9 - 8 - 7 SHORT PACKETIEC 6 RXSTALLDEC 5 OVERFIEC 4 NAKEDEC 3 PERREC 2 TXSTPEC/ UNDERFIEC 1 TXOUTEC 0 RXINEC /CRCERREC Writing a one to a bit in this register will clear the corresponding bit in UPCONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 730 32072A-AVR32-03/09 AT32UC3A3 27.8.3.19 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..7] Access Type: Offset: Read Value: Write-Only 0x05F0 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 RSTDTS 17 PFREEZES 16 PDISHDMAS 15 - 14 - 13 - 12 NBUSYBKES 11 - 10 - 9 - 8 - 7 SHORT PACKETIES 6 RXSTALLDES 5 OVERFIES 4 NAKEDES 3 PERRES 2 TXSTPES/ UNDERFIES 1 TXOUTES 0 RXINES /CRCERRES Writing a one to a bit in this register will set the corresponding bit in UPCONn. Writing a zero to a bit in this register has no effect. This bit always reads as zero. 731 32072A-AVR32-03/09 AT32UC3A3 27.8.3.20 Pipe n IN Request Register Register Name: UPINRQn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0650 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 INMODE 7 6 5 4 INRQ 3 2 1 0 * INMODE: IN Request Mode Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen. Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field. * INRQ: IN Request Number before Freeze This field contains the number of IN transactions before the USBB freezes the pipe. The USBB will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed. This register has no effect when the INMODE bit is one (infinite IN requests generation till the pipe is not frozen). 732 32072A-AVR32-03/09 AT32UC3A3 27.8.3.21 Pipe n Error Register Register Name: UPERRn, n in [0..7] Access Type: Offset: Reset Value: Read/Write 0x0680 + (n * 0x04) 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 COUNTER 5 4 CRC16 3 TIMEOUT 2 PID 1 DATAPID 0 DATATGL * COUNTER: Error Counter This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL). This field is cleared when receiving a good usb packet without any error. When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (UPCONn.PFREEZE is set). Writing 0b00 to this field will clear the counter. CRC16: CRC16 Error This bit is set when a CRC16 error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. TIMEOUT: Time-Out Error This bit is set when a Time-Out error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. PID: PID Error This bit is set when a PID error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. DATAPID: Data PID Error This bit is set when a Data PID error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. DATATGL: Data Toggle Error This bit is set when a Data Toggle error has been detected. Writing a zero to this bit will clear the bit. Writing a one to this bit has no effect. * * * * * 733 32072A-AVR32-03/09 AT32UC3A3 27.8.3.22 Host DMA Channel n Next Descriptor Address Register Register Name: UHDMAnNEXTDESC, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0710 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 NXTDESCADDR[31:24] 23 22 21 20 19 18 17 16 NXTDESCADDR[23:16] 15 14 13 12 11 10 9 8 NXTDESCADDR[15:8] 7 6 5 4 3 - 2 - 1 - 0 - NXTDESCADDR[7:4] Same as Section 27.8.2.17. 734 32072A-AVR32-03/09 AT32UC3A3 27.8.3.23 Host DMA Channel n HSB Address Register Register Name: UHDMAnADDR, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0714 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 HSBADDR[31:24] 23 22 21 20 19 18 17 16 HSBADDR[23:16] 15 14 13 12 11 10 9 8 HSBADDR[15:8] 7 6 5 4 3 2 1 0 HSBADDR[7:0] Same as Section 27.8.2.18. 735 32072A-AVR32-03/09 AT32UC3A3 27.8.3.24 USB Host DMA Channel n Control Register Register Name: UHDMAnCONTROL, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x0718 + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTELENGTH[15:8] 23 22 21 20 19 18 17 16 CHBYTELENGTH[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 BURSTLOC KEN 6 DESCLD IRQEN 5 EOBUFF IRQEN 4 EOTIRQEN 3 DMAENDEN 2 BUFFCLOSE INEN 1 LDNXTCHD ESCEN 0 CHEN Same as Section 27.8.2.19. (just replace the IN endpoint term by OUT endpoint, and vice-versa) 736 32072A-AVR32-03/09 AT32UC3A3 27.8.3.25 USB Host DMA Channel n Status Register Register Name: UHDMAnSTATUS, n in [1..7] Access Type: Offset: Reset Value: Read/Write 0x071C + (n - 1) * 0x10 0x00000000 31 30 29 28 27 26 25 24 CHBYTECNT[15:8] 23 22 21 20 19 18 17 16 CHBYTECNT[7:0] 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 DESCLD STA 5 EOCHBUFFS TA 4 EOTSTA 3 - 2 - 1 CHACTIVE 0 CHEN Same as Section 27.8.2.20. 737 32072A-AVR32-03/09 AT32UC3A3 27.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA) The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a 64KB logical address space. The application can access a 64KB buffer linearly or fixedly as the DPRAM address increment is fully handled by hardware. Byte, half-word and word access are supported. Data should be access in a big-endian way. Disabling the USBB (by writing a zero to the USBE bit) does not reset the DPRAM. 738 32072A-AVR32-03/09 AT32UC3A3 27.9 Module Configuration The specific configuration for the USBB instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 27-7. Module name USBB Module Clock Name Clock name CLK_USBB_HSB Clock name CLK_USBB_PB Table 27-8. Register UVERS UFEATURES UADDRSIZE UNAME1 UNAME2 Register Reset Values Reset Value 0x00000320 to be defined to be defined to be defined to be defined 739 32072A-AVR32-03/09 AT32UC3A3 28. Timer/Counter (TC) Rev: 2.2.3.1 28.1 Features * Three 16-bit Timer Counter channels * A wide range of functions including: - Frequency measurement - Event counting - Interval measurement - Pulse generation - Delay timing - Pulse width modulation - Up/down capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Internal interrupt signal * Two global registers that act on all three TC channels 28.2 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC block has two global registers which act upon all three TC channels. The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction. The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained. 740 32072A-AVR32-03/09 AT32UC3A3 28.3 Block Diagram Figure 28-1. TC Block Diagram TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOA1 TIOA2 XC0 XC1 XC2 TC0XC0S SYNC INT0 Timer/Counter Channel 0 TIOA I/O Contr oller CLK0 CLK1 CLK2 A0 B0 TIOA0 TIOB TIOB0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC INT1 Timer/Counter Channel 1 TIOA TIOB TIOA1 TIOB1 A1 B1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB A2 B2 TIOB2 SYNC INT2 Timer Count er Interrupt Controller 28.4 I/O Lines Description Table 28-1. Pin Name CLK0-CLK2 A0-A2 B0-B2 I/O Lines Description Description External Clock Input I/O Line A I/O Line B Type Input Input/Output Input/Output 28.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first program the I/O Controller to assign the TC pins to their peripheral functions. 741 32072A-AVR32-03/09 AT32UC3A3 28.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 28.5.3 28.5.4 Interrupts The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt requires the interrupt controller to be programmed first. 28.5.5 Debug Operation The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 28.6 28.6.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Figure 28-3 on page 757. Channel I/O Signals As described in Figure 28-1 on page 741, each Channel has the following I/O signals. 28.6.1.1 Table 28-2. Channel I/O Signals Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture mode: Timer Counter Input Waveform mode: Timer Counter Output Capture mode: Timer Counter Input Waveform mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 28.6.1.2 16-bit counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 742 32072A-AVR32-03/09 AT32UC3A3 28.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 28-2 on page 743. Each channel can independently select an internal or external clock source for its counter: * Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources. * External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources. This selection is made by the Clock Selection field in the Channel n Mode Register (CMRn.TCCLKS). The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The Burst Signal Selection field in the CMRn register (CMRn.BURST) defines this signal. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC. Figure 28-2. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 28.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 28-3 on page 744. 743 32072A-AVR32-03/09 AT32UC3A3 * The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA). * The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled. Figure 28-3. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 28.6.1.5 TC operating modes Each channel can independently operate in two different modes: * Capture mode provides measurement on signals. * Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs. In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 744 32072A-AVR32-03/09 AT32UC3A3 28.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: * Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). * SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register (BCR.SYNC). * Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn (CMRn.CPCTRG) is written to one. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG). If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 28.6.2 Capture Operating Mode This mode is entered by writing a zero to the CMRn.WAVE bit. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 28-4 on page 747 shows the configuration of the TC channel when programmed in Capture mode. 28.6.2.1 Capture registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in SRn (SRn.LOVRS). In this case, the old value is overwritten. 745 32072A-AVR32-03/09 AT32UC3A3 28.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled. 746 32072A-AVR32-03/09 32072A-AVR32-03/09 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 Q Q S R R Figure 28-4. Capture Mode TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 S LDBSTOP BURST LDBDIS Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LD A R LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = SYNC MTIOB TIOB CPCS COVFS LOVRS LDRBS LDRAS ETRGS SR MTIOA If RA is not Loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector IMR TIOA Timer/Counter Channel INT AT32UC3A3 747 AT32UC3A3 28.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event. Figure 28-5 on page 749 shows the configuration of the TC channel when programmed in Waveform operating mode. 28.6.3.1 Waveform selection Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 748 32072A-AVR32-03/09 Contr o r el l t up u O t Contlr o re l Edge Detector IMR TIOB BSWTRG Timer/Counter Channel AT32UC3A3 749 INT t uO u p t 32072A-AVR32-03/09 TCCLKS CLKSTA CLKDIS CLKI Q R Q R CPCSTOP AEEVT S CPCDIS S ACPA MTIOA CLKEN ACPC TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 Figure 28-5. Waveform Mode TIOA XC2 BURST Register A WAVSEL Register B Register C ASWTRG 1 16-bit Counter CLK OVF Compare RA = Compare RB = Compare RC = SWTRG RESET BCPC T rig BCPB WAVSEL E VT E BEEVT E VTEDG E EN G ETR SR CPCS CPBS CPAS ETRGS COVFS MTIOB SYNC TIOB AT32UC3A3 28.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 28-6 on page 750. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 28-7 on page 751. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 28-6. WAVSEL= 0 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 750 32072A-AVR32-03/09 AT32UC3A3 Figure 28-7. WAVSEL= 0 With Trigger Counter cleared by compare match with 0xFFFF Counter Value 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples TIOB Time TIOA 28.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 28-8 on page 752. It is important to note that CVn can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 28-9 on page 752. In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1). 751 32072A-AVR32-03/09 AT32UC3A3 Figure 28-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 28-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 28.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 28-10 on page 753. 752 32072A-AVR32-03/09 AT32UC3A3 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 28-11 on page 753. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 28-10. WAVSEL = 1 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 28-11. WAVSEL = 1 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC Counter decremented by compare match with 0xFFFF RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 753 32072A-AVR32-03/09 AT32UC3A3 28.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 28-12 on page 754. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 28-13 on page 755. RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 28-12. WAVSEL = 3 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 754 32072A-AVR32-03/09 AT32UC3A3 Figure 28-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 28.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined. If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by writing a one to the CMRn.ENETRG bit. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the CMRn.WAVSEL field. 28.6.3.7 Output controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: * software trigger * external event * RC compare RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn: * RC Compare Effect on TIOB (CMRn.BCPC) 755 32072A-AVR32-03/09 AT32UC3A3 * RB Compare Effect on TIOB (CMRn.BCPB) * RC Compare Effect on TIOA (CMRn.ACPC) * RA Compare Effect on TIOA (CMRn.ACPA) 756 32072A-AVR32-03/09 AT32UC3A3 28.7 User Interface TC Register Memory Map Register Channel 0 Control Register Channel 0 Mode Register Channel 0 Counter Value Channel 0 Register A Channel 0 Register B Channel 0 Register C Channel 0 Status Register Interrupt Enable Register Channel 0 Interrupt Disable Register Channel 0 Interrupt Mask Register Channel 1 Control Register Channel 1 Mode Register Channel 1 Counter Value Channel 1 Register A Channel 1 Register B Channel 1 Register C Channel 1 Status Register Channel 1 Interrupt Enable Register Channel 1 Interrupt Disable Register Channel 1 Interrupt Mask Register Channel 2 Control Register Channel 2 Mode Register Channel 2 Counter Value Channel 2 Register A Channel 2 Register B Channel 2 Register C Channel 2 Status Register Channel 2 Interrupt Enable Register Channel 2 Interrupt Disable Register Channel 2 Interrupt Mask Register Block Control Register Block Mode Register Notes: Register Name CCR0 CMR0 CV0 RA0 RB0 RC0 SR0 IER0 IDR0 IMR0 CCR1 CMR1 CV1 RA1 RB1 RC1 SR1 IER1 IDR1 IMR1 CCR2 CMR2 CV2 RA2 RB2 RC2 SR2 IER2 IDR2 IMR2 BCR BMR Access Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write Read/Write (1) (1) Table 28-3. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x40 0x44 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x80 0x84 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xC0 0xC4 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 00x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write 1. Read-only if CMRn.WAVE is zero 757 32072A-AVR32-03/09 AT32UC3A3 28.7.1 Name: Channel Control Register CCR Write-only 0x00 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SWTRG 1 CLKDIS 0 CLKEN * SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect. * CLKDIS: Counter Clock Disable Command 1: Writing a one to this bit will disable the clock. 0: Writing a zero to this bit has no effect. * CLKEN: Counter Clock Enable Command 1: Writing a one to this bit will enable the clock if CLKDIS is not one. 0: Writing a zero to this bit has no effect. 758 32072A-AVR32-03/09 AT32UC3A3 28.7.2 Name: Channel Mode Register: Capture Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 LDRB 18 17 LDRA 16 15 WAVE 14 CPCTRG 13 - 12 - 11 - 10 ABETRG 9 ETRGEDG 8 7 LDBDIS 6 LDBSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 * LDRB: RB Loading Selection LDRB 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA * LDRA: RA Loading Selection LDRA 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA * WAVE 1: Capture mode is disabled (Waveform mode is enabled). 0: Capture mode is enabled. * CPCTRG: RC Compare Trigger Enable 1: RC Compare resets the counter and starts the counter clock. 0: RC Compare has no effect on the counter and its clock. * ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 759 32072A-AVR32-03/09 AT32UC3A3 0: TIOB is used as an external trigger. * ETRGEDG: External Trigger Edge Selection ETRGEDG 0 1 2 3 Edge none rising edge falling edge each edge * LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. * LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs. * BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal XC0 is ANDed with the selected clock XC1 is ANDed with the selected clock XC2 is ANDed with the selected clock * CLKI: Clock Invert 1: The counter is incremented on falling edge of the clock. 0: The counter is incremented on rising edge of the clock. * TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 760 32072A-AVR32-03/09 AT32UC3A3 28.7.3 Name: Channel Mode Register: Waveform Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 BSWTRG 30 29 BEEVT 28 27 BCPC 26 25 BCPB 24 23 ASWTRG 22 21 AEEVT 20 19 ACPC 18 17 ACPA 16 15 WAVE 14 WAVSEL 13 12 ENETRG 11 EEVT 10 9 EEVTEDG 8 7 CPCDIS 6 CPCSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 * BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 1 2 3 Effect none set clear toggle * BEEVT: External Event Effect on TIOB BEEVT 0 1 2 3 Effect none set clear toggle 761 32072A-AVR32-03/09 AT32UC3A3 * BCPC: RC Compare Effect on TIOB BCPC 0 1 2 3 Effect none set clear toggle * BCPB: RB Compare Effect on TIOB BCPB 0 1 2 3 Effect none set clear toggle * ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 1 2 3 Effect none set clear toggle * AEEVT: External Event Effect on TIOA AEEVT 0 1 2 3 Effect none set clear toggle * ACPC: RC Compare Effect on TIOA ACPC 0 1 2 3 Effect none set clear toggle 762 32072A-AVR32-03/09 AT32UC3A3 * ACPA: RA Compare Effect on TIOA ACPA 0 1 2 3 Effect none set clear toggle * WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). * WAVSEL: Waveform Selection WAVSEL 0 1 2 3 Effect UP mode without automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare * ENETRG: External Event Trigger Enable 1: The external event resets the counter and starts the counter clock. 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. * EEVT: External Event Selection EEVT 0 1 2 3 Note: Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. * EEVTEDG: External Event Edge Selection EEVTEDG 0 1 2 3 Edge none rising edge falling edge each edge * CPCDIS: Counter Clock Disable with RC Compare 1: Counter clock is disabled when counter reaches RC. 0: Counter clock is not disabled when counter reaches RC. * CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 763 32072A-AVR32-03/09 AT32UC3A3 0: Counter clock is not stopped when counter reaches RC. * BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock. 0: Counter is incremented on rising edge of the clock. * TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 764 32072A-AVR32-03/09 AT32UC3A3 28.7.4 Name: Channel Counter Value Register CV Read-only 0x10 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 CV[15:8] 11 10 9 8 7 6 5 4 CV[7:0] 3 2 1 0 * CV: Counter Value CV contains the counter value in real time. 765 32072A-AVR32-03/09 AT32UC3A3 28.7.5 Name: Channel Register A RA Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x14 + n * 0X40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RA[15:8] 11 10 9 8 7 6 5 4 RA[7:0] 3 2 1 0 * RA: Register A RA contains the Register A value in real time. 766 32072A-AVR32-03/09 AT32UC3A3 28.7.6 Name: Channel Register B RB Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x18 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RB[15:8] 11 10 9 8 7 6 5 4 RB[7:0] 3 2 1 0 * RB: Register B RB contains the Register B value in real time. 767 32072A-AVR32-03/09 AT32UC3A3 28.7.7 Name: Channel Register C RC Read/Write 0x1C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RC[15:8] 11 10 9 8 7 6 5 4 RC[7:0] 3 2 1 0 * RC: Register C RC contains the Register C value in real time. 768 32072A-AVR32-03/09 AT32UC3A3 28.7.8 Name: Channel Status Register SR Read-only 0x20 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 MTIOB 17 MTIOA 16 CLKSTA 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. * MTIOB: TIOB Mirror 1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high. 0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low. * MTIOA: TIOA Mirror 1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high. 0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low. * CLKSTA: Clock Enabling Status 1: This bit is set when the clock is enabled. 0: This bit is cleared when the clock is disabled. * ETRGS: External Trigger Status 1: This bit is set when an external trigger has occurred. 0: This bit is cleared when the SR register is read. * LDRBS: RB Loading Status 1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. * LDRAS: RA Loading Status 1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. * CPCS: RC Compare Status 1: This bit is set when an RC Compare has occurred. 0: This bit is cleared when the SR register is read. 769 32072A-AVR32-03/09 AT32UC3A3 * CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. * CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. * LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. * COVFS: Counter Overflow Status 1: This bit is set when a counter overflow has occurred. 0: This bit is cleared when the SR register is read. 770 32072A-AVR32-03/09 AT32UC3A3 28.7.9 Name: Channel Interrupt Enable Register IER Write-only 0x24 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 771 32072A-AVR32-03/09 AT32UC3A3 28.7.10 Name: Channel Interrupt Disable Register IDR Write-only 0x28 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 772 32072A-AVR32-03/09 AT32UC3A3 28.7.11 Name: Channel Interrupt Mask Register IMR Read-only 0x2C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 773 32072A-AVR32-03/09 AT32UC3A3 28.7.12 Name: Block Control Register BCR Write-only 0xC0 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SYNC * SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect. 774 32072A-AVR32-03/09 AT32UC3A3 28.7.13 Name: Block Mode Register BMR Read/Write 0xC4 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 TC2XC2S 4 3 TC1XC1S 2 1 TC0XC0S 0 * TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 1 2 3 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 * TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 1 2 3 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 * TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 Signal Connected to XC0 TCLK0 775 32072A-AVR32-03/09 AT32UC3A3 1 2 3 none TIOA1 TIOA2 776 32072A-AVR32-03/09 AT32UC3A3 28.8 Module Configuration The specific configuration for each TC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 28-4. Module name TC0 TC1 Module Clock Name Clock name CLK_TC0 CLK_TC1 28.8.1 Clock Connections Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 28-5. Name Timer/Counter Internal Clock Connections Connection 32 KHz clock PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 777 32072A-AVR32-03/09 AT32UC3A3 29. Analog-to-Digital Converter (ADC) Rev: 2.0.0.1 29.1 Features * Integrated multiplexer offering up to eight independent analog inputs * Individual enable and disable of each channel * Hardware or software trigger - External trigger pin - Timer counter outputs (corresponding TIOA trigger) * PDC support * Possibility of ADC timings configuration * Sleep mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 29.2 Overview The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR) 10-bit ADC. It also integrates an ADC_NB_CHANNELS-to-1 analog multiplexer, making possible the analog-to-digital conversions of ADC_NB_CHANNELS analog lines. The conversions extend from 0V to VDDANA. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter output(s) are configurable. The ADC also integrates a sleep mode and a conversion sequencer and connects with a Peripheral DMA Controller channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as startup time and sample & hold time. 778 32072A-AVR32-03/09 AT32UC3A3 29.3 Block Diagram Figure 29-1. ADC Block Diagram Timer Counter Channels ADC TRIGGER Trigger Selection Control Logic ADC Interrupt Interrupt Controller VDDANA VREF High Speed Bus (HSB) ADDedicated Analog Inputs ADUser Interface Peripheral DMA Controller Peripheral Bridge AD- ADAnalog Inputs Multiplexed With I/O lines ADI/O Controller Successive Approximation Register Analog-to-Digital Converter Peripheral Bus (PB) AD- GND 29.4 I/O Lines Description ADC Pins Description Description Analog power supply Analog input channels External trigger Table 29-1. Pin Name VDDANA AD[0] - AD[ADC_NB_CHANNELS-1] TRIGGER 29.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 29.5.1 I/O Lines The TRIGGER pin may be shared with other peripheral functions through the I/O Controller. Refer to the Peripheral Event System chapter for details 779 32072A-AVR32-03/09 AT32UC3A3 29.5.2 Power Management In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the ADC behavior. Clocks The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ADC before disabling the clock, to avoid freezing the ADC in an undefined state. 29.5.3 29.5.4 Interrupts The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt controller to be programmed first. 29.5.5 Analog Inputs The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER). By default, after reset, the I/O line is configured as input with its pull-up enabled and the ADC input is connected to the ground. 29.5.6 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. 29.6 29.6.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL). The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC Clock frequency according to the parameters given in the Electrical Characteristics chapter. 29.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage connected to VDDANA. Analog input values between these voltages are converted to digital values based on a linear conversion. Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the Channel Data Registers (CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Register (LCDR.LDATA) will be read as zero too. 29.6.3 780 32072A-AVR32-03/09 AT32UC3A3 Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 29.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of the current channel and in the LCDR register. Channels are enabled by writing a one to the Channel n Enable bit (CHn) in the CHER register. The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY can trigger an interrupt. Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. Figure 29-2. EOCn and DRDY Flag Behavior Write CR With START=1 Read CDRn Write CR With START=1 Read LCDR CHn(CHSR) EOCn(SR) Conversion Time Conversion Time DRDY(SR) 781 32072A-AVR32-03/09 AT32UC3A3 If the CDR register is not read before further incoming data is converted, the corresponding Overrun Error bit in the SR register (SR.OVREn) is set. In the same way, new data converted when DRDY is high sets the General Overrun Error bit in the SR register (SR.GOVRE). The OVREn and GOVRE bits are automatically cleared when the SR register is read. Figure 29-3. GOVRE and OVREn Flag Behavior Read SR TRIGGER CH0(CHSR) CH1(CHSR) LCDR CRD0 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Data C CRD1 Data B EOC0(SR) Conversion Conversion Read CDR0 EOC1(SR) Conversion Read CDR1 GOVRE(SR) DRDY(ASR) OVRE0(SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable. 782 32072A-AVR32-03/09 AT32UC3A3 29.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing a one to the START bit in the Control Register (CR.START). The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 29.6.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in the Mode Register (MR.SLEEP). The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the Peripheral DMA Controller. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 783 32072A-AVR32-03/09 AT32UC3A3 29.6.7 ADC Timings Each ADC has its own minimal startup time that is defined through the Start Up Time field in the Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics chapter. In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be defined through the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. 29.6.8 Conversion Performances For performance and electrical characteristics of the ADC, see the Electrical Characteristics chapter. 784 32072A-AVR32-03/09 AT32UC3A3 29.7 User Interface ADC Register Memory Map Register Control Register Mode Register Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 ...(if implemented) Channel Data Register 7(if implemented) Version Register Name CR MR CHER CHDR CHSR SR LCDR IER IDR IMR CDR0 ... CDR7 VERSION Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only ... Read-only Read-only Reset State 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000C0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ... 0x00000000 - (1) Table 29-2. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 ... 0x4C 0xFC Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 785 32072A-AVR32-03/09 AT32UC3A3 29.7.1 Name: Control Register CR Write-only 0x00 0x00000000 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 START 24 - 16 - 8 - 0 SWRST Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 - * START: Start Conversion Writing a one to this bit will begin an analog-to-digital conversion. Writing a zero to this bit has no effect. This bit always reads zero. * SWRST: Software Reset Writing a one to this bit will reset the ADC. Writing a zero to this bit has no effect. This bit always reads zero. 786 32072A-AVR32-03/09 AT32UC3A3 29.7.2 Name: Mode Register MR Read/Write 0x04 0x00000000 30 - 22 29 - 21 28 - 20 27 26 SHTIM 19 STARTUP 11 PRESCAL 7 - 6 - 5 SLEEP 4 LOWRES 3 2 TRGSEL 1 0 TRGEN 18 17 16 25 24 Access Type: Offset: Reset Value: 31 - 23 - 15 14 13 12 10 9 8 * SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock * STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock * PRESCAL: Prescaler Rate Selection ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 ) * SLEEP: Sleep Mode 1: Sleep Mode is selected. 0: Normal Mode is selected. * LOWRES: Resolution 1: 8-bit resolution is selected. 0: 10-bit resolution is selected. * TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Selected TRGSEL Internal Trigger 0, depending of chip integration Internal Trigger 1, depending of chip integration Internal Trigger 2, depending of chip integration Internal Trigger 3, depending of chip integration Internal Trigger 4, depending of chip integration Internal Trigger 5, depending of chip integration External trigger * TRGEN: Trigger Enable 1: The hardware trigger selected by the TRGSEL field is enabled. 0: The hardware triggers are disabled. Starting a conversion is only possible by software. 787 32072A-AVR32-03/09 AT32UC3A3 29.7.3 Name: Channel Enable Register CHER Write-only 0x10 0x00000000 30 - 22 - 14 - 6 CH6 29 - 21 - 13 - 5 CH5 28 - 20 - 12 - 4 CH4 27 - 19 - 11 - 3 CH3 26 - 18 - 10 - 2 CH2 25 - 17 - 9 - 1 CH1 24 - 16 - 8 - 0 CH0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 CH7 * CHn: Channel n Enable Writing a one to these bits will set the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero. 788 32072A-AVR32-03/09 AT32UC3A3 29.7.4 Name: Channel Disable Register CHDR Write-only 0x14 0x00000000 30 - 22 - 14 - 6 CH6 29 - 21 - 13 - 5 CH5 28 - 20 - 12 - 4 CH4 27 - 19 - 11 - 3 CH3 26 - 18 - 10 - 2 CH2 25 - 17 - 9 - 1 CH1 24 - 16 - 8 - 0 CH0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 CH7 * CHn: Channel n Disable Writing a one to these bits will clear the corresponding bit in CHSR. Writing a zero to these bits has no effect. These bits always read a zero. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in SR are unpredictable. 789 32072A-AVR32-03/09 AT32UC3A3 29.7.5 Name: Channel Status Register CHSR Read-only 0x18 0x00000000 30 - 22 - 14 - 6 CH6 29 - 21 - 13 - 5 CH5 28 - 20 - 12 - 4 CH4 27 - 19 - 11 - 3 CH3 26 - 18 - 10 - 2 CH2 25 - 17 - 9 - 1 CH1 24 - 16 - 8 - 0 CH0 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 CH7 * CHn: Channel n Status These bits are set when the corresponding bits in CHER is written to one. These bits are cleared when the corresponding bits in CHDR is written to one. 1: The corresponding channel is enabled. 0: The corresponding channel is disabled. 790 32072A-AVR32-03/09 AT32UC3A3 29.7.6 Name: Status Register SR Read-only 0x1C 0x000C0000 30 - 22 - 14 OVRE6 6 EOC6 29 - 21 - 13 OVRE5 5 EOC5 28 - 20 - 12 OVRE4 4 EOC4 27 - 19 RXBUFF 11 OVRE3 3 EOC3 26 - 18 ENDRX 10 OVRE2 2 EOC2 25 - 17 GOVRE 9 OVRE1 1 EOC1 24 - 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 - 23 - 15 OVRE7 7 EOC7 * RXBUFF: RX Buffer Full This bit is set when the Buffer Full signal from the Peripheral DMA is active. This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive. * ENDRX: End of RX Buffer This bit is set when the End Receive signal from the Peripheral DMA is active. This bit is cleared when the End Receive signal from the Peripheral DMA is inactive. * GOVRE: General Overrun Error This bit is set when a General Overrun Error has occurred. This bit is cleared when the SR register is read. 1: At least one General Overrun Error has occurred since the last read of the SR register. 0: No General Overrun Error occurred since the last read of the SR register. * DRDY: Data Ready This bit is set when a data has been converted and is available in the LCDR register. This bit is cleared when the LCDR register is read. 0: No data has been converted since the last read of the LCDR register. 1: At least one data has been converted and is available in the LCDR register. * OVREn: Overrun Error n These bits are set when an overrun error on the corresponding channel has occurred (if implemented). These bits are cleared when the SR register is read. 0: No overrun error on the corresponding channel (if implemented) since the last read of SR. 1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR. * EOCn: End of Conversion n These bits are set when the corresponding conversion is complete. These bits are cleared when the corresponding CDR or LCDR registers are read. 0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished. 1: Corresponding analog channel (if implemented) is enabled and conversion is complete. 791 32072A-AVR32-03/09 AT32UC3A3 29.7.7 Name: Last Converted Data Register LCDR Read-only 0x20 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 LDATA[7:0] * LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 LDATA[9:8] 1 0 24 - 16 - 8 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 792 32072A-AVR32-03/09 AT32UC3A3 29.7.8 Name: Interrupt Enable Register IER Write-only 0x24 0x00000000 30 - 22 - 14 OVRE6 6 EOC6 29 - 21 - 13 OVRE5 5 EOC5 28 - 20 - 12 OVRE4 4 EOC4 27 - 19 RXBUFF 11 OVRE3 3 EOC3 26 - 18 ENDRX 10 OVRE2 2 EOC2 25 - 17 GOVRE 9 OVRE1 1 EOC1 24 - 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 - 23 - 15 OVRE7 7 EOC7 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 793 32072A-AVR32-03/09 AT32UC3A3 29.7.9 Name: Interrupt Disable Register IDR Write-only 0x28 0x00000000 30 - 22 - 14 OVRE6 6 EOC6 29 - 21 - 13 OVRE5 5 EOC5 28 - 20 - 12 OVRE4 4 EOC4 27 - 19 RXBUFF 11 OVRE3 3 EOC3 26 - 18 ENDRX 10 OVRE2 2 EOC2 25 - 17 GOVRE 9 OVRE1 1 EOC1 24 - 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 - 23 - 15 OVRE7 7 EOC7 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 794 32072A-AVR32-03/09 AT32UC3A3 29.7.10 Name: Interrupt Mask Register IMR Read-only 0x2C 0x00000000 30 - 22 - 14 OVRE6 6 EOC6 29 - 21 - 13 OVRE5 5 EOC5 28 - 20 - 12 OVRE4 4 EOC4 27 - 19 RXBUFF 11 OVRE3 3 EOC3 26 - 18 ENDRX 10 OVRE2 2 EOC2 25 - 17 GOVRE 9 OVRE1 1 EOC1 24 - 16 DRDY 8 OVRE0 0 EOC0 Access Type: Offset: Reset Value: 31 - 23 - 15 OVRE7 7 EOC7 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is cleared when the corresponding bit in IER is written to one. 795 32072A-AVR32-03/09 AT32UC3A3 29.7.11 Name: Channel Data Register CDRx Read-only 0x2C-0x4C 0x00000000 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DATA[7:0] * DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 DATA[9:8] 1 0 24 - 16 - 8 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 796 32072A-AVR32-03/09 AT32UC3A3 29.7.12 Name: Version Register VERSION Read-only 0xFC - 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 VERSION[7:0] * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associated. 27 - 19 26 - 18 VARIANT 11 10 9 VERSION[11:8] 2 1 8 25 - 17 24 - 16 Access Type: Offset: Reset Value: 31 - 23 - 15 - 7 3 0 797 32072A-AVR32-03/09 AT32UC3A3 29.8 Module Configuration The specific configuration for the ADC instance is listed in the following tables.The modPower Manager section. Table 29-3. Feature Module configuration ADC0 8 TIOA Ouput A of the Timer Counter Channel 0 TIOB Ouput B of the Timer Counter Channel 0 TIOA Ouput A of the Timer Counter Channel 1 TIOB Ouput B of the Timer Counter Channel 1 TIOA Ouput A of the Timer Counter Channel 2 TIOBOuput B of the Timer Counter Channel 2 ADC_NUM_CHANNELS Internal Trigger 0 Internal Trigger 1 Internal Trigger 2 Internal Trigger 3 Internal Trigger 4 Internal Trigger 5 Table 29-4. Module name ADC0 Module Clock Name Clock name CLK_ADC0 Table 29-5. Module name VERSION Register Reset Values Reset Value 0x00000200 798 32072A-AVR32-03/09 AT32UC3A3 30. HSB Bus Performance Monitor (BUSMON) Rev 1.0.0.0 30.1 Features * Allows performance monitoring of High Speed Bus master interfaces - Up to 4 masters can be monitored - Peripheral Bus access to monitor registers * The following is monitored - Data transfer cycles - Bus stall cycles - Maximum access latency for a single transfer * Automatic handling of event overflow 30.2 Overview BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB). Up to 4 device-specific masters can be measured. Each of these masters is part of a measurement channel. Which masters that are connected to a channel is device-specific. Devices may choose not to implement all channels. 30.3 Block Diagram Figure 30-1. BUSMON Block Diagram Master A Master B Master C Master D Channel 0 Slave 0 Registers Master E Master F Master G Master H Channel 1 Slave 1 Registers Master I Master J Master K Master L Channel 2 Slave 2 Registers Master M Master N Master O Master P Channel 3 Slave 3 Registers Control Peripheral Bus Interface 799 32072A-AVR32-03/09 AT32UC3A3 30.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.4.1 Clocks The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager. This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined state. 30.5 Functional Description Three different parameters can be measured by each channel: * The number of data transfer cycles since last channel reset * The number of stall cycles since last channel reset * The maximum continuous number of stall cycles since last channel reset (This approximates the max latency in the transfers.) These measurements can be extracted by software and used to generate indicators for bus latency, bus load and maximum bus latency. Each of the counters have a fixed width, and may therefore overflow. When overflow is encountered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles (STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit is written to one, the channel registers are frozen when either DATAn or STALLn reaches its maximum value. This simplifies one-shot readout of the counter values. The registers can also be manually reset by writing to the CONTROL register. The Channeln Max Initiation Latency (LATn) register is saturating, when its max count is reached, it will be set to its maximum value. The LATn register is reset whenever DATAn and STALLn are reset. A counter must manually be enabled by writing to the CONTROL register. 800 32072A-AVR32-03/09 AT32UC3A3 30.6 User interface BUSMON Register Memory Map Register Control register Channel0 Data Cycles register Channel0 Stall Cycles register Channel0 Max Initiation Latency register Channel1 Data Cycles register Channel1 Stall Cycles register Channel1 Max Initiation Latency register Channel2 Data Cycles register Channel2 Stall Cycles register Channel2 Max Initiation Latency register Channel3 Data Cycles register Channel3 Stall Cycles register Channel3 Max Initiation Latency register Parameter register Version register Register Name CONTROL DATA0 STALL0 LAT0 DATA1 STALL1 LAT1 DATA2 STALL2 LAT2 DATA3 STALL3 LAT3 PARAMETER VERSION Access Read/Write Read Read Read Read Read Read Read Read Read Read Read Read Read Read Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) Table 30-1. Offset 0x00 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 0x40 0x44 0x48 0x50 0x54 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 801 32072A-AVR32-03/09 AT32UC3A3 30.6.1 Name: Control Register CONTROL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 CH3RES 18 CH2RES 17 CH1RES 16 CH0RES 15 - 14 - 13 - 12 - 11 CH3OF 10 CH2OF 9 CH1OF 8 CH0OF 7 - 6 - 5 - 4 - 3 CH3EN 2 CH2EN 1 CH1EN 0 CH0EN * CHnRES: Channel Counter Reset Writting a one to this bit will reset the counter in the channel n. Writting a zero to this bit has no effect. This bit always reads as zero. * CHnOF: Channel Overflow Freeze 1: All channel n registers are frozen just before DATA or STALL overflows. 0: The channel n registers are reset if DATA or STALL overflows. * CHnEN: Channel Enabled 1: The channel n is enabled. 0: The channel n is disabled. 802 32072A-AVR32-03/09 AT32UC3A3 30.6.2 Name: Channel n Data Cycles Register DATAn Read-Only 0x10 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA: Data cycles counted since the last reset. 803 32072A-AVR32-03/09 AT32UC3A3 30.6.3 Name: Channel n Stall Cycles Register STALLn Read-Only 0x14 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 STALL[31:24] 27 26 25 24 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 * STALL: Stall cycles counted since the last reset. 804 32072A-AVR32-03/09 AT32UC3A3 30.6.4 Name: Channel n Max Transfer Initiation Cycles Register LATn Read-Only 0x18 + n*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 LAT[31:24] 27 26 25 24 23 22 21 20 LAT[23:16] 19 18 17 16 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 * LAT: This field is cleared whenever the DATA or STALL register is reset. Maximum transfer initiation cycles counted since the last reset. This counter is saturating. 805 32072A-AVR32-03/09 AT32UC3A3 30.6.5 Name: Parameter Register PARAMETER Read-only 0x50 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 CH3IMPL 2 CH2IMPL 1 CH1IMPL 0 CH0IMPL * CHnIMP: Channel Implementation 1: The corresponding channel is implemented. 0: The corresponding channel is not implemented. 806 32072A-AVR32-03/09 AT32UC3A3 30.6.6 Name: Version Register VERSION Read-only 0x54 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associated. 807 32072A-AVR32-03/09 AT32UC3A3 30.7 Module Configuration Table 30-2. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000100 0x0000000F 808 32072A-AVR32-03/09 AT32UC3A3 31. MultiMedia Card Interface (MCI) Rev. 3.0.3.6 31.1 Features * * * * * * * * * * * * * Compatible with Multimedia Card specification version 4.2 Compatible with SD Memory Card specification version 2.0 Compatible with SDIO specification version 1.1 Compatible with CE-ATA specification 1.1 Cards clock rate up to master clock divided by two High Speed mode support Embedded power management to slow down clock rate when not used Supports 2 Slots - Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card Support for stream, block and multi-block data read and write Supports connection to DMA Controller - Minimizes processor intervention for large buffer transfers Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access Support for CE-ATA completion cignal disable command Protection against unexpected modification on-the-Fly of the configuration registers 31.2 Overview The Multimedia Card Interface (MCI) supports the MultiMedia Card (MMC) specification V4.2, the SD Memory Card specification V2.0, the SDIO V1.1 specificationand CE-ATA specification V1.1. The MCI includes a Command Register (CMDR), Response Registers (RSPRn), data registers, time-out counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller, minimizing processor intervention for large buffers transfers. The MCI operates at a rate of up to CLK_MCI divided by 2 and supports the interfacing of 2 Slots. Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). The SDCard/SDIO Slot Selection field in the SDCard/SDIO Register (SDCR.SDCSEL) performs this selection. The SD Memory Card communication is based on a nine-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a seven-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. MCI fully supports CE-ATA Revision 1.1, built on the MMC System specification V4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 809 32072A-AVR32-03/09 AT32UC3A3 31.3 Block Diagram Figure 31-1. MCI Block Diagram Peripheral Bus Brigde DMA Controller Peripheral Bus CLK CMD MCI Interface Power Manager CLK_MCI I/O controller DATA Interrupt Control MCI Interrupt Figure 31-2. Application Block Diagram Application Layer Ex: File System, Audio, Security, etc Physical Layer MCI Interface 12 34567 1 2 3 4 5 6 78 9 910 1213 8 MMC SDCard 810 32072A-AVR32-03/09 AT32UC3A3 31.4 I/O Lines Description I/O Lines Description Pin Description Command/Response Clock Data 0..7 of Slot A Data 0..7 of Slot B Type (1) Input/Output/ PP/OD Input/Output Input/Output/PP Input/Output/PP Comments CMD of a MMC or SDCard/SDIO CLK of a MMC or SD Card/SDIO DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO DAT[0..7] of a MMC DAT[0..3] of a SD Card/SDIO Table 31-1. Pin Name CMD[1:0] CLK DATA[7:0] DATA[15:8] 1. PP: Push/Pull, OD: Open Drain 31.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 31.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the MCI, the MCI will stop functioning and resume operation after the system wakes up from sleep mode. I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with GPIO lines. User must first program the I/O controller to assign the peripheral functions to MCI pins. 31.5.2 31.5.3 Clocks The clock for the MCI bus interface (CLK_MCI) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the MCI before disabling the clock, to avoid freezing the MCI in an undefined state. 31.5.4 Interrupt The MCI interrupt request line is connected to the interrupt controller. Using the MCI interrupt requires the interrupt controller to be programmed first. 31.6 31.6.1 Functional Description Bus Topology Figure 31-3. Multimedia Memory Card Bus Topology 12 34567 910 1213 8 MMC 811 32072A-AVR32-03/09 AT32UC3A3 The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 31-2. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: Bus Topology Name DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] DAT[4] DAT[5] DAT[6] DAT[7] Type(1) I/O/PP I/O/PP/OD S S I/O S I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP I/O/PP Description Data Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 Data 1 Data 2 Data 4 Data 5 Data 6 Data 7 MCI Pin Name(2) (Slot z) DATAz[3] CMDz VSS VDD CLK VSS DATAz[0] DATAz[1] DATAz[2] DATAz[4] DATAz[5] DATAz[6] DATAz[7] 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. Figure 31-4. MMC Bus Connections (One Slot) MCI CMD DATA[0] CLK 12 34567 91011 1213 8 MMC1 12 34567 91011 1213 8 MMC2 12 34567 91011 1213 8 MMC3 Figure 31-5. SD Memory Card Bus Topology 12345678 9 SDCARD 812 32072A-AVR32-03/09 AT32UC3A3 The SD Memory Card bus includes the signals listed in Table 31-3 on page 813. Table 31-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) DATAz[3] CMDz VSS VDD CLK VSS DATAz[0] DATAz[1] DATAz[2] I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. Figure 31-6. SD Card Bus Connections with One Slot DATA[3:0] CLK CMD 12345678 SDCARD Figure 31-7. SD Card Bus Connections with Two Slots DATA[3:0] CLK CMD[0] 1 234 5678 1 234 5678 DATA[7:4] CMD[1] 9 9 SDCARD2 9 SDCARD1 813 32072A-AVR32-03/09 AT32UC3A3 Figure 31-8. Mixing MultiMedia and SD Memory Cards with Two Slots DATA[7:0] CMD[0] CLK 12 34567 91011 1213 8 MMC1 12 34567 91011 1213 8 MMC2 12 34567 91011 1213 8 MMC3 DATA[11:8] 12 345 678 SDCARD CMD[1] When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the SDCard /SDIO Bus Width field in the SDCR register (SDCR.SDCBUS). See Section "31.7.4" on page 834. for details. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent GPIOs. 31.6.2 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: * Command: a command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the CMD line. * Response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. * Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. Refer also to Table 31-4 on page 816. MultiMediaCard bus data transfers are composed of these tokens. 9 814 32072A-AVR32-03/09 AT32UC3A3 There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI clock (CLK). Two types of data transfer commands are defined: * Sequential commands: these commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. * Block-oriented commands: these commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See Section "31.6.3" on page 817.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 31.6.2.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the Multi-Media Interface Enable bit in the Control Register (CR.MCIEN). The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the MCI clock (CLK) by 2PWSDIV + 1 when the bus is inactive. The Power Saving Divider field locates in the Mode Register (MR.PWSDIV). The two bits, Read Proof Enable and Write Proof Enable in the MR register (MR.RDPROOF and MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the Command Register (CMDR). The CMDR register allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z 815 32072A-AVR32-03/09 AT32UC3A3 The command ALL_SEND_CID and the fields and values for CMDR register are described in Table 31-4 on page 816 and Table 31-5 on page 816. Table 31-4. CMD Index ALL_SEND_CID Command Description Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Note: bcr means broadcast command with response. Table 31-5. Field Fields and Values for the CMDR register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The Argument Register (ARGR) contains the argument field of the command. To send a command, the user must perform the following steps: * Set the ARGR register with the command argument. * Set the CMDR register (see Table 31-5 on page 816). The command is sent immediately after writing the command register. As soon as the command register is written, then the Command Ready bit in the Status Register (SR.CMDRDY) is cleared. It is released and the end of the card response. If the command requires a response, it can be read in the Response Registers (RSPRn). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (IER) allows using an interrupt method. 816 32072A-AVR32-03/09 AT32UC3A3 Figure 31-9. Command/Response Functional Flow Diagram Set the command argument ARGR = Argument(1) Set the command CMD = Command Read the SR register Wait for SR.CMDRY bit set to one 0 SR.CMDRDY 1 Check error bits in the SR register(1) Yes Status error bits? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error bit is always present (refer to R3 response in the MultiMedia Card specification). 31.6.3 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type field in the CMDR register (CMDR.TRTYP). These operations can be done using the features of the DMA Controller. In all cases, the Data Block Length must be defined either in the Data Block Length field in the MR register (MR.BLKLEN)), or in the Block Register (BLKR). This field determines the size of the data block. 817 32072A-AVR32-03/09 AT32UC3A3 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): * Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. * Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly set the BLKR register. Otherwise the card will start an openended multiple block read. The MMC/SDIO Block Count - SDIO Byte Count field in the BLKR register (BLKR.BCNT) defines the number of blocks to transfer (from 1 to 65535 blocks). Writing zero to this field corresponds to an infinite block transfer. 31.6.4 Read/Write Operation The following flowchart shows how to read a single block with or without use of DMA Controller facilities. In this example (see Figure 31-10 on page 819), a polling method is used to wait for the end of read. Similarly, the user can configure the IER register to trigger an interrupt at the end of read. 818 32072A-AVR32-03/09 AT32UC3A3 Figure 31-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Read with DMA Yes Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Send READ_SINGLE_BLOCK command(1) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Number of words to read = (MR.BLKLEN)/4 Send READ_SINGLE_BLOCK command(1) Yes Number of words to read = 0 ? Read the SR register No Read the SR register Yes SR.XFRDONE = 0 ? SR.RXRDY = 0 ? Yes No RETURN No Read data in the RDR register Number of words to read = Number of words to read -1 RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 817). 2. This field is also accessible in the BLKR register. 819 32072A-AVR32-03/09 AT32UC3A3 In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00 value is used when padding data, otherwise 0xFF is used. Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register (DMA.DMAEN) enables DMA transfer. The following flowchart shows how to write a single block with or without use of DMA facilities (see Figure 31-11 on page 821). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (IMR). 820 32072A-AVR32-03/09 AT32UC3A3 Figure 31-11. Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) No Write using DMA Yes Write a zero in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Write a one in the DMA.DMAEN bit Write the BlockLenght in the MR.BLKLEN field(2) Send WRITE_SINGLE_BLOCK command(1) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Number of words to write = BlockLength/4 Send WRITE_SINGLE_BLOCK command(1) Enable the DMA channel X Yes Number of words to write = 0 ? Read the SR register No Read the SR register Yes SR.NOTBUSY = 0 ? SR.TXRDY = 0 ? Yes No No Write Data to transmit in the TDR register Number of words to write = Number of words to write - 1 RETURN RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 817). 2. This field is also accessible in BLKR register. 821 32072A-AVR32-03/09 AT32UC3A3 The following flowchart shows how to manage a multiple write block transfer with the DMA Controller (see Figure 31-12 on page 823). Polling or interrupt method can be used to wait for the end of write according to the contents of the IMR register. 822 32072A-AVR32-03/09 AT32UC3A3 Figure 31-12. Multiple Write Functional Flow Diagram Send SELECT/DESELECT_CARD Command(1) to select the card Send SET_BLOCKLEN command(1) Write a zero in the DMA.DMAEN bit Write the block lenght in the MR.BLKLEN field(2) Write the block count in the BLKR.BCNT field (if necessary) Configure the DMA channel X write the Data Adress in the DMA Controller write the (MR.BLKLEN)/4 for Transfer Size in the DMA Controller Send WRITE_MULTIPLE_BLOCK command(1) Enable the DMA channel X Read the SR register Yes SR.BLKE = 0 ? No Send STOP_TRANSMISSION command(1) Yes SR.NOTBUSY = 0 ? No RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 817). 2. This field is also accessible in BLKR register. 823 32072A-AVR32-03/09 AT32UC3A3 31.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Configure the DMA Channel in the DMA Controller. 5. Write the DMA register with the following fields: - Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET). - Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE). - Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE). 7. Issue a WRITE_SINGLE_BLOCK command. 8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set. 31.6.4.2 READ_SINGLE_BLOCK operation using DMA Controller 1. Wait until the current command execution has successfully terminated. d. Check that the SR.XFRDONE bit is set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Configure the DMA Channel in the DMA Controller. 5. Write the DMA register with the following fields: - Write zero to the DMA.OFFSET field. - Write the DMA.CHKSIZE field. - Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a READ_SINGLE_BLOCK command. 8. Wait for SR.DMADONE bit is set. 31.6.4.3 WRITE_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.XFRDONE bit is set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one block of data. 5. Program the DMA register with the following fields: - Write the dma_offset in the DMA.OFFSET field. - Write the DMA.CHKSIZE field. - Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a WRITE_MULTIPLE_BLOCK command. 8. Wait for DMA chained buffer transfer complete interrupt. 824 32072A-AVR32-03/09 AT32UC3A3 31.6.4.4 READ_MULTIPLE_BLOCK 1. Wait until the current command execution has successfully terminated. a. Check that the SR.CMDRDY and the SR.NOTBUSY are set. 2. Write the block length in the card. This value defines the value block_lenght. 3. Write the MR.BLKLEN with block_lenght value. 4. Program the DMA Controller to use a list of descriptors. 5. Write the DMA register with the following fields: - Write zero to the DMA.OFFSET. - Write the DMA.CHKSIZE. - Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI. 6. Write a one to the IER.DMADONE bit. 7. Issue a READ_MULTIPLE_BLOCK command. 8. Wait for DMA end of chained buffer transfer interrupt. 31.6.5 SD/SDIO Card Operation The MCI allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and more. SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD/SDIO Card communication is based on a nine-pin interface (Clock, Command, four Data and three Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the MultiMedia Card is the initialization process. The SD/SDIO Card Register (SDCR) allows selection of the Card Slot (SDCSEL) and the data bus width (SDCBUS). The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT[0] for data transfer. After initialization, the host can change the bus width (number of active data lines). 31.6.5.1 SDIO Data Transfer Type SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The CMDR.TRTYP field allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the BLKR register. In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode. 825 32072A-AVR32-03/09 AT32UC3A3 An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD). 31.6.5.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card's interrupt to the host. An SDIO interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regardless of the currently selected slot. 31.6.6 CE-ATA Operation CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands: * GO_IDLE_STATE (CMD0): used for hard reset. * STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted. * FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit access only. * RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers. * RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command. CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices. 31.6.6.1 Executing an ATA Polling Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of DATA. 2. Read the ATA status register until DRQ is set. 3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 4. Read the ATA status register until DRQ && BSY are set to 0. 31.6.6.2 Executing an ATA Interrupt Command 1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of DATA with the IEN field written to zero to enable the command completion signal in the device. 2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 3. Wait for Completion Signal Received Interrupt. 31.6.6.3 Aborting an ATA Command If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid potential collision on the command line. The Special Command field of 826 32072A-AVR32-03/09 AT32UC3A3 CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal Disable Command. 31.6.6.4 CE-ATA Error Recovery Several methods of ATA command failure may occur, including: * No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60). * CRC is invalid for an MMC command or response. * CRC16 is invalid for an MMC data packet. * ATA Status register reflects an error by setting the ERR bit to one. * The command completion signal does not arrive within a host specified time out period. Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for each error event. The recommended error recovery procedure after a time-out is: * Issue the command completion signal disable if IEN was cleared to zero and the RW_MULTIPLE_BLOCK (CMD61) response has been received. * Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response. * Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the error recovery procedure does not work as expected or there is another time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states. Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA command itself failed implying that the device could not complete the action requested, however, there was no communication or protocol failure. After the device signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command. 31.6.7 31.6.7.1 MCI Transfer Done Timings Definition The SR.XFRDONE bit indicates exactly when the read or write sequence is finished. 31.6.7.2 Read Access During a read access, the SR.XFRDONE bit behaves as shown in Figure 31-13 on page 828. 827 32072A-AVR32-03/09 AT32UC3A3 Figure 31-13. SR.XFRDONE During a Read Access CMD line MCI read CMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit lafter the end of the card response. Data 1st Block Not busy flag Last Block XFRDONE flag 31.6.7.3 Write Access During a write access, the SR.XFRDONE bit behaves as shown in Figure 31-14 on page 828. Figure 31-14. SR.XFRDONE During a Write Access CMD line MCI writeCMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit lafter the end of the card response. D0 1st Block Data bus - D0 1st Block Not busy flag Last Block Last Block D0 is tied by the card D0 is released XFRDONE flag 828 32072A-AVR32-03/09 AT32UC3A3 31.7 User Interface MCI Register Memory Map Register Control Register Mode Register Data Time-out Register SD/SDIO Card Register Argument Register Command Register Block Register Completion Signal Time-out Register Response Register Response Register Response Register Response Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register DMA Configuration Register Configuration Register Write Protection Mode Register Write Protection Status Register Version Register FIFO Memory Aperture Name CR MR DTOR SDCR ARGR CMDR BLKR CSTOR RSPR RSPR1 RSPR2 RSPR3 RDR TDR SR IER IDR IMR DMA CFG WPMR WPSR VERSION - Access Write-only Read-write Read-write Read-write Read-write Write-only Read-write Read-write Read-only Read-only Read-only Read-only Read-only Write-only Read-only Write-only Write-only Read-only Read-write Read-write Read-write Read-only Read-only Read-write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0C000025 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - (1) 0x00000000 Table 31-6. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x040 0x044 0x048 0x04C 0x050 0x054 0x0E4 0x0E8 0x0FC 0x200-0x3FFC 1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter. 829 32072A-AVR32-03/09 AT32UC3A3 31.7.1 Name: Control Register CR Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SWRST 6 - 5 IOWAITDIS 4 IOWAITEN 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN * SWRST: Software Reset Writing a one to this bit will reset the MCI interface. Writing a zero to this bit has no effect. * IOWAITDIS: SDIO Read Wait Disable Writing a one to this bit will disable the SDIO Read Wait Operation. Writing a zero to this bit has no effect. * IOWAITEN: SDIO Read Wait Enable Writing a one to this bit will enable the SDIO Read Wait Operation. Writing a zero to this bit has no effect. * PWSDIS: Power Save Mode Disable Writing a one to this bit will disable the Power Saving Mode. Writing a zero to this bit has no effect. * PWSEN: Power Save Mode Enable Writing a one to this bit and a zero to PWSDIS will enable the Power Saving Mode. Writing a one to this bit and a one to PWSDIS will disable the Power Saving Mode. Writing a zero to this bit has no effect. Warning: Before enabling this mode, the user must write a value different from 0 to the PWSDIV field. * MCIDIS: Multi-Media Interface Disable Writing a one to this bit will disable the Multi-Media Interface. Writing a zero to this bit has no effect. * MCIEN: Multi-Media Interface Enable Writing a one to this bit and a zero to MCIDIS will enable the Multi-Media Interface. Writing a one to this bit and a one to MCIDIS will disable the Multi-Media Interface. Writing a zero to this bit has no effect. 830 32072A-AVR32-03/09 AT32UC3A3 31.7.2 Name: Mode Register MR Read-write 0x004 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 19 18 17 16 15 - 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 CLKDIV 3 2 1 0 * BLKLEN[15:0]: Data Block Length This field determines the size of the data block. This field is also accessible in the BLKR register. If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00 Notes: 1. In SDIO Byte mode, BLKLEN field is not used. 2. BLKLEN should be written to one before sending the data transfer command. Otherwise, Overrun may occur even if RDPROOF bit is one. * PADV: Padding Value 0: 0x00 value is used when padding data in write transfer. 1: 0xFF value is used when padding data in write transfer. PADV is used only in manual transfer. * FBYTE: Force Byte Transfer Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. Warning: BLKLEN value depends on FBYTE. Writing a one to this bit will enable the Force Byte Transfer. Writing a zero to this bit will disable the Force Byte Transfer. * WRPROOF Write Proof Enable Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. Writing a one to this bit will enable the Write Proof mode. Writing a zero to this bit will disable the Write Proof mode. * RDPROOF Read Proof Enable Enabling Read Proof allows to stop the MCI Clock (CLK) during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. Writing a one to this bit will enable the Read Proof mode. Writing a zero to this bit will disable the Read Proof mode. 831 32072A-AVR32-03/09 AT32UC3A3 * PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN). * CLKDIV: Clock Divider The Multimedia Card Interface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)). 832 32072A-AVR32-03/09 AT32UC3A3 31.7.3 Name: Data Time-out Register DTOR Read/Write 0x008 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 DTOMUL 4 3 2 DTOCYC 1 0 These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. It is equal to (DTOCYC x Multiplier). If the data time-out defined by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error bit in the SR register (SR.DTOE) is set. * DTOMUL: Data Time-out Multiplier Multiplier is defined by DTOMUL as shown in the following table DTOMUL 0 1 2 3 4 5 6 7 Multiplier 1 16 128 256 1024 4096 65536 1048576 * DTOCYC: Data Time-out Cycle Number 833 32072A-AVR32-03/09 AT32UC3A3 31.7.4 Name: SDCard/SDIO Register SDCR Read/Write 0x00C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 SDCBUS 6 5 - 4 - 3 - 2 - 1 SDCSEL 0 * SDCBUS: SDCard/SDIO Bus Width SDCBUS 0 1 2 3 BUS WIDTH 1 bit Reserved 4 bits 8 bits * SDCSEL: SDCard/SDIO Slot SDCSEL 0 1 2 3 SDCard/SDIO Slot Slot A is selected. Slot B is selected. Reserved. Reserved. 834 32072A-AVR32-03/09 AT32UC3A3 31.7.5 Name: Argument Register ARGR Read/Write 0x010 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 ARG[31:24] 27 26 25 24 23 22 21 20 ARG[23:16] 19 18 17 16 15 14 13 12 ARG[15:8] 11 10 9 8 7 6 5 4 ARG[7:0] 3 2 1 0 * ARG[31:0]: Command Argument this field contains the argument field of the command. 835 32072A-AVR32-03/09 AT32UC3A3 31.7.6 Name: Command Register CMDR Write-only 0x014 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 ATACS 25 IOSPCMD 24 23 - 22 - 21 20 TRTYP 19 18 TRDIR 17 TRCMD 16 15 - 14 - 13 - 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 7 RSPTYP 6 5 4 3 CMDNB 2 1 0 This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified. * ATACS: ATA with Command Completion Signal Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out Register (CSTOR). Writing a zero to this bit will configure no ATA completion signal. * IOSPCMD: SDIO Special Command IOSPCMD 0 1 2 3 SDIO Special Command Type Not a SDIO Special Command SDIO Suspend Command SDIO Resume Command Reserved 836 32072A-AVR32-03/09 AT32UC3A3 * TRTYP: Transfer Type TRTYP 0 1 2 3 4 5 others Transfer Type MMC/SDCard Single Block MMC/SDCard Multiple Block MMC Stream Reserved SDIO Byte SDIO Block Reserved * TRDIR: Transfer Direction Writing a zero to this bit will configure the transfer direction as write transfer. Writing a one to this bit will configure the transfer direction as read transfer. * TRCMD: Transfer Command TRCMD 0 1 2 3 Transfer Type No data transfer Start data transfer Stop data transfer Reserved * MAXLAT: Max Latency for Command to Response Writing a zero to this bit will configure a 5-cycle max latency. Writing a one to this bit will configure a 64-cycle max latency. * OPDCMD: Open Drain Command Writing a zero to this bit will configure the push-pull command. Writing a one to this bit will configure the open-drain command. * SPCMD: Special Command SPCMD 0 1 2 Command Not a special CMD. Initialization CMD: 74 clock cycles for initialization sequence. Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Interrupt command: Corresponds to the Interrupt Mode (CMD40). Interrupt response: Corresponds to the Interrupt Mode (CMD40). Reserved 3 4 5 others 837 32072A-AVR32-03/09 AT32UC3A3 * RSPTYP: Response Type RSP 0 1 2 3 Response Type No response. 48-bit response. 136-bit response. R1b response type * CMDNB: Command Number The Command Number to transmit. 838 32072A-AVR32-03/09 AT32UC3A3 31.7.7 Name: Block Register BLKR Read/Write 0x018 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 BLKLEN[15:8] 23 22 21 20 BLKLEN[7:0] 19 18 17 16 15 14 13 12 BCNT[15:8] 11 10 9 8 7 6 5 4 BCNT[7:0] 3 2 1 0 * BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MR register. If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00 1. In SDIO Byte mode, BLKLEN field is not used. 2. BLKLEN should be specified before sending the data transfer command. Otherwise, Overrun may occur (even if MR.RDPROOF bit is set). * BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by CMDR.TRTYP field: TRTYP 0 2 3 Others Type of Transfer MMC/SDCard Multiple Block SDIO Byte SDIO Block BCNT Authorized Values From 1 to 65535: Value 0 corresponds to an infinite block transfer. From 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer. Values from 0x200 to 0xFFFF are forbidden. From 1 to 511 blocks: Value 0 corresponds to an infinite block transfer. Values from 0x200 to 0xFFFF are forbidden. Reserved. Notes: Warning: In SDIO Byte and Block modes, writing to the seven last bits of BCNT field is forbidden and may lead to unpredictable results. 839 32072A-AVR32-03/09 AT32UC3A3 31.7.8 Name: Completion Signal Time-out Register CSTOR Read-write 0x01C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 CSTOMUL 4 3 2 CSTOCYC 1 0 These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its value is calculated by (CSTOCYC x Multiplier). These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal. If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the SR register (SR.CSTOE) is set. * CSTOMUL: Completion Signal Time-out Multiplier Multiplier is defined by CSTOMUL as shown in the following table: CSTOMUL 0 1 2 3 4 5 6 7 Multiplier 1 16 128 256 1024 4096 65536 1048576 * CSTOCYC: Completion Signal Time-out Cycle Number 840 32072A-AVR32-03/09 AT32UC3A3 31.7.9 Name: Response Register n RSPRn Read-only 0x020 + 0*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 RSP[31:24] 27 26 25 24 23 22 21 20 RSP[23:16] 19 18 17 16 15 14 13 12 RSP[15:8] 11 10 9 8 7 6 5 4 RSP[7:0] 3 2 1 0 * RSP[31:0]: Response The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04). N depends on the size of the response. 841 32072A-AVR32-03/09 AT32UC3A3 31.7.10 Name: Receive Data Register RDR Read-only 0x030 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA[31:0]: Data to Read The last data received. 842 32072A-AVR32-03/09 AT32UC3A3 31.7.11 Name: Transmit Data Register TDR Write-only 0x034 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:8] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA[31:0]: Data to Write The data to send. 843 32072A-AVR32-03/09 AT32UC3A3 31.7.12 Name: Status Register SR Read-only 0x040 0x0C000025 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 - 28 - 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY * UNRE: Underrun Error This bit is set when at least one eight-bit data has been sent without valid information (not written). This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register (CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one. * OVRE: Overrun Error This bit is set when at least one 8-bit received data has been lost (not read). This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when reading the SR register if CFG.FERRCTRL is one. * XFRDONE: Transfer Done This bit is set when the CR register is ready to operate and the data bus is in the idle state. This bit is cleared when a transfer is in progress. * FIFOEMPTY: FIFO empty This bit is set when the FIFO is empty. This bit is cleared when the FIFO contains at least one byte. * DMADONE: DMA Transfer done This bit is set when the DMA buffer transfer is completed. This bit is cleared when reading the SR register. * BLKOVRE: DMA Block Overrun Error This bit is set when a new block of data is received and the DMA controller has not started to move the current pending block. This bit is cleared when reading the SR register. * CSTOE: Completion Signal Time-out Error This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is reached. This bit is cleared when reading the SR register. * DTOE: Data Time-out Error This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached. This bit is cleared when reading the SR register. 844 32072A-AVR32-03/09 AT32UC3A3 * DCRCE: Data CRC Error This bit is set when a CRC16 error is detected in the last data block. This bit is cleared when reading the SR register. * RTOE: Response Time-out Error This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached. This bit is cleared when writing the CMDR register. * RENDE: Response End Bit Error This bit is set when the end bit of the response is not detected. This bit is cleared when writing the CMDR register. * RCRCE: Response CRC Error This bit is set when a CRC7 error is detected in the response. This bit is cleared when writing the CMDR register. * RDIRE: Response Direction Error This bit is set when the direction bit from card to host in the response is not detected. This bit is cleared when writing the CMDR register. * RINDE: Response Index Error This bit is set when a mismatch is detected between the command index sent and the response index received. This bit is cleared when writing the CMDR register. * TXBUFE: TX Buffer Empty Status This bit is set when the DMA Tx Buffer is empty. This bit is cleared when the DMA Tx Buffer is not empty. * RXBUFF: RX BUffer Full Status This bit is set when the DMA Rx Buffer is full. This bit is cleared when the DMA Rx Buffer is not full. * CSRCV: CE-ATA Completion Signal Received This bit is set when the device issues a command completion signal on the command line. This bit is cleared when reading the SR register. * SDIOWAIT: SDIO Read Wait Operation Status This bit is set when the data bus has entered IO wait state. This bit is cleared when normal bus operation. * SDIOIRQB: SDIO Interrupt for Slot B This bit is cleared when reading the SR register. This bit is set when a SDIO interrupt on Slot B occurs. * SDIOIRQA: SDIO Interrupt for Slot A This bit is set when a SDIO interrupt on Slot A occurs. This bit is cleared when reading the SR register. * ENDTX: End of RX Buffer This bit is set when the DMA Controller transmission is finished. This bit is cleared when the DMA Controller transmission is not finished. * ENDRX: End of RX Buffer This bit is set when the DMA Controller reception is finished. This bit is cleared when the DMA Controller reception is not finished. * NOTBUSY: MCI Not Busy This bit must be used only for write operations. A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. The NOTBUSY bit allows to deal with these different states. 1: MCI is ready for new data transfer. 0: MCI is not ready for new data transfer. This bit is cleared at the end of the card response. 845 32072A-AVR32-03/09 AT32UC3A3 This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. DTIP: Data Transfer in Progress This bit is set when the current data transfer is in progress. This bit is cleared at the end of the CRC16 calculation 1: The current data transfer is still in progress. 0: No data transfer in progress. BLKE: Data Block Ended This bit must be used only for Write Operations. This bit is set when a data block transfer has ended. This bit is cleared when reading SR. 1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status. 0: A data block transfer is not yet finished. Refer to the MMC or SD Specification for more details concerning the CRC Status. TXRDY: Transmit Ready This bit is set when the last data written in the TDR register has been transferred. This bit is cleared the last data written in the TDR register has not yet been transferred. RXRDY: Receiver Ready This bit is set when the data has been received since the last read of the RDR register. This bit is cleared when the data has not yet been received since the last read of the RDR register. CMDRDY: Command Ready This bit is set when the last command has been sent. This bit is cleared when writing the CMDR register * * * * * 846 32072A-AVR32-03/09 AT32UC3A3 31.7.13 Name: Interrupt Enable Register IER Write-only 0x044 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 - 28 - 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 847 32072A-AVR32-03/09 AT32UC3A3 31.7.14 Name: Interrupt Disable Register IDR Write-only 0x048 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 - 28 - 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 848 32072A-AVR32-03/09 AT32UC3A3 31.7.15 Name: Interrupt Mask Register IMR Read-only 0x04C 0x00000000 Access Type: Offset: Reset Value: 31 UNRE 30 OVRE 29 - 28 - 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFF 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 - 10 - 9 SDIOIRQB 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 849 32072A-AVR32-03/09 AT32UC3A3 31.7.16 Name: DMA Configuration Register DMA Read/Write 0x050 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 DAMEN 7 - 6 5 CHKSIZE 4 3 - 2 - 1 OFFSET 0 * DMAEN: DMA Hardware Handshaking Enable 1: DMA Interface is enabled. 0: DMA interface is disabled. To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed. To avoid data losses, the DMA register should be initialized before sending the data transfer command. This is also illustrated in Figure 31-10 on page 819 or Figure 31-11 on page 821 * CHKSIZE: DMA Channel Read and Write Chunk Size The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted. CHKSIZE value 0 1 2 3 4 others Number of data transferred 1 4 8 16 32 Only available if FIFO_SIZE>= 16 bytes Only available if FIFO_SIZE>= 32 bytes Only available if FIFO_SIZE>= 64 bytes Only available if FIFO_SIZE>= 128 bytes Only available if FIFO_SIZE>= 256 bytes Reserved * OFFSET: DMA Write Buffer Offset This field indicates the number of discarded bytes when the DMA writes the first word of the transfer. 850 32072A-AVR32-03/09 AT32UC3A3 31.7.17 Name: Configuration Register CFG Read/Write 0x054 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 LSYNC 11 - 10 - 9 - 8 HSMODE 7 - 6 - 5 - 4 FERRCTRL 3 - 2 - 1 - 0 FIFOMODE * LSYNC: Synchronize on the last block 1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be different from zero) 0: The pending command is sent at the end of the current data block. This register needs to configured before sending the data transfer command. * HSMODE: High Speed Mode 1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers. 0: Default bus timing mode. * FERRCTRL: Flow Error bit reset control mode 1: When an underflow/overflow condition bit is set, reading SR resets the bit. 0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit. * FIFOMODE: MCI Internal FIFO control mode 1: A write transfer starts as soon as one data is written into the FIFO. 0: A write transfer starts when a sufficient amount of data is written into the FIFO. When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfer starts as soon as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the internal FIFO. 851 32072A-AVR32-03/09 AT32UC3A3 31.7.18 Name: Write Protect Mode Register WPMR Read/Write 0x0E4 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 WPKEY[23:16] 23 22 21 20 WPKEY[15:8] 19 18 17 16 15 14 13 12 WPKEY[7:0] 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WPEN * WPKEY[23:0]: Write Protection Key password This field should be written at value 0x4D4349 (ASCII code for "MCI"). Writing any other value in this field has no effect. * WPEN: Write Protection Enable 1: This bit enables the Write Protection if WPKEY corresponds. 0: This bit disables the Write Protection if WPKEY corresponds. 852 32072A-AVR32-03/09 AT32UC3A3 31.7.19 Name: Write Protect Status Register WPSR Read-only 0x0E8 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 WPVSRC[15:8] 15 14 13 12 11 10 9 8 WPVSRC[7:0] 7 - 6 - 5 - 4 - 3 2 WPVS 1 0 * WPVSRC[15:0]: Write Protection Violation Source This field contains address where the violation access occurs. * WPVS: Write Protection Violation Status WPVS 0 1 2 3 others Definition No Write Protection Violation occurred since the last read of this register (WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) Software reset had been performed while Write Protection was enabled (since the last read). Both Write Protection violation and software reset with Write Protection enabled had occurred since the last read. Reserved 853 32072A-AVR32-03/09 AT32UC3A3 31.7.20 Name: Access: Offset: Reset Value: Version Register VERSION Read-only 0x0FC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 17 VARIANT 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION: Version Number Version number of the module. No functionality associate 854 32072A-AVR32-03/09 AT32UC3A3 31.7.21 Name: Access: Offset: Reset Value: FIFO Memory Aperture Read/Write 0x200 - 0x3FFC 0x000000000 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 * DATA[31:0]:Data to read or Data to write 855 32072A-AVR32-03/09 AT32UC3A3 31.8 Module Configuration The specific configuration for the MCI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the Power Manager section. Table 31-7. Module name MCI Module Clock Name Clock name CLK_MCI Table 31-8. Register VERSION Register Reset Values Reset Value 0x00000300 856 32072A-AVR32-03/09 AT32UC3A3 32. Advanced Encryption Standard (AES) Rev: 1.2.3.0 32.1 Features * Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) * 128-bit/192-bit/256-bit cryptographic key * 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit cryptographic key * Support of the five standard modes of operation specified in the NIST Special Publication 80038A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) 8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode Last output data mode allows optimized Message Authentication Code (MAC) generation Hardware counter measures against differential power analysis attacks Connection to DMA Controller capabilities optimizes data transfers for all operating modes * * * * 32.2 Overview The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 80038A Recommendation. It is compatible with all these modes via DMA Controller, minimizing processor intervention for large buffer transfers. The 128-bit/192-bit/256-bit key is stored in write-only four/six/eight 32-bit KEY Word Registers (KEYWnR) which are all write-only registers. The 128-bit input data and initialization vector (for some modes) are each stored in 32-bit Input Data Registers (IDATAnR) and in Initialization Vector Registers (VnR) which are all write-only registers. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the four 32-bit Output Data Registers (ODATAnR) or through the DMA Controller. 32.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 32.3.1 Power Management If the CPU enters a sleep mode that disables clocks used by the AES, the AES will stop functioning and resume operation after the system wakes up from sleep mode. 857 32072A-AVR32-03/09 AT32UC3A3 32.3.2 Clocks The clock for the AES bus interface (CLK_AES) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the AES before disabling the clock, to avoid freezing the AES in an undefined state. 32.3.3 Interrupts The AES interrupt request line is connected to the interrupt controller. Using the AES interrupt requires the interrupt controller to be programmed first. 32.4 Functional Description The AES specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The Processing Mode bit in the Mode Register (MR.CIPHER) allows selection between the encryption and the decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the KEYWnR Registers (KEYWnR). The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector, which must be writing in the Initialization Vector Registers (IVnR). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The IVRnR registers are also used in the CTR mode to set the counter value. 32.4.1 Operation Modes The AES supports the following modes of operation: * ECB: Electronic Code Book * CBC: Cipher Block Chaining * OFB: Output Feedback * CFB: Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) - CFB128 (CFB where the length of the data segment is 128 bits) * CTR: Counter The data pre-processing, post-processing and chaining for the concerned modes are automatically performed. Refer to the NIST Special Publication 800-38A Recommendation for more complete information. These modes are selected by writing the Operation Mode field in the Mode Register (MR.OPMOD). In CFB mode, five data size are possible (8 bits, 16 bits, 32 bits, 64 bits or 128 bits). 858 32072A-AVR32-03/09 AT32UC3A3 These sizes are selected by writing the Cipher Feedback Data Size field in the MR register (MR.CFDS). 32.4.2 Start Modes The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or decryption) start mode. 32.4.2.1 Manual mode The sequence is as follows: * Write the 128-bit/192-bit/256-bit key in the KEYWnR registers. * Write the initialization vector (or counter) in the IVnR registers. Note: The Initialization Vector Registers concern all modes except ECB. * Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on whether an interrupt is required or not at the end of processing. * Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR). Table 32-1. Authorized Input Data Registers IDATAnR to Write All All All All IDATA1R and IDATA2R IDATA1R IDATA1R IDATA1R All Operation Mode ECB CBC OFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CFB CTR Note: Note: In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to errors in processing. In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not allowed and may lead to errors in processing. * Write the START bit in the Control Register (CR.START) to begin the encryption or the decryption process. * When the processing completes, the DATRDY bit in the Interrupt Status Register (ISR.DATRDY) is set. * If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES is activated. * When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit is cleared. 32.4.2.2 Automatic mode The automatic mode is similar to the manual one, except that in this mode, as soon as the correct number of IDATAnR Registers is written, processing is automatically started without any action in the CR register. 859 32072A-AVR32-03/09 AT32UC3A3 32.4.2.3 DMA mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by the software during processing. In this starting mode, the type of the data transfer (byte, halfword or word) depends on the operation mode. Table 32-2. Data Transfer Type for the Different Operation Modes Data Transfer Type (DMA) word word word word word word halfword byte word Operation Mode ECB CBC OFB CFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CTR The sequence is as follows: * Write the 128-bit/192-bit/256-bit key in the KEYWnR registers. * Write the initialization vector (or counter) in the IVnR registers. Note: The Initialization Vector Registers concern all modes except ECB. * Initialize the DMA Controller with address where the data buffer to encrypt/decrypt is stored and with the address where encrypted/decrypted data must be stored. Note: Transmit and receive buffers can be identical. * Enable the DMA Controller in transmission and reception to start the processing. * The processing completion should be monitored with the DMA Controller. 32.4.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBC-MAC algorithm for example). After each end of encryption/decryption, the output data is available either on the ODATAnR registers for manual and automatic mode or at the address specified in the receive buffer pointer for DMA mode. The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in DMA mode. This data is only available on the Output Data Registers (ODATAnR). 32.4.3.1 Manual and automatic modes * When MR.LOD is zero The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read. 860 32072A-AVR32-03/09 AT32UC3A3 Figure 32-1. Manual and Automatic Modes when MR.LOD is zero Write CR.START (Manual mode) Or Write IDATAnR register(s) (Auto mode) Read ODATAnR register(s) ISR.DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot know the end of the following encryptions/decryptions. * When MR.LOD is one The ISR.DATRDY bit is cleared when at least one IDATAnR register is written, so before the start of a new transfer. No more ODATAnR register reads are necessary between consecutive encryptions/decryptions. Figure 32-2. Manual and Automatic Modes when MR.LOD is one Write CR.START(Manual mode) or Write IDATAnR register(s) (Auto mode) Write IDATAnR register(s) ISR.DATRDY Encryption or Decryption Process 32.4.3.2 DMA mode * when MR.LOD is zero The end of the encryption/decryption should be monitored with the DMA Controller. Figure 32-3. DMA Mode when MR.LOD is zero E n a b le D M A C o n tro lle r C h a n n e ls (R e c e iv e a n d T ra n s m it C h a n n e ls ) M u ltip le e n c ry p tio n o r d e c ry p tio n p ro c e s s e s D M A C o n tro lle r In te rru p t * when MR.LOD is one The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that the encryption/decryption is completed. 861 32072A-AVR32-03/09 AT32UC3A3 In this case, no receive buffers are required. The output data is only available on the ODATAnR registers. Figure 32-4. DMA Mode when MR.LOD is one Enable DMA Controller Channels (only Transmit Channel) ISR.DATRDY Multiple Encryption or Decryption Processes DMA Controller Interrupt Following table summarizes the different cases. Table 32-3. Last Output Mode Behavior versus Start Modes Manual and Automatic Modes MR.LOD = 0 MR.LOD = 1 At least one IDATAnR register must be written MR.LOD = 0 Not used At the address specified in the configuration of DMA Mode MR.LOD = 1 Managed by the DMA ISR.DATRDY bit Clearing Condition(1) Encrypted/Decrypted Data Result Location At least one ODATAnR register must be read Controller In ODATAnR registers In ODATAnR registers In ODATAnR registers DMA Controller End of Encryption/Decryption Note: ISR.DATRDY ISR.DATRDY DMA Controller Interrupt DMA Controller Interrupt then DATRDY.ISR 1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR) definition. Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results. 32.4.4 32.4.4.1 Security Features Countermeasures The AES also features hardware countermeasures that can be useful to protect data against Differential Power Analysis (DPA) attacks. These countermeasures can be enabled through the Countermeasure Type field in the MR register (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the same time, the Countermeasure Key field in the Mode Register (MR.CKEY) is correctly written (see the Mode Register (MR) description in Section 32.5.2). Note: Enabling countermeasures has an impact on the AES encryption/decryption throughput. By default, all the countermeasures are enabled. The best throughput is achieved with all the countermeasures disabled. On the other hand, the best protection is achieved with all of them enabled. 862 32072A-AVR32-03/09 AT32UC3A3 The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a new seed to be loaded in the embedded random number generator used for the different countermeasures. 32.4.4.2 Unspecified register access detection When an unspecified register access occurs, the Unspecified Register Detection Status bit in the ISR register (ISR.URAD) is set to one. Its source is then reported in the Unspecified Register Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is available through the ISR.URAT field. Several kinds of unspecified register accesses can occur when: * Writing the IDATAnR registers during the data processing in DMA mode * Reading the ODATAnR registers during data processing * Writing the MR register during data processing * Reading the ODATAnR registers during sub-keys generation * Writing the MR register during sub-keys generation * Reading an write-only register The ISR.URAD bit and the ISR.URAT field can only be reset by the Software Reset bit in the CR register (CR.SWRST). 863 32072A-AVR32-03/09 AT32UC3A3 32.5 User Interface AES Register Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Key Word 1 Register Key Word 2 Register Key Word 3 Register Key Word 4 Register Key Word 5 Register Key Word 6 Register Key Word 7 Register Key Word 8 Register Input Data 1 Register Input Data 2 Register Input Data 3 Register Input Data 4 Register Output Data 1 Register Output Data 2 Register Output Data 3 Register Output Data 4 Register Initialization Vector 1 Register Initialization Vector 2 Register Initialization Vector 3 Register Initialization Vector 4 Register Version Register Register Name CR MR IER IDR IMR ISR KEYW1R KEYW2R KEYW3R KEYW4R KEYW5R KEYW6R KEYW7R KEYW8R IDATA1R IDATA2R IDATA3R IDATA4R ODATA1R ODATA2R ODATA3R ODATA4R IV1R IV2R IV3R IV4R VR Access Write-only Read/Write Write-only Write-only Read-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Read-only Read-only Read-only Write-only Write-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000001E 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xC01F0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) Table 32-4. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0xFC Note: 1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter. 864 32072A-AVR32-03/09 AT32UC3A3 32.5.1 Name: Control Register CR Write-only 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 LOADSEED 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 SWRST 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 START * LOADSEED: Random Number Generator Seed Loading Writing a one to this bit will load a new seed in the embedded random number generator used for the different countermeasures. writing a zero to this bit has no effect. * SWRST: Software Reset Writing a one to this bit will reset the AES. writing a zero to this bit has no effect. * START: Start Processing Writing a one to this bit will start manual encryption/decryption process. writing a zero to this bit has no effect. 865 32072A-AVR32-03/09 AT32UC3A3 32.5.2 Name: Mode Register MR Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 27 26 CTYPE 25 24 23 22 CKEY 21 20 19 - 18 17 CFBS 16 15 LOD 14 13 OPMOD 12 11 KEYSIZE 10 9 SMOD 8 7 6 PROCDLY 5 4 3 - 2 - 1 - 0 CIPHER * CTYPE: Countermeasure Type CTYPE X X X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X X X Description Countermeasure type 1 is disabled Add random spurious power consumption during some configuration settings Countermeasure type 2 is disabled Add randomly 1 cycle to processing. Countermeasure type 3 is disabled Add randomly 1 cycle to processing (other version) Countermeasure type 4 is disabled Add randomly up to /13/15 cycles (for /192/256-bit key) to processing Countermeasure type 5 is disabled Add random spurious power consumption during processing (recommended with DMA access) All the countermeasures are enabled by default. CTYPE field is write-only and can only be modified if CKEY is correctly set. 866 32072A-AVR32-03/09 AT32UC3A3 * CKEY: Countermeasure Key Writing the value 0xE to this field allows the CTYPE field to be modified. Writing another value to this field has no effect. This bit always reads as zero. * CFBS: Cipher Feedback Data Size CFBS 0 1 2 3 4 Others Description 128-bit 64-bit 32-bit 16-bit 8-bit Reserved * LOD: Last Output Data Mode Writing a one to this bit will enabled the LOD mode. Writing a zero to this bit will disabled the LOD mode. These mode is described in the Table 32-3 on page 862. * OPMOD: Operation Mode OPMOD 0 1 2 3 4 Others Description ECB: Electronic Code Book mode CBC: Cipher Block Chaining mode OFB: Output Feedback mode CFB: Cipher Feedback mode CTR: Counter mode Reserved * KEYSIZE: Key Size KEYSIZE 0 1 Others Description AES Key Size is 128 bits AES Key Size is 192 bits AES Key Size is 256 bits 867 32072A-AVR32-03/09 AT32UC3A3 * SMOD: Start Mode SMOD 0 1 Description Manual mode Automatic mode DMA mode 2 * LOD = 0: The encrypted/decrypted data are available at the address specified in the configuration of DMA Controller. * LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers. Reserved 3 * PROCDLY: Processing Delay The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption with no countermeasures activated: Processing Time = 12 x ( PROCDLY + 1 ) The best performance is achieved with PROCDLY equal to 0. Writing a value to this field will update the processing time. Reading this field will give the current processing delay. * CIPHER: Processing Mode 0: Decrypts data is enabled. 1: Encrypts data is enabled. 868 32072A-AVR32-03/09 AT32UC3A3 32.5.3 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 869 32072A-AVR32-03/09 AT32UC3A3 32.5.4 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 870 32072A-AVR32-03/09 AT32UC3A3 32.5.5 Name: Interrupt Mask Register IMR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 871 32072A-AVR32-03/09 AT32UC3A3 32.5.6 Name: Interrupt Status Register ISR Read-only 0x1C 0x0000001E Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 URAT 13 12 11 - 10 - 9 - 8 URAD 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 DATRDY * URAT: Unspecified Register Access Type: URAT 0 1 2 3 4 5 Others Description The IDATAnR register during the data processing in DMA mode. The ODATAnR register read during the data processing. The MR register written during the data processing. The ODATAnR register read during the sub-keys generation. The MR register written during the sub-keys generation. Write-only register read access. Reserved Only the last Unspecified Register Access Type is available through the URAT field. This field is reset to 0 when SWRST bit in the Control Register is written to one. * URAD: Unspecified Register Access Detection Status This bit is set when at least one unspecified register access has been detected since the last software reset. This bit is cleared when SWRST bit in the Control Register is set to one. * * * * 872 32072A-AVR32-03/09 AT32UC3A3 * DATRDY: Data Ready This bit is set/clear as described in the Table 32-3 on page 862. This bit is also cleared when SWRST bit in the Control Register is set to one. 873 32072A-AVR32-03/09 AT32UC3A3 32.5.7 Name: Key Word n Register KEYWnR Write-only 0x20 +(n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 KEYWn[31:24] 23 22 21 20 19 18 17 16 KEYWn[23:16] 15 14 13 12 KEYWn[15:8] 11 10 9 8 7 6 5 4 KEYWn[7:0] 3 2 1 0 * KEYWn[31:0]: Key Word n Writing the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption in the four/six/eight 32-bit Key Word registers. KEYW1 corresponds to the first word of the key and respectively KEYW4/KEYW6/KEYW8 to the last one. This field always read as zero to prevent the key from being read by another application. 874 32072A-AVR32-03/09 AT32UC3A3 32.5.8 Name: Input Data n Register IDATAnR Write-only 0x40 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 IDATAn[31:24] 23 22 21 20 19 18 17 16 IDATAn[23:16] 15 14 13 12 IDATAn[15:8] 11 10 9 8 7 6 5 4 IDATAn[7:0] 3 2 1 0 * IDATAn[31:0]: Input Data Word n Writing the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers. IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one. This field always read as zero to prevent the input data from being read by another application. 875 32072A-AVR32-03/09 AT32UC3A3 32.5.9 Name: Output Data n Register ODATAnR Read-only 0x50 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 ODATAn[31:24] 23 22 21 20 19 18 17 16 ODATAn[23:16] 15 14 13 12 ODATAn[15:8] 11 10 9 8 7 6 5 4 ODATAn[7:0] 3 2 1 0 * ODATAn[31:0]: Output Data n Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA4 to the last one. 876 32072A-AVR32-03/09 AT32UC3A3 32.5.10 Name: Initialization Vector n Register IVnR Write-only 0x60 + (n-1)*0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 IVn[31:24] 27 26 25 24 23 22 21 20 IVn[23:16] 19 18 17 16 15 14 13 12 IVn[15:8] 11 10 9 8 7 6 5 4 IVn[7:0] 3 2 1 0 * IVn[31:0]: Initialization Vector n The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input: MODE(OPMODE. CBC,OFB, CFB CTR ECB Description initialization vector counter value not used, must not be written IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one. This field is always read as zero to prevent the Initialization Vector from being read by another application. 877 32072A-AVR32-03/09 AT32UC3A3 32.5.11 Name: Version Register VERSION Read-only 0xFC - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 * VARIANT: Variant Number Reserved. No functionality associated. * VERSION[11:0] Version number of the module. No functionality associated. 878 32072A-AVR32-03/09 AT32UC3A3 32.6 Module Configuration The specific configuration for each AES instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. Table 32-5. Module name AES Module clock name Clock name CLK_AES Table 32-6. Register VERSION Register Reset Values Reset Value 0x00000123 879 32072A-AVR32-03/09 AT32UC3A3 33. Audio Bitstream DAC (ABDAC) Rev: 1.0.1.1 33.1 Features * Digital Stereo DAC * Oversampled D/A conversion architecture - Oversampling ratio fixed 128x - FIR equalization filter - Digital interpolation filter: Comb4 - 3rd Order Sigma-Delta D/A converters * Digital bitstream outputs * Parallel interface * Connected to DMA Controller for background transfer without CPU intervention 33.2 Overview The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported, making the Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of complementary digital outputs, DATAn and DATANn, which can be connected to an external high input impedance amplifier. The Audio Bitstream DAC is compromised of two 3rd order Sigma-Delta D/A converter with an oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter (Comb4) before being input to the Sigma-Delta Modulator. In order to compensate for the pass band frequency response of the interpolation filter and flatten the overall frequency response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency response of the Equalization FIR filter and the interpolation filter is given in Figure 33-2 on page 883. The digital output bitstreams from the Sigma-Delta Modulators should be low-pass filtered to remove high frequency noise inserted by the Modulation process. The output DATAn and DATANn should be as ideal as possible before filtering, to achieve the best SNR quality. The output can be connected to a class D amplifier output stage, or it can be low pass filtered and connected to a high input impedance amplifier. A simple 1st order or higher low pass filter that filters all the frequencies above 50kHz should be adequate. 880 32072A-AVR32-03/09 AT32UC3A3 33.3 Block Diagram Figure 33-1. ABDAC Block Diagram Audio Bitstream DAC PM GCLK_ABDAC Clock Generator sample_clk bit_clk CHANNEL0[15:0] Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD DATA0 User Interface CHANNEL1[15:0] Equalization FIR COMB (INT=128) Sigma-Delta DA-MOD DATA1 33.4 I/O Lines Description I/O Lines Description Pin Description Output from Audio Bitstream DAC Channel 0 Output from Audio Bitstream DAC Channel 1 Inverted output from Audio Bitstream DAC Channel 0 Inverted output from Audio Bitstream DAC Channel 1 Type Output Output Output Output Table 33-1. Pin Name DATA0 DATA1 DATAN0 DATAN1 33.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 33.5.1 I/O Lines The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed with IO lines. Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode. 881 32072A-AVR32-03/09 AT32UC3A3 33.5.2 Clocks The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is enabled in the Power Manager. The ABDAC needs a separate clock for the D/A conversion operation. This clock, GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its frequency must as follow: f GCLK = 256 x f S For fs= 48kHz this means that the GCLK_ABDAC clock must have a frequency of 12.288MHz. 33.5.3 Interrupts The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC interrupt requires the interrupt controller to be programmed first. 33.6 33.6.1 Functional Description How to Initialize the Module In order to use the Audio Bitstream DAC the product dependencies given in Section 33.5 on page 881 must be resolved. Particular attention should be given to the configuration of clocks and I/O lines in order to ensure correct operation of the Audio Bitstream DAC. The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream DAC Control Register (CR.EN). The two 16-bit sample values for channel 0 and 1 can then be written to the least and most significant halfword of the Sample Data Register (SDR), respectively. The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be set whenever the ABDAC is ready to receive a new sample. A new sample value should be written to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writing one to the corresponding bits in the Interrupt Clear Register (ICR). The Audio Bitstream DAC can also be configured for Peripheral DMA access, in which case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. 33.6.2 Equalization Filter The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for the pass band frequency response of the sinc interpolation filter. The equalization filter makes the pass band response more flat and moves the -3dB corner a little higher. Interpolation Filter The interpolation filter interpolates from fs to 128fs. This filter is a 4thorder Cascaded IntegratorComb filter, and the basic building blocks of this filter is a comb part and an integrator part. Sigma-Delta Modulator This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to shape the noise, so that the noise is reduced in the band of interest and increased at the higher frequencies, where it can be filtered. 33.6.3 33.6.4 882 32072A-AVR32-03/09 AT32UC3A3 33.6.5 Data Format Input data is on two's complement format. 33.6.6 Data Swapping When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1 fields to be swapped. Frequency Response Figure 33-2. Frequency Response, EQ-FIR+COMB4 10 33.6.7 0 [dB ] A m p li t u d e -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 0 1 2 3 4 5 F re q u e n c y 6 [F s ] 7 8 9 x 10 10 4 33.6.8 Peripheral DMA Controller The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA Controller can be programmed to automatically transfer samples to the Audio Bitstream DAC Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new samples. This enables the Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Status Register (ISR) or using interrupts. See the Peripheral DMA Controller documentation for details on how to setup Peripheral DMA transfers. 883 32072A-AVR32-03/09 AT32UC3A3 33.7 User Interface ABDAC Register Memory Map Register Sample Data Register Control Register Interrupt Mask Register Interrupt Enable Register Interrupt Disable Register Interrupt Clear Register Interrupt Status Register Register Name SDR CR IMR IER IDR ICR ISR Access Read/Write Read/Write Read-only Write-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 33-2. Offset 0x00 0x08 0x0C 0x10 0x14 0x18 0x1C 884 32072A-AVR32-03/09 AT32UC3A3 33.7.1 Name: Sample Data Register SDR Read/Write 0x00 0x00000000 30 29 28 27 CHANNEL1[15:8] 20 19 CHANNEL1[7:0] 12 11 CHANNEL0[15:8] 4 3 CHANNEL0[7:0] 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 * CHANNEL1: Sample Data for Channel 1 signed 16-bit Sample Data for channel 1. * CHANNEL0: Signed 16-bit Sample Data for Channel 0 signed 16-bit Sample Data for channel 0. 885 32072A-AVR32-03/09 AT32UC3A3 33.7.2 Name: Control Register CR Read/Write 0x08 0x00000000 30 SWAP 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 EN 23 15 7 - * EN: Enable Audio Bitstream DAC 1: The module is enabled. 0: The module is disabled. * SWAP: Swap Channels 1: The swap of CHANNEL0 and CHANNEL1 samples is enabled. 0: The swap of CHANNEL0 and CHANNEL1 samples is disabled. 886 32072A-AVR32-03/09 AT32UC3A3 33.7.3 Name: Interrupt Mask Register IMR Read-only 0x0C 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 887 32072A-AVR32-03/09 AT32UC3A3 33.7.4 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 888 32072A-AVR32-03/09 AT32UC3A3 33.7.5 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 889 32072A-AVR32-03/09 AT32UC3A3 33.7.6 Name: Interrupt Clear Register ICR Write-only 0x18 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 890 32072A-AVR32-03/09 AT32UC3A3 33.7.7 Name: Interrupt Status Register ISR Read-only 0x1C 0x00000000 30 22 14 6 29 TXREADY 21 13 5 28 UNDERRUN 20 12 4 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 - Access Type: Offset: Reset Value: 31 23 15 7 - * TXREADY: TX Ready Interrupt Status This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR. This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR. * UNDERRUN: Underrun Interrupt Status This bit is cleared when no Audio Bitstream DAC Underrun has occurred since the last time this bit has been cleared (by reset or by writing in ICR). This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit has been cleared (by reset or by writing in ICR). 891 32072A-AVR32-03/09 AT32UC3A3 34. Programming and Debugging 34.1 Overview General description of programming and debug features, block diagram and introduction of main concepts. 34.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG port through a bus master module, which also handles synchronization between the debugger and SAB clocks. When accessing the SAB through the debugger there are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. Debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. This ratio can be measured with debug protocol specific instructions. The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. 34.2.1 SAB address map The Service Access Bus (SAB) gives the user access to the internal address space and other features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32 LSBs are decoded within the slave's address space. The SAB slaves are shown in Table 34-1 on page 892. Table 34-1. Slave SAB Slaves, addresses and descriptions. Address [35:32] 0x0 0x1 0x4 0x5 0x6 Other Description Intentionally unallocated OCD registers HSB memory space, as seen by the CPU Alternative mapping for HSB space, for compatibility with other AVR32 devices. Memory Service Unit registers Unused Unallocated OCD HSB HSB Memory Service Unit Reserved 34.2.2 SAB security restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 892 32072A-AVR32-03/09 AT32UC3A3 34.2.2.1 Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure. These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance. Table 34-2. SAB Security measures. Control Location FLASHC security bit set FLASHC UPROT + security bit set Description Programming and debugging not possible, very restricted access. Restricts all access except parts of the flash and the flash controller for programming user code. Debugging is not possible unless an OS running from the secure part of the flash supports it. Security measure Security bit User code programming Below follows a more in depth description of what locations are accessible when the security measures are active. Table 34-3. Name Security bit SAB restrictions Address start 0x100000110 0x580800000 Address end 0x100000118 0x581000000 Access Read/Write Read Blocked OCD DCCPU, OCD DCEMU, OCD DCSR User page Other accesses Table 34-4. Name User code programming SAB restrictions Address start 0x100000110 0x580800000 0x5FFFE0000 0x580000000 + BOOTPROT size Address end 0x100000118 0x581000000 0x5FFFE0400 Access Read/Write Read Read/Write OCD DCCPU, OCD DCEMU, OCD DCSR User page FLASHC PB interface FLASH pages outside BOOTPROT Other accesses 0x580000000 + Flash size - Read/Write Blocked 893 32072A-AVR32-03/09 AT32UC3A3 34.3 On-Chip Debug (OCD) Rev: 1.4.2.1 34.3.1 Features * * * * * * * * Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ JTAG access to all on-chip debug functions Advanced program, data, ownership, and watchpoint trace supported NanoTrace JTAG-based trace access Auxiliary port for high-speed trace information Hardware support for 6 program and 2 data breakpoints Unlimited number of software breakpoints supported Automatic CRC check of memory regions 34.3.2 Overview Debugging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The user accesses this through an external debug tool which connects to the JTAG port and the Auxiliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based debugger is sufficient for basic debugging. The debug system is based on the Nexus 2.0 standard, class 2+, which includes: * Basic run-time control * Program breakpoints * Data breakpoints * Program trace * Ownership trace * Data trace In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful OCD features, such as: * Debug Communication Channel between CPU and JTAG * Run-time PC monitoring * CRC checking * NanoTrace * Software Quality Assurance (SQA) support The OCD features are controlled by OCD registers, which can be accessed by JTAG when the NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical Reference Manual. 894 32072A-AVR32-03/09 AT32UC3A3 34.3.3 Block Diagram Figure 34-1. On-Chip Debug Block Diagram JTAG JTAG AUX On-Chip Debug Service Access Bus Memory Service Unit Transmit Queue Watchpoints Debug PC Debug Instruction Program Trace Data Trace Ownership Trace Breakpoints CPU Internal SRAM HSB Bus Matrix Memories and peripherals 34.3.4 JTAG-based Debug Features A debugger can control all OCD features by writing OCD registers over the JTAG interface. Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be used. A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector as described in the AVR32UC Technical Reference Manual. 895 32072A-AVR32-03/09 AT32UC3A3 Figure 34-2. JTAG-based Debugger PC JTAG-based debug tool 10-pin IDC JTAG AVR32 34.3.4.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange data between the CPU and the JTAG master, both runtime as well as in debug mode. breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system. This is accomplished by breakpoints, of which many types are available: * Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU immediately. * Program breakpoints halt the CPU when a specific address in the program is executed. * Data breakpoints halt the CPU when a specific memory address is read or written, allowing variables to be watched. * Software breakpoints halt the CPU when the breakpoint instruction is executed. When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is set. This is a privileged mode with dedicated return address and return status registers. All privileged instructions are permitted. Debug mode can be entered as either OCD mode, running instructions from JTAG, or monitor mode, running instructions from program memory. 34.3.4.2 896 32072A-AVR32-03/09 AT32UC3A3 34.3.4.3 OCD mode When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g. read out the register file by issuing mtdr instructions to the CPU, writing each register to the Debug Communication Channel OCD registers. 34.3.4.4 monitor mode Since the OCD registers are directly accessible by the CPU, it is possible to build a softwarebased debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development Control register causes the CPU to enter monitor mode instead of OCD mode when a breakpoint triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by JTAG. program counter monitoring Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current PC value. However, the AT32UC3A3 provides a Debug Program Counter OCD register, where the debugger can continuously read the current PC without affecting the CPU. This allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization. 34.3.4.5 34.3.5 Memory Service Unit The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is controlled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG command. Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The OCD will then read out each word in the specified memory block and report the CRC32-value in an OCD register. NanoTrace The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace data is output to memory instead of the AUX port. This allows the trace data to be extracted by JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must write MSU registers to configure the address and size of the memory block to be used for NanoTrace. The NanoTrace buffer can be anywhere in the physical address range, including internal and external RAM, through an EBI, if present. This area may not be used by the application running on the CPU. 34.3.5.1 34.3.5.2 34.3.6 AUX-based Debug Features Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the CPU. Additionally, Event In and Event Out pins allow external events to be correlated with the program flow. The AUX port contains a number of pins, as shown in Table 34-5 on page 898. These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before the debug session starts. The AUX port is mapped to two different locations, selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. 897 32072A-AVR32-03/09 AT32UC3A3 Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mictor-38 connector, as described in the AVR32UC Technical Reference manual. This connector includes the JTAG signals and the RESET_N pin, giving full access to the programming and debug features in the device. Table 34-5. Signal MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Auxiliary Port Signals Direction Output Output Output Input Output Description Trace data output clock Trace data output Trace frame control Event In Event Out Figure 34-3. AUX+JTAG based Debugger PC T ra c e b u ffe r AU X+JTA G d e b u g to o l M ic to r 3 8 AUX h ig h s p e e d JTA G AVR 32 34.3.6.1 trace operation Trace features are enabled by writing OCD registers by JTAG. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and are output on the AUX port one frame at a time. 898 32072A-AVR32-03/09 AT32UC3A3 The trace features can be configured to be very selective, to reduce the bandwidth on the AUX port. In case the transmit queue overflows, error messages are produced to indicate loss of data. The transmit queue module can optionally be configured to halt the CPU when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 34.3.6.2 program trace Program trace allows the debugger to continuously monitor the program execution in the CPU. Program trace messages are generated for every branch in the program, and contains compressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address. data trace Data trace outputs a message every time a specific location is read or written. The message contains information about the type (read/write) and size of the access, as well as the address and data of the accessed location. The AT32UC3A3 contains two data trace channels, each of which are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 34.3.6.4 ownership trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch. When the O/S activates a process, it will write the process ID number to an OCD register, which produces an Ownership Trace Message, allowing the debugger to switch context for the subsequent program and data trace messages. As the use of this feature depends on the software running on the CPU, it can also be used to extract other types of information from the system. watchpoint messages The breakpoint modules normally used to generate program and data breakpoints can also be used to generate Watchpoint messages, allowing a debugger to monitor program and data events without halting the CPU. Watchpoints can be enabled independently of breakpoints, so a breakpoint module can optionally halt the CPU when the trigger condition occurs. Data trace modules can also be configured to produce watchpoint messages instead of regular data trace messages. Event In and Event Out pins The AUX port also contains an Event In pin (EVTI_N) and an Event Out pin (EVTO_N). EVTI_N can be used to trigger a breakpoint when an external event occurs. It can also be used to trigger specific program and data trace synchronization messages, allowing an external event to be correlated to the program flow. When the CPU enters debug mode, a Debug Status message is transmitted on the trace port. All trace messages can be timestamped when they are received by the debug tool. However, due to the latency of the transmit queue buffering, the timestamp will not be 100% accurate. To improve this, EVTO_N can toggle every time a message is inserted into the transmit queue, allowing trace messages to be timestamped precisely. EVTO_N can also toggle when a breakpoint module triggers, or when the CPU enters debug mode, for any reason. This can be used to measure precisely when the respective internal event occurs. 34.3.6.3 34.3.6.5 34.3.6.6 899 32072A-AVR32-03/09 AT32UC3A3 34.3.6.7 Software Quality Analysis (SQA) Software Quality Analysis (SQA) deals with two important issues regarding embedded software development. Code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. Performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized. Program trace must be used to accomplish these tasks without instrumenting (altering) the code to be examined. However, traditional program trace cannot reconstruct the current PC value without correlating the trace information with the source code, which cannot be done on-the-fly. This limits program trace to a relatively short time segment, determined by the size of the trace buffer in the debug tool. The OCD system in AT32UC3A3 extends program trace with SQA capabilities, allowing the debug tool to reconstruct the PC value on-the-fly. Code coverage and performance analysis can thus be reported for an unlimited execution sequence. 900 32072A-AVR32-03/09 AT32UC3A3 34.3.7 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the GPIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXC register (AXO and AXS bitfileds). For details, see the AVR32UC Technical Reference Manual. Table 34-6. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] Nexus OCD AUX port connections AXO=0 & AXS=0 PB05 PA00 PA01 PA03 PA16 PA13 PA12 PB06 PB07 PA10 PA11 AXO=0 & AXS=1 or AXO=1 PA08 PX56 PX57 PX58 PA24 PA23 PA22 PB06 PA00 PA07 PX55 AXO=0 & AXS=2 PX00 PX06 PX05 PX04 PX03 PX02 PX01 PB06 PB09 PX08 PX07 901 32072A-AVR32-03/09 AT32UC3A3 34.4 JTAG and Boundary Scan (JTAG) Rev.: 2.0.0.3 34.4.1 Features * * * * IEEE1149.1 compliant JTAG Interface Boundary-Scan Chain for board-level testing Direct memory access and programming capabilities through JTAG interface On-Chip Debug access in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) 34.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary scan support for board- level testing. The JTAG interface supports memory access, programming capabilities, and On-Chip Debug access. Figure 34-4 on page 903 shows how the JTAG is connected in an AVR32 device. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift register) between the TDI-input and TDO-output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The ID Register, Bypass Register, and the Boundary-Scan Chain are the Data Registers used for board-level testing. The Reset Register can be used to keep the device reset during test or programming. The Service Access Bus (SAB) interface contains address and data registers for the Service Access Bus, which gives access to On-Chip Debug, programming, and other functions in the device. The SAB offers several modes of access to the address and data registers, as discussed in Section 34.4.10. Section 34.4.11 lists the supported JTAG instructions, with references to the description in this document. 902 32072A-AVR32-03/09 AT32UC3A3 34.4.3 Block Diagram Figure 34-4. JTAG and Boundary Scan Access JTA G TM S TCK m a s te r TDO TDI A V R 3 2 d e v ic e TAP C o n tr o lle r B o u n d a r y s c a n e n a b le TCK TM S TDI TDO JTAG TAP In s tr u c tio n R e g is te r S c a n e n a b le D a ta r e g is te r s c a n e n a b le In s tr u c tio n R e g is te r TM S TCK TDO TDI JTAG d a ta r e g is te r s JTA G d e v ic e B ypass ID R e g is te r R eset R e g is te r ... S e r v ic e A c c e s s B u s in te r fa c e OCD CPU RAM S e r v ic e A ccess Bus R e g is te r s M e m o r y S e r v ic e U n it M e m o r ie s a n d p e r ip h e r a ls 34.4.4 I/O Lines Description I/O Lines Description Pin Description Test Clock Input. Fully asynchronous to system clock frequency. Test Mode Select, sampled on rising TCK Test Data In, sampled on rising TCK. Test Data Out, driven on falling TCK. Type Input Input Input Output Table 34-7. Pin Name TCK TMS TDI TDO 34.4.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. Clocks The JTAG Interface is using the external TCK pin as clock source. This clock must be provided by the user. 34.4.5.1 32072A-AVR32-03/09 Pins and analog blocks Boundary Scan Chain High Speed Bus 903 AT32UC3A3 34.4.6 JTAG Interface The JTAG Interface is accessed through the dedicated JTAG pins shown in Table 34-7 on page 903. The TMS control line navigates the TAP controller, as shown in Figure 34-5 on page 905. The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data is scanned into the selected instruction or data register on TDI, and out of the register on TDO, in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is highZ in other states than Shift-IR and Shift-DR. The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions defined by the JTAG standard are supported, as described in Section 34.4.12, as well as a number of AVR32-specific private JTAG instructions described in Section 34.4.13. Each instruction selects a specific data register for the Shift-DR path, as described for each instruction. 904 32072A-AVR32-03/09 AT32UC3A3 Figure 34-5. TAP Controller State Diagram 1 Test-LogicReset 0 1 1 Select-DR Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 1 Update-DR 0 1 0 1 0 0 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 1 0 0 Run-Test/ Idle 1 1 905 32072A-AVR32-03/09 AT32UC3A3 34.4.7 How to Initialize the Module Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied at the start of a JTAG session to bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the RunTest/Idle state, which is the starting point for JTAG operations. Typical Sequence Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG Interface is: Scanning in JTAG Instruction At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register (Shift-IR) state. While in this state, shift the 5 bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. 34.4.8 34.4.8.1 Figure 34-6. Scanning in JTAG Instruction TCK TAP State TMS TDI TDO 34.4.8.2 TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI Instruction ImplDefined Scanning in/out Data At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register (Shift-DR) state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers. 34.4.9 Boundary-Scan The Boundary-Scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by 906 32072A-AVR32-03/09 AT32UC3A3 the TDI/TDO signals to form a long shift register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-Scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the 4 TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR32 device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. Entering reset, the outputs of any Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESETn pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG Interface for Boundary-Scan, the JTAG TCK clock is independent of the internal chip clock, which is not required to run. 34.4.10 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the aWire through a bus master module, which also handles synchronization between the aWire and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 34.4.10.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any 36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruction for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These instructions require two passes through the Shift-DR TAP state: one for the address and control information, and one for data. Block Transfer To increase the transfer rate, consecutive memory accesses can be accomplished by the MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for data transfer only. The address is automatically incremented according to the size of the last SAB transfer. 34.4.10.2 907 32072A-AVR32-03/09 AT32UC3A3 34.4.10.3 Canceling a SAB Access It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid hanging the bus due to an extremely slow slave. 34.4.10.4 Busy Reporting As the time taken to perform an access may vary depending on system activity and current chip frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates whether a delay needs to be inserted, or an operation needs to be repeated in order to be successful. If a new access is requested while the SAB is busy, the request is ignored. The SAB becomes busy when: * Entering Update-DR in the address phase of any read operation, e.g. after scanning in a NEXUS_ACCESS address with the read bit set. * Entering Update-DR in the data phase of any write operation, e.g. after scanning in data for a NEXUS_ACCESS write. * Entering Update-DR during a MEMORY_BLOCK_ACCESS. * Entering Update-DR after scanning in a counter value for SYNC. * Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the previous access was a read and data was scanned after scanning the address. The SAB becomes ready again when: * A read or write operation completes. * A SYNC countdown completed. * A operation is cancelled by the CANCEL_ACCESS instruction. What to do if the busy bit is set: * During Shift-IR: The new instruction is selected, but the previous operation has not yet completed and will continue (unless the new instruction is CANCEL_ACCESS). You may continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. * During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. * During Shift-DR of read data: The read data are invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears. * During Shift-DR of write data: The write data are ignored. The SAB stays in data mode. Repeat scanning until the busy bit clears. 34.4.10.5 Error Reporting The Service Access Bus may not be able to complete all accesses as requested. This may be because the address is invalid, the addressed area is read-only or cannot handle byte/halfword accesses, or because the chip is set in a protected mode where only limited accesses are allowed. The error bit is updated when an access completes, and is cleared when a new access starts. What to do if the error bit is set: 908 32072A-AVR32-03/09 AT32UC3A3 * During Shift-IR: The new instruction is selected. The last operation performed using the old instruction did not complete successfully. * During Shift-DR of an address: The previous operation failed. The new address is accepted. If the read bit is set, a read operation is started. * During Shift-DR of read data: The read operation failed, and the read data are invalid. * During Shift-DR of write data: The previous write operation failed. The new data are accepted and a write operation started. This should only occur during block writes or stream writes. No error can occur between scanning a write address and the following write data. * While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not have actually completed. 34.4.11 JTAG Instruction Summary The implemented JTAG instructions in the AVR32 are shown in the table below. JTAG Instruction Summary Instruction IDCODE SAMPLE_PRELOAD EXTEST INTEST CLAMP AVR_RESET CHIP_ERASE NEXUS_ACCESS MEMORY_WORD_ACCESS MEMORY_BLOCK_ACCESS CANCEL_ACCESS MEMORY_SERVICE MEMORY_SIZED_ACCESS SYNC HALT BYPASS N/A Description Select the 32-bit ID register as data register. Take a snapshot of external pin values without affecting system operation. Select boundary scan chain as data register for testing circuitry external to the device. Select boundary scan chain for internal testing of the device. Bypass device through Bypass register, while driving outputs from boundary scan register. Apply or remove a static reset to the device Erase the device Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Nexus mode. Select the SAB Address and Data registers as data register for the TAP. Select the SAB Data register as data register for the TAP. The address is auto-incremented. Cancel an ongoing Nexus or Memory access. Select the SAB Address and Data registers as data register for the TAP. The registers are accessed in Memory Service mode. Select the SAB Address and Data registers as data register for the TAP. Synchronization counter Halt the CPU for safe programming. Bypass this device through the bypass register. Acts as BYPASS Page 910 910 910 911 911 918 918 912 915 916 917 913 914 918 919 911 Table 34-8. Instruction OPCODE 0x01 0x02 0x03 0x04 0x06 0x0C 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x17 0x1C 0x1F Others 909 32072A-AVR32-03/09 AT32UC3A3 34.4.11.1 Security Restrictions When the security fuse in the Flash is programmed, the following JTAG instructions are restricted: * NEXUS_ACCESS * MEMORY_WORD_ACCESS * MEMORY_BLOCK_ACCESS * MEMORY_SIZED_ACCESS For description of what memory locations remain accessible, please refer to the SAB address map. Full access to these instructions is re-enabled when the security fuse is erased by the CHIP_ERASE JTAG instruction. Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 34.4.12 34.4.12.1 Public JTAG Instructions IDCODE This instruction selects the 32 bit ID register as Data Register. The ID register consists of a version number, a device number, and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: * Capture-DR: The static IDCODE value is latched into the shift register. * Shift-DR: The IDCODE scan chain is shifted by the TCK input. 34.4.12.2 SAMPLE_PRELOAD JTAG instruction for taking a snap-shot of the input/output pins without affecting the system operation, and pre-loading the scan chain without updating the DR-latch. The Boundary-Scan Chain is selected as Data Register. The active states are: * Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain. * Shift-DR: The Boundary-Scan Chain is shifted by the TCK input. 34.4.12.3 EXTEST JTAG instruction for selecting the Boundary-Scan Chain as Data Register for testing circuitry external to the AVR32 package. The contents of the latched outputs of the Boundary-Scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction. The active states are: * Capture-DR: Data on the external pins is sampled into the Boundary-Scan Chain. * Shift-DR: The Internal Scan Chain is shifted by the TCK input. * Update-DR: Data from the scan chain is applied to output pins. 910 32072A-AVR32-03/09 AT32UC3A3 34.4.12.4 INTEST This instruction selects the Boundary-Scan Chain as Data Register for testing internal logic in the device. The logic inputs are determined by the Boundary-Scan Chain, and the logic outputs are captured by the Boundary-Scan chain. The device output pins are driven from the BoundaryScan Chain. The active states are: * Capture-DR: Data from the internal logic is sampled into the Boundary-Scan Chain. * Shift-DR: The Internal Scan Chain is shifted by the TCK input. * Update-DR: Data from the scan chain is applied to internal logic inputs. 34.4.12.5 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the Boundary-Scan Chain. The active states are: * Capture-DR: Loads a logic `0' into the Bypass Register. * Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 34.4.12.6 BYPASS JTAG instruction selecting the 1-bit Bypass Register for Data Register. The active states are: * Capture-DR: Loads a logic `0' into the Bypass Register. * Shift-DR: Data is scanned from TDI to TDO through the Bypass register. 34.4.13 34.4.13.1 Private JTAG Instructions Notation The AVR32 defines a number of private JTAG instructions. Each instruction is briefly described in text, with details following in table form. Table 34-10 on page 912 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability. The rightmost bit is always shifted first, and the leftmost bit shifted last. The symbols used are shown in Table 34-9. Table 34-9. Symbol 0 1 a b d e Symbol Description Description Constant low value - always reads as zero. Constant high value - always reads as one. An address bit - always scanned with the least significant bit first A busy bit. Reads as one if the SAB was busy, or zero if it was not. See Section 34.4.10.4 for details on how the busy reporting works. A data bit - always scanned with the least significant bit first. An error bit. Reads as one if an error occurred, or zero if not. See Section 34.4.10.5 for details on how the error reporting works. 911 32072A-AVR32-03/09 AT32UC3A3 Table 34-9. p r s x Symbol Description The chip protected bit. Some devices may be set in a protected state where access to chip internals are severely restricted. See the documentation for the specific device for details. On devices without this possibility, this bit always reads as zero. A direction bit. Set to one to request a read, set to zero to request a write. A size bit. The size encoding is described where used. A don't care bit. Any value can be shifted in, and output data should be ignored. In many cases, it is not required to shift all bits through the data register. Bit patterns are shown using the full width of the shift register, but the suggested or required bits are emphasized using bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is 34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar". The following describes how to interpret the fields in the instruction description tables: Table 34-10. Instruction Description Instruction Description Shows the bit pattern to shift into IR in the Shift-IR state in order to select this instruction. The pattern is show both in binary and in hexadecimal form for convenience. Example: 10000 (0x10) Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is active. Example: peb01 Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g. to distinguish between reads and writes. Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx Shows the bit pattern shifted out of the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g. to distinguish between reads and writes. Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb IR input value IR output value DR Size DR input value DR output value 34.4.13.2 NEXUS_ACCESS This instruction allows Nexus-compliant access to On-Chip Debug registers through the SAB. OCD registers are addressed by their register index, as listed in the AVR32 Technical Reference Manual. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the DR Scan path. 2. Scan in the 7-bit address for the OCD register and a direction bit (1=read, 0=write). 912 32072A-AVR32-03/09 AT32UC3A3 3. Go to Update-DR and re-enter Select-DR Scan. 4. For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 5. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-11. NEXUS_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10000 (0x10) peb01 34 bits aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dddddddd dddddddd dddddddd dddddddd xx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.4.13.3 MEMORY_SERVICE This instruction allows access to registers in an optional Memory Service unit. Memory Service registers are addressed by their register index, as listed in the Memory Service documentation. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the JTAG port. The Memory Service unit may offer features such as CRC calculation of memory, debug trace support, and test features. Please refer to the Memory Service Unit documentation and the part specific documentation for details. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, Memory Service registers are accessed in the following way: 1. Select the DR Scan path. 2. Scan in the 7-bit address for the Memory Service register and a direction bit (1=read, 0=write). 3. Go to Update-DR and re-enter Select-DR Scan. 4. For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 5. Return to Run-Test/Idle. 913 32072A-AVR32-03/09 AT32UC3A3 For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-12. MEMORY_SERVICE Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10100 (0x14) peb01 34 bits aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dddddddd dddddddd dddddddd dddddddd xx xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.4.13.4 MEMORY_SIZED_ACCESS This instruction allows access to the entire Service Access Bus data area. Data are accessed through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units mapped on the SAB bus may support all sizes of accesses, e.g. some may only support word accesses. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. The size field is encoded as i Table 34-13. Table 34-13. Size Field Semantics Size field value Access size Data alignment Address modulo 4 : data alignment 0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx 2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx 3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd 00 Byte (8 bits) 914 32072A-AVR32-03/09 AT32UC3A3 Table 34-13. Size Field Semantics Size field value Access size Data alignment Address modulo 4 : data alignment 0: dddddddd dddddddd xxxxxxxx xxxxxxxx 1: Not allowed 2: xxxxxxxx xxxxxxxx dddddddd dddddddd 3: Not allowed Address modulo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: Not allowed 2: Not allowed 3: Not allowed N/A 01 Halfword (16 bits) 10 Word (32 bits) 11 Reserved Starting in Run-Test/Idle, SAB data are accessed in the following way: 1. Select the DR Scan path. 2. Scan in the 36-bit address of the data to access, a 2-bit access size, and a direction bit (1=read, 0=write). 3. Go to Update-DR and re-enter Select-DR Scan. 4. For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 5. Return to Run-Test/Idle. For any operation, the full 36 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-14. MEMORY_SIZED_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10101 (0x15) peb01 39 bits aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx dddddddd dddddddd dddddddd dddddddd xxxxxxx xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb xxxxxeb dddddddd dddddddd dddddddd dddddddd xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.4.13.5 MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area. Data are accessed through a 34-bit word index, a direction bit, and 32 bits of data. This instruction is identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. The size field is implied, and the two lowest address bits are removed. 915 32072A-AVR32-03/09 AT32UC3A3 Note: This instruction was previously known as MEMORY_ACCESS, and is provided for backwards compatibility. The data register is alternately interpreted by the SAB as an address register and a data register. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. Starting in Run-Test/Idle, SAB data are accessed in the following way: 1. Select the DR Scan path. 2. Scan in the 34-bit address of the data to access, and a direction bit (1=read, 0=write). 3. Go to Update-DR and re-enter Select-DR Scan. 4. For a read operation, scan out the contents of the addressed area. For a write operation, scan in the new contents of the area. 5. Return to Run-Test/Idle. For any operation, the full 34 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-15. MEMORY_WORD_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Address phase) DR input value (Data read phase) DR input value (Data write phase) DR output value (Address phase) DR output value (Data read phase) DR output value (Data write phase) Details 10001 (0x11) peb01 35 bits aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx dddddddd dddddddd dddddddd dddddddd xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb xeb dddddddd dddddddd dddddddd dddddddd xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb 34.4.13.6 MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area. Up to 32 bits of data are accessed at a time, while the address is sequentially incremented from the previously used address. In this mode, the SAB address, size, and access direction is not provided with each access. Instead, the previous address is auto-incremented depending on the specified size and the previous operation repeated. The address must be set up in advance with MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to shift data after shifting the address. This instruction is primarily intended to speed up large quantities of sequential word accesses. It is possible to use it also for byte and halfword accesses, but the overhead in this is case much larger as 32 bits must still be shifted for each access. The following sequence should be used: 916 32072A-AVR32-03/09 AT32UC3A3 1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the first location. 2. Apply MEMORY_BLOCK_ACCESS in the IR Scan path. 3. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corresponding to the next byte, halfword, or word location). 4. For a read operation, scan out the contents of the next addressed location. For a write operation, scan in the new contents of the next addressed location. 5. Go to Update-DR. 6. If the block access is not complete, return to Select-DR Scan and repeat the access. 7. If the block access is complete, return to Run-Test/Idle. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired. Table 34-16. MEMORY_BLOCK_ACCESS Details Instructions IR input value IR output value DR Size DR input value (Data read phase) DR input value (Data write phase) DR output value (Data read phase) DR output value (Data write phase) Details 10010 (0x12) peb01 34 bits xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dddddddd dddddddd dddddddd dddddddd xx eb dddddddd dddddddd dddddddd dddddddd xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 34.4.13.7 CANCEL_ACCESS If a very slow memory location is accessed during a SAB memory access, it could take a very long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a timeout to the user. When the CANCEL_ACCESS instruction is selected, the current access will be terminated as soon as possible. There are no guarantees about how long this will take, as the hardware may not always be able to cancel the access immediately. The SAB is ready to respond to a new command when the busy bit clears. Table 34-17. CANCEL_ACCESS Details Instructions IR input value IR output value DR Size DR input value DR output value Details 10011 (0x13) peb01 1 x 0 917 32072A-AVR32-03/09 AT32UC3A3 34.4.13.8 SYNC This instruction allows external debuggers and testers to measure the ratio between the external JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that counts down to zero using the internal system clock. The busy bit stays high until the counter reaches zero. Starting in Run-Test/Idle, SYNC instruction is used in the following way: 1. Select the DR Scan path. 2. Scan in an 16-bit counter value. 3. Go to Update-DR and re-enter Select-DR Scan. 4. Scan out the busy bit, and retry until the busy bit clears. 5. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 6. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined. When reading status, shifting may be terminated once the required number of bits have been acquired. Table 34-18. SYNC_ACCESS Details Instructions IR input value IR output value DR Size DR input value DR output value Details 10111 (0x17) peb01 16 bits dddddddd dddddddd xxxxxxxx xxxxxxeb 34.4.13.9 AVR_RESET This instruction allows a debugger or tester to directly control separate reset domains inside the chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain. See the device specific documentation for the number of reset domains, and what these domains are. For any operation, all bits must be provided or the result will be undefined. Table 34-19. AVR_RESET Details Instructions IR input value IR output value DR Size DR input value DR output value Details 01100 (0x0C) p0001 Device specific. Device specific. Device specific. 34.4.13.10 CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In 918 32072A-AVR32-03/09 AT32UC3A3 devices without non-volatile memories this instruction does nothing, and appears to complete immediately. The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected. The CHIP_ERASE instruction selects a 1 bit bypass data register. A chip erase operation should be performed as: 1. Scan in the HALT instruction 2. Scan in the value 1 to halt the CPU 3. Stay in Run-Test/Idle for 10 TCK cycles to let the halt command propagate properly 4. Scan in the CHIP_ERASE instruction 5. Keep scanning the CHIP_ERASE instruction until the busy bit is cleared and the protection bit is cleared. 6. Scan in the HALT instruction 7. Scan in the value 0 to release the CPU 8. Return to Run-Test/Idle 9. Stay in Run-Test/Idle for 10 TCK cycles to let the halt command propagate properly. Table 34-20. CHIP_ERASE Details Instructions IR input value IR output value DR Size DR input value DR output value Details 01111 (0x0F) p0b01 Where b is the busy bit. 1 bit x 0 34.4.13.11 HALT This instruction allows a programmer to easily stop the CPU to ensure that it does not execute invalid code during programming. This instruction selects a 1-bit halt register. Setting this bit to one resets the device and halts the CPU. Setting this bit to zero resets the device and releases the CPU to run normally. The value shifted out from the data register is one if the CPU is halted. The HALT instruction can be used in the following way: 1. Scan in the HALT instruction 2. Scan in the value 1 to halt the CPU 3. Stay in Run-Test/Idle for 10 TCK cycles to let the command propagate properly 4. Use any MEMORY_* instructions to program the device 5. Scan in the HALT instruction 6. Scan in the value 0 to release the CPU 7. Return to Run-Test/Idle 919 32072A-AVR32-03/09 AT32UC3A3 8. Stay in Run-Test/Idle for 10 TCK cycles to let the command propagate properly - the device now runs with the new code. Table 34-21. HALT Details Instructions IR input value IR output value DR Size DR input value DR output value Details 11100 (0x1C) p0001 1 bit d d 920 32072A-AVR32-03/09 AT32UC3A3 34.4.14 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. Device Identification Register The Device Identification Register contains a unique identifier for each product. The register is selected by the IDCODE instruction, which is the default instruction after a JTAG reset. MSB Bit Device ID 31 28 27 Part Number 34.4.14.1 LSB 12 11 Manufacturer ID 1 0 1 Revision 4 bits 16 bits 11 bits 1 bit Revision Part Number Manufacturer ID This is a 4 bit number identifying the revision of the component. Rev A = 0x0, B = 0x1, etc. The part number is a 16 bit code identifying the component. The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is 0x01F. *Device specific ID codes The different device configurations have different JTAG ID codes, as shown in Table 34-22. Note that if the flash controller is statically reset, the ID code will be undefined. Table 34-22. Device and JTAG ID Device name AT32UC3A3256S AT32UC3A3128S AT32UC3A364S AT32UC3A3256 AT32UC3A3128 AT32UC3A364 JTAG ID code (r is the revision number) 0xr202003F 0xr202103F 0xr202203F 0xr202603F 0xr202703F 0xr202803F 34.4.14.2 Reset register The reset register is selected by the AVR_RESET instruction and contains one bit for each reset domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared. LSB Bit Device ID 4 OCD 3 APP 2 RESERVED 1 RESERVED 0 CPU 921 32072A-AVR32-03/09 AT32UC3A3 CPU APP OCD RSERVED CPU HSB and PB buses On-Chip Debug logic and registers No effect Note: This register is primarily intended for compatibility with other AVR32 devices. Certain operations may not function correctly when parts of the system are reset. It is generally recommended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects occur. 34.4.14.3 Boundary-Scan Chain The Boundary-Scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the internal logic. Typically, output value, output enable, and input data are all available in the boundary scan chain. The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file available at the Atmel web site. 922 32072A-AVR32-03/09 AT32UC3A3 35. Electrical Characteristics 35.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature.................................... -40C to +85C Storage Temperature .......................................................... ....60C to +150C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP144 packag ................................................... 370 mA for TBGA144 package ................................................. 370 mA 35.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Symbol VVDDIO VIL VIH Parameter DC Supply Peripheral I/Os Input Low-level Voltage Input High-level Voltage IOL=-2mA for Pin drive x1 IOL=-4mA for Pin drive x2 IOL=-8mA for Pin drive x3 IOL=2mA for Pin drive x1 IOL=4mA for Pin drive x2 IOL=8mA for Pin drive x3 Pullup resistors disabled 7 9 15 25 2.0 4.0 8.0 On VVDDIN = 3.3V, CPU in static mode VVDDIO-0.4 Condition Min. 3.0 -0.3 2.0 Typ. Max. 3.6 +0.8 VVDDIO+0 .3 0.4 Units V V V VOL Output Low-level Voltage V VOH ILEAK CIN RPULLUP Output High-level Voltage Input Leakage Current Input Capacitance Pull-up Resistance Output Current Pin drive x1 Pin drive x2 Pin drive x3 See Table 35-1 V A pF Ohm IO mA ISC Static Current TA =25C TA =85C TBD TBD A A 923 32072A-AVR32-03/09 AT32UC3A3 Table 35-1. PIN Pins drive capabilities Drive PIN Drive PIN Drive PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 x3 x1 x1 x1 x1 x1 x1 x1 x3 x2 x2 x2 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x2 x1 x1 x1 x1 x1 x1 x1 x1 x1 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 x1 x1 x3 x2 x2 x2 x1 x1 x1 x1 x1 x1 x1 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x3 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 924 32072A-AVR32-03/09 AT32UC3A3 35.3 35.3.1 Symbol VVDDIN VVDDCORE IOUT Regulator characteristics Electrical characteristics Parameter Supply voltage (input) Supply voltage (output) Maximum DC output current with VVDDIN = 3.3V Maximum DC output current with VVDDIN = 2.7V Condition Min. 2.7 1.81 Typ. 3.3 1.85 Max. 3.6 1.89 100 90 Units V V mA mA 35.3.2 Symbol CIN1 CIN2 COUT1 COUT2 Decoupling requirements Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Condition Typ. 1 4.7 470 2.2 Techno. NPO X7R NPO X7R Units nF uF pF uF 35.3.3 BOD Table 35-2. BODLEVEL Values Typ. Units. BODLEVEL Value 111111b 101000b 100000b 011000b 000000b 1.58 1.62 1.67 1.77 1.92 V V V V V The values in Table 35-2 describes the values of the BODLEVEL in the flash FGPFRL register. 35.4 Power Consumption The values in Table 35-3 and Table 35-4 on page 927 are measured values of power consumption with operating conditions as follows: *VDDIO = 3.3V *TA = 25C, TA = 85C *I/Os are configured in input, pull-up enabled. 925 32072A-AVR32-03/09 AT32UC3A3 Figure 35-1. Measurement setup VDDANA Amp0 VDDIO Amp1 VDDIN Internal Voltage Regulator VDDCORE GNDCORE GNDPLL 926 32072A-AVR32-03/09 AT32UC3A3 These figures represent the power consumption measured on the power supplies. Table 35-3. Power Consumption for Different Modes(1) Consumption Typ. f = 12 MHz f = 24 MHz f = 36MHz f = 50 MHz 10 18 27 34 Mode Conditions CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Typ : Ta = 25 C CPU is in static mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped Unit mA mA mA mA Active f = 60 MHz 42 mA on Amp0 0 uA Static on Amp1 <100 uA 1. Core frequency is generated from XIN0 using the PLL so that 140 MHz < fpll0 < 160 MHz and 10 MHz < fxin0 < 12MHz Table 35-4. Peripheral GPIO SMC SDRAMC ADC EBI INTC TWI PDCA RTC SPI SSC TC USART Power Consumption by Peripheral in Active Mode Consumption 37 10 4 18 31 25 14 30 7 13 13 10 35 A/MHz Unit 35.5 Clock Characteristics These parameters are given in the following conditions: * VDDCORE = 1.8V 927 32072A-AVR32-03/09 AT32UC3A3 * Ambient Temperature = 25C 35.5.1 CPU/HSB Clock Characteristics Core Clock Waveform Parameters Parameter CPU Clock Frequency CPU Clock Period 15.5 Conditions Min Max 66 Units MHz ns Table 35-5. Symbol 1/(tCPCPU) tCPCPU 35.5.2 PBA Clock Characteristics PBA Clock Waveform Parameters Parameter PBA Clock Frequency PBA Clock Period 15.5 Conditions Min Max 66 Units MHz ns Table 35-6. Symbol 1/(tCPPBA) tCPPBA 35.5.3 PBB Clock Characteristics PBB Clock Waveform Parameters Parameter PBB Clock Frequency PBB Clock Period 15.5 Conditions Min Max 66 Units MHz ns Table 35-7. Symbol 1/(tCPPBB) tCPPBB 35.5.4 XIN Clock Characteristics XIN Clock Electrical Characteristics Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pulldown Resistor (1) (1) Table 35-8. Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Note: Conditions Min 3 20.0 0.4 x tCPXIN 0.4 x tCPXIN Max 24 Units MHz ns 0.6 x tCPXIN 0.6 x tCPXIN TBD TBD pF k 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register.) 35.6 Crystal Oscillator Characteristis The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified. 928 32072A-AVR32-03/09 AT32UC3A3 35.6.1 32 KHz Oscillator Characteristics 32 KHz Oscillator Characteristics Parameter Crystal Oscillator Frequency Equivalent Load Capacitance Duty Cycle tST Note: Startup Time RS = TBD k, CL = TBD pF (1) Table 35-9. Symbol 1/(tCP32KHz) CL Conditions Min Typ 32 768 Max Unit Hz 6 TBD 12.5 TBD TBD pF % ms 1. RS is the equivalent series resistance, CL is the equivalent load capacitance. 35.6.2 Main Oscillators Characteristics Table 35-10. Main Oscillator Characteristics Symbol 1/(tCPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle tST IOSC Startup Time Active mode @TBD MHz Current Consumption Standby mode @TBD V 1. CS is the shunt capacitance TBD A 40 Conditions Min 3 12 TBD 50 60 TBD TBD Typ Max 16 Unit MHz pF pF % ms A Notes: 35.6.3 PLL Characteristics Table 35-11. Phase Lock Loop Characteristics Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency active mode Current Consumption standby mode 1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. TBD A Conditions Min 80 TBD Typ Max 240 TBD TBD Unit MHz MHz mA Note: 929 32072A-AVR32-03/09 AT32UC3A3 35.7 ADC Characteristics Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 600 ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz 2 1.25 384(1) 533(2) Min Typ Max 5 8 20 Units MHz MHz s ns s s kSPS kSPS Table 35-12. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes: 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. Table 35-13. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 TBD 17 Typ Max VDDANA A pF Units Table 35-14. Transfer Characteristics Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error f=5MHz f=5MHz f=5MHz f=5MHz f=5MHz -0.5 -0.5 0.35 0.3 Conditions Min Typ 10 0.8 0.5 0.5 0.5 0.5 Max Units Bit LSB LSB LSB LSB LSB 930 32072A-AVR32-03/09 AT32UC3A3 35.8 35.8.1 USB Transceiver Characteristics Electrical Characteristics Table 35-15. Electrical Parameters Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 k tied to 3.6V Measured with RL of 14.25 k tied to GND TBD TBD TBD TBD TBD TBD V V V Low Level High Level Differential Input Sensivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with 5% TBD TBD |(D+) - (D-)| TBD TBD TBD TBD TBD TBD TBD V V V V pF A Parameter Conditions Min Typ Max Unit 35.8.2 Switching Characteristics Table 35-16. In Low Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 400 pF CLOAD = 400 pF CLOAD = 400 pF Min TBD TBD TBD Typ Max TBD TBD TBD Unit ns ns % Table 35-17. In Full Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min TBD TBD TBD Typ Max TBD TBD TBD Unit ns ns % 931 32072A-AVR32-03/09 AT32UC3A3 35.9 EBI Timings These timings are given for worst case process, T = 85C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 35-18. SMC Clock Signal. Symbol 1/(tCPSMC) Note: Parameter SMC Controller Clock Frequency Max(1) 1/(tcpcpu) Units MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 35-19. SMC Read Signals with Hold Settings Symbol Parameter NRD Controlled (READ_MODE = 1) SMC1 SMC2 SMC3 SMC4 SMC5 SMC7 SMC8 SMC9 Min Units Data Setup before NRD High Data Hold after NRD High NRD High to NBS0/A0 Change NRD High to NBS1 Change(1) NRD High to NBS2/A1 Change (1) (1) 12 0 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 nrd pulse length * tCPSMC - 1.4 ns NRD High to A2 - A23 Change(1) NRD High to NCS Inactive NRD Pulse Width (1) NRD Controlled (READ_MODE = 0) SMC10 SMC11 SMC12 SMC13 SMC14 SMC16 SMC17 SMC18 Note: Data Setup before NCS High Data Hold after NCS High NCS High to NBS0/A0 Change(1) NCS High to NBS0/A0 Change (1) 11.5 0 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 4 ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ncs rd pulse length * tCPSMC - 3.6 ns NCS High to NBS2/A1 Change(1) NCS High to A2 - A23 Change(1) NCS High to NRD Inactive(1) NCS Pulse Width 1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs rd hold length" or "nrd hold length". 932 32072A-AVR32-03/09 AT32UC3A3 Table 35-20. SMC Read Signals with no Hold Settings Symbol Parameter NRD Controlled (READ_MODE = 1) SMC19 SMC20 Min Units Data Setup before NRD High Data Hold after NRD High NRD Controlled (READ_MODE = 0) 13.7 ns 1 SMC21 SMC22 Data Setup before NCS High Data Hold after NCS High 13.3 ns 0 Table 35-21. SMC Write Signals with Hold Settings Symbol Parameter NRD Controlled (READ_MODE = 1) SMC23 SMC24 SMC25 SMC26 SMC29 SMC31 SMC32 SMC33 Min Units Data Out Valid before NWE High Data Out Valid after NWE High(1) NWE High to NBS0/A0 Change NWE High to NBS1 Change(1) NWE High to A1 Change (1) (1) (nwe pulse length - 1) * tCPSMC - 0.9 nwe hold length * tCPSMC - 6 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.7 (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 nwe pulse length * tCPSMC - 0.9 ns NWE High to A2 - A23 Change(1) NWE High to NCS Inactive NWE Pulse Width (1) NRD Controlled (READ_MODE = 0) SMC34 SMC35 SMC36 Note: Data Out Valid before NCS High Data Out Valid after NCS High NCS High to NWE Inactive(1) (1) (ncs wr pulse length - 1)* tCPSMC - 4.6 ncs wr hold length * tCPSMC - 5.8 (ncs wr hold length - nwe hold length)* tCPSMC - 0.6 ns 1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "nwe hold length" 933 32072A-AVR32-03/09 AT32UC3A3 Table 35-22. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol SMC37 SMC38 SMC39 SMC40 SMC41 SMC42 SMC43 SMC44 SMC45 Parameter Min Units NWE Rising to A2-A25 Valid NWE Rising to NBS0/A0 Valid NWE Rising to NBS1 Change NWE Rising to A1/NBS2 Change NWE Rising to NBS3 Change NWE Rising to NCS Rising Data Out Valid before NWE Rising Data Out Valid after NWE Rising NWE Pulse Width 5.4 5 5 5 5 5.1 (nwe pulse length - 1) * tCPSMC - 1.2 5 nwe pulse length * tCPSMC - 0.9 ns Figure 35-2. SMC Signals for NCS Controlled Accesses. SMC16 SMC16 SMC16 A2-A25 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 A0/A1/NBS[3:0] NRD SMC17 SMC17 NCS SMC18 SMC22 SMC18 SMC18 SMC21 SMC10 SMC11 SMC34 SMC35 D0 - D15 SMC36 NWE 934 32072A-AVR32-03/09 AT32UC3A3 Figure 35-3. SMC Signals for NRD and NRW Controlled Accesses. SMC7 SMC37 SMC7 SMC31 A2-A25 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 SMC25 SMC26 SMC29 SMC30 A0/A1/NBS[3:0] SMC42 SMC8 SMC32 NCS SMC8 NRD SMC9 SMC9 SMC19 SMC20 SMC43 SMC44 SMC1 SMC2 SMC23 SMC24 D0 - D15 SMC45 SMC33 NWE 35.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 35-23. SDRAM Clock Signal. Symbol 1/(tCPSDCK) Note: Parameter SDRAM Controller Clock Frequency Max(1) 1/(tcpcpu) Units MHz 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB. Table 35-24. SDRAM Clock Signal. Symbol SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 Parameter Min 7.4 3.2 7 2.9 7.5 1.6 7.2 2.3 7.6 1.9 Units ns SDCKE High before SDCK Rising Edge SDCKE Low after SDCK Rising Edge SDCKE Low before SDCK Rising Edge SDCKE High after SDCK Rising Edge SDCS Low before SDCK Rising Edge SDCS High after SDCK Rising Edge RAS Low before SDCK Rising Edge RAS High after SDCK Rising Edge SDA10 Change before SDCK Rising Edge SDA10 Change after SDCK Rising Edge 935 32072A-AVR32-03/09 AT32UC3A3 Table 35-24. SDRAM Clock Signal. Symbol SDRAMC11 SDRAMC12 SDRAMC13 SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC23 SDRAMC24 SDRAMC25 SDRAMC26 Parameter Min 6.2 2.2 6.3 2.4 7.4 1.9 6.4 ns 2.2 9 0 7.6 1.8 7.1 1.5 Units Address Change before SDCK Rising Edge Address Change after SDCK Rising Edge Bank Change before SDCK Rising Edge Bank Change after SDCK Rising Edge CAS Low before SDCK Rising Edge CAS High after SDCK Rising Edge DQM Change before SDCK Rising Edge DQM Change after SDCK Rising Edge D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge SDWE High after SDCK Rising Edge D0-D15 Out Valid before SDCK Rising Edge D0-D15 Out Valid after SDCK Rising Edge 936 32072A-AVR32-03/09 AT32UC3A3 Figure 35-4. SDRAMC Signals relative to SDCK. SDCK SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDCKE SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDCS SDRAMC7 SDRAMC8 RAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 CAS SDRAMC23 SDRAMC24 SDWE SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDA10 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 A0 - A9, A11 - A13 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 BA0/BA1 SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18 DQM0 DQM3 SDRAMC19 SDRAMC20 D0 - D15 Read SDRAMC25 SDRAMC26 D0 - D15 to Write 937 32072A-AVR32-03/09 AT32UC3A3 35.10 JTAG Timings 35.10.1 JTAG Interface Signals Table 35-25. JTAG Interface Timing specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time TCK to Device Outputs Valid 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Conditions (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) Min 6 3 9 1 0 4 Max Units ns ns ns ns ns ns 6 ns ns ns ns ns 938 32072A-AVR32-03/09 AT32UC3A3 Figure 35-5. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8 Device Outputs JTAG9 JTAG10 35.11 SPI Characteristics Figure 35-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 MISO SPI1 SPI2 MOSI 939 32072A-AVR32-03/09 AT32UC3A3 Figure 35-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 MISO SPI4 SPI5 MOSI Figure 35-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI6 MISO SPI7 MOSI SPI8 Figure 35-9. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 MOSI SPI11 940 32072A-AVR32-03/09 AT32UC3A3 Table 35-26. SPI Timings Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 Notes: Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay (master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) Conditions 3.3V domain 3.3V domain 3.3V domain 3.3V domain (1) (1) (1) (1) Min 22 + (tCPMCK)/2 0 (2) Max Units ns ns 7 22 + (tCPMCK)/2 0 7 26.5 0 1.5 27 0 1 (2) ns ns ns ns ns ns ns ns ns ns 3.3V domain (1) 3.3V domain (1) 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain (1) (1) (1) (1) (1) (1) 1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF. 2. tCPMCK: Master Clock period in ns. 35.12 MACB Characteristics Table 35-27. Ethernet MAC Signals Symbol EMAC1 EMAC2 EMAC3 Notes: Parameter Setup for EMDIO from EMDC rising Hold for EMDIO from EMDC rising EMDIO toggling from EMDC falling 1. f: MCK frequency (MHz) 2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Conditions Load: 20pF (2) Min (ns) Max (ns) Load: 20pF(2) Load: 20pF(2) Table 35-28. Ethernet MAC MII Specific Signals Symbol EMAC4 EMAC5 EMAC6 EMAC7 EMAC8 EMAC9 EMAC10 EMAC11 Parameter Setup for ECOL from ETXCK rising Hold for ECOL from ETXCK rising Setup for ECRS from ETXCK rising Hold for ECRS from ETXCK rising ETXER toggling from ETXCK rising ETXEN toggling from ETXCK rising ETX toggling from ETXCK rising Setup for ERX from ERXCK Conditions Load: 20pF Load: 20pF Load: 20pF (1) (1) (1) Min (ns) 3 0 3 0 Max (ns) Load: 20pF (1) Load: 20pF Load: 20pF Load: 20pF (1) (1) (1) 15 15 15 1 Load: 20pF (1) 941 32072A-AVR32-03/09 AT32UC3A3 Table 35-28. Ethernet MAC MII Specific Signals Symbol EMAC12 EMAC13 EMAC14 EMAC15 EMAC16 Note: Parameter Hold for ERX from ERXCK Setup for ERXER from ERXCK Hold for ERXER from ERXCK Setup for ERXDV from ERXCK Hold for ERXDV from ERXCK Conditions Load: 20pF Load: 20pF Load: 20pF (1) (1) (1) Min (ns) 1.5 1 0.5 1.5 1 Max (ns) Load: 20pF (1) Load: 20pF (1) 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Figure 35-10. Ethernet MAC MII Mode EMDC EMAC1 EMDIO EMAC4 ECOL EMAC6 ECRS EMAC7 EMAC5 EMAC2 EMAC3 ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 ERX[3:0] EMAC13 ERXER EMAC15 ERXDV EMAC16 EMAC14 EMAC12 942 32072A-AVR32-03/09 AT32UC3A3 Table 35-29. Ethernet MAC RMII Specific Signals Symbol EMAC21 EMAC22 EMAC23 EMAC24 EMAC25 EMAC26 EMAC27 EMAC28 Parameter ETXEN toggling from EREFCK rising ETX toggling from EREFCK rising Setup for ERX from EREFCK Hold for ERX from EREFCK Setup for ERXER from EREFCK Hold for ERXER from EREFCK Setup for ECRSDV from EREFCK Hold for ECRSDV from EREFCK Min (ns) 7 7 1.5 0 1.5 0 1.5 0 Max (ns) 14.5 14.7 Figure 35-11. Ethernet MAC RMII Mode EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 ERX[1:0] EMAC25 ERXER EMAC27 ECRSDV EMAC28 EMAC26 EMAC24 35.13 Flash Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Table 35-30. Flash Wait States FWS 0 1 Read Operations 1 cycle 2 cycles Maximum Operating Frequency (MHz) 36 66 943 32072A-AVR32-03/09 AT32UC3A3 36. Mechanical Characteristics 36.1 36.1.1 Thermal Considerations Thermal Data Table 36-1 summarizes the thermal resistance data depending on the package. Table 36-1. Symbol JA JC JA JC Thermal Resistance Data Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Still Air Condition Still Air Package TQFP144 TQFP144 TBGA144 TBGA144 Typ TBD TBD TBD TBD C/W Unit C/W 36.1.2 Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA ) T J = T A + ( P D x ( HEATSINK + JC ) ) where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 36-1 on page 944. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 36-1 on page 944. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Regulator characteristics" on page 925. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. 944 32072A-AVR32-03/09 AT32UC3A3 36.2 Package Drawings Figure 36-1. TBGA 144 package drawing 945 32072A-AVR32-03/09 AT32UC3A3 Figure 36-2. LQFP-144 package drawing Table 36-2. TBD Device and Package Maximum Weight mg Table 36-3. Package Characteristics TBD Moisture Sensitivity Level Table 36-4. Package Reference MS-026 E3 JEDEC Drawing Reference JESD97 Classification 946 32072A-AVR32-03/09 AT32UC3A3 Table 36-5. TBD Device and Package Maximum Weight mg 36.3 Soldering Profile Table 36-6 gives the recommended soldering profile from J-STD-20. Table 36-6. Soldering Profile Green Package TBD TBD TBD TBD TBD TBD TBD Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature Note: It is recommended to apply a soldering temperature higher than 250C. A maximum of three reflow passes is allowed per component. 947 32072A-AVR32-03/09 AT32UC3A3 37. Ordering Information Device AT32UC3A3256S Ordering Code AT32UC3A3256S-ALUT AT32UC3A3256S-ALUR AT32UC3A3256S-CTUT AT32UC3A3256S-CTUR AT32UC3A3256 AT32UC3A3256-ALUT AT32UC3A3256-ALUR AT32UC3A3256-CTUT AT32UC3A3256-CTUR AT32UC3A3128S AT32UC3A3128S-ALUT AT32UC3A3128S-ALUR AT32UC3A3128S-CTUT AT32UC3A3128S-CTUR AT32UC3A3128 AT32UC3A3128-ALUT AT32UC3A3128-ALUR AT32UC3A3128-CTUT AT32UC3A3128-CTUR AT32UC3A364S AT32UC3A364S-ALUT AT32UC3A364S-ALUR AT32UC3A364S-CTUT AT32UC3A364S-CTUR AT32UC3A364 AT32UC3A364-ALUT AT32UC3A364-ALUR AT32UC3A364-CTUT AT32UC3A364-CTUR Package 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA 144 lead LQFP 144 lead LQFP 144 balls TBGA 144 balls TBGA Conditioning Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Temperature Operating Range Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) 948 32072A-AVR32-03/09 AT32UC3A3 38. Errata 38.1 38.1.1 Rev. E Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 38.1.2 ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 38.1.3 SPI 1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 2. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 38.2 38.2.1 Rev. D Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround 949 32072A-AVR32-03/09 AT32UC3A3 When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE. 3. Exceptions when system stack is protected by MPU RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Workaround 1: Make system stack readable in unprivileged mode, or Workaround 2: Return from supervisor mode using rete instead of rets. This requires : 1. Changing the mode bits from 001b to 110b before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. Even if this step is described in general as not safe in the UC technical reference guide, it is safe in this very specific case. 2. Execute the RETE instruction. 4. Multiply instructions do not work on RevD. All the multiply instructions do not work. Fix/Workaround Do not use the multiply instructions. 38.2.2 ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 38.2.3 SPI 1. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 2. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 38.2.4 TWI 1. TWIM Version Register is zero TWIM Version Register (VR) is zero instead of 0x100. Fix/Workaround None. 950 32072A-AVR32-03/09 AT32UC3A3 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 Rev. A - 03/09 1. Initial revision. 951 32072A-AVR32-03/09 AT32UC3A3 Table of Contents 1 2 Description ............................................................................................... 3 Overview ................................................................................................... 4 2.1Block Diagram ...........................................................................................................4 3 4 Configuration Summary .......................................................................... 5 Package and Pinout ................................................................................. 6 4.1Package ....................................................................................................................6 4.2Peripheral Multiplexing on I/O lines ...........................................................................8 4.3Signal Descriptions ..................................................................................................12 4.4Power Considerations .............................................................................................17 5 Processor and Architecture .................................................................. 18 5.1Features ..................................................................................................................18 5.2AVR32 Architecture .................................................................................................18 5.3The AVR32UC CPU ................................................................................................19 5.4Programming Model ................................................................................................23 5.5Exceptions and Interrupts ........................................................................................27 6 Memories ................................................................................................ 31 6.1Embedded Memories ..............................................................................................31 6.2Physical Memory Map .............................................................................................31 6.3Peripheral Address Map ..........................................................................................32 6.4CPU Local Bus Mapping .........................................................................................34 7 Boot Sequence ....................................................................................... 35 7.1Starting of Clocks ....................................................................................................35 7.2Fetching of Initial Instructions ..................................................................................35 8 Power Manager (PM) .............................................................................. 36 8.1Features ..................................................................................................................36 8.2Overview .................................................................................................................36 8.3Block Diagram .........................................................................................................37 8.4Product Dependencies ............................................................................................38 8.5Functional Description .............................................................................................38 8.6User Interface ..........................................................................................................49 9 Real Time Counter (RTC) ...................................................................... 72 9.1Features ..................................................................................................................72 952 32072A-AVR32-03/09 AT32UC3A3 9.2Overview .................................................................................................................72 9.3Block Diagram .........................................................................................................72 9.4Product Dependencies ............................................................................................72 9.5Functional Description .............................................................................................73 9.6User Interface ..........................................................................................................75 10 Watchdog Timer (WDT) ......................................................................... 84 10.1Features ................................................................................................................84 10.2Overview ...............................................................................................................84 10.3Block Diagram .......................................................................................................84 10.4Product Dependencies ..........................................................................................84 10.5Functional Description ...........................................................................................85 10.6User Interface ........................................................................................................86 11 Interrupt Controller (INTC) .................................................................... 89 11.1Features ................................................................................................................89 11.2Overview ...............................................................................................................89 11.3Block Diagram .......................................................................................................89 11.4Product Dependencies ..........................................................................................90 11.5Functional Description ...........................................................................................90 11.6User Interface ........................................................................................................91 11.7Interrupt Request Signal Map ................................................................................95 12 External Interrupt Controller (EIC) ....................................................... 99 12.1Features ................................................................................................................99 12.2Overview ...............................................................................................................99 12.3Block Diagram .....................................................................................................100 12.4I/O Lines Description ...........................................................................................100 12.5Product Dependencies ........................................................................................100 12.6Functional Description .........................................................................................101 12.7User Interface ......................................................................................................105 13 Flash Controller (FLASHC) ................................................................. 121 13.1Features ..............................................................................................................121 13.2Overview .............................................................................................................121 13.3Product dependencies .........................................................................................121 13.4Functional description .........................................................................................122 13.5Flash commands .................................................................................................124 13.6General-purpose fuse bits ...................................................................................126 953 32072A-AVR32-03/09 AT32UC3A3 13.7Security bit ...........................................................................................................128 13.8User Interface ......................................................................................................129 13.9Fuses Settings .....................................................................................................137 13.10Module configuration .........................................................................................138 14 HSB Bus Matrix (HMATRIX) ................................................................ 139 14.1Features .............................................................................................................139 14.2Overview .............................................................................................................139 14.3Product Dependencies ........................................................................................139 14.4Functional Description .........................................................................................139 14.5User Interface ......................................................................................................143 14.6Bus Matrix Connections ......................................................................................152 15 External Bus Interface (EBI) ................................................................ 154 15.1Features ..............................................................................................................154 15.2Overview .............................................................................................................154 15.3Block Diagram .....................................................................................................155 15.4I/O Lines Description ...........................................................................................156 15.5Product Dependencies ........................................................................................157 15.6Functional Description .........................................................................................159 15.7Application Example ............................................................................................166 16 Static Memory Controller (SMC) ......................................................... 169 16.1Features .............................................................................................................169 16.2Overview .............................................................................................................169 16.3Block Diagram .....................................................................................................170 16.4I/O Lines Description ...........................................................................................170 16.5Product Dependencies ........................................................................................170 16.6Functional Description .........................................................................................171 16.7User Interface ......................................................................................................203 17 SDRAM Controller (SDRAMC) ............................................................ 210 17.1Features ..............................................................................................................210 17.2Overview .............................................................................................................210 17.3Block Diagram .....................................................................................................211 17.4I/O Lines Description ...........................................................................................211 17.5Application Example ............................................................................................211 17.6Product Dependencies ........................................................................................213 17.7Functional Description .........................................................................................214 954 32072A-AVR32-03/09 AT32UC3A3 17.8User Interface ......................................................................................................223 18 Error Corrected Code Controller (ECCHRS) ...................................... 236 18.1Features .............................................................................................................236 18.2Overview .............................................................................................................236 18.3Block Diagram .....................................................................................................237 18.4Product Dependencies ........................................................................................237 18.5Functional Description .........................................................................................238 18.6User Interface .....................................................................................................244 18.7Module Configuration ..........................................................................................271 19 Peripheral DMA Controller (PDCA) .................................................... 272 19.1Features ..............................................................................................................272 19.2Overview .............................................................................................................272 19.3Block Diagram .....................................................................................................273 19.4Product Dependencies ........................................................................................273 19.5Functional Description .........................................................................................274 19.6User Interface ......................................................................................................277 19.7Module Configuration ..........................................................................................305 20 DMA Controller (DMACA) .................................................................... 306 20.1Features ..............................................................................................................306 20.2Overview .............................................................................................................306 20.3Block Diagram .....................................................................................................307 20.4Product Dependencies ........................................................................................307 20.5Functional Description .........................................................................................308 20.6Arbitration for HSB Master Interface ...................................................................313 20.7Memory Peripherals ............................................................................................313 20.8Handshaking Interface ........................................................................................313 20.9DMACA Transfer Types ......................................................................................315 20.10Programming a Channel ...................................................................................319 20.11Disabling a Channel Prior to Transfer Completion ............................................336 20.12User Interface ....................................................................................................338 20.13Module Configuration ........................................................................................370 21 General-Purpose Input/Output Controller (GPIO) ............................. 371 21.1Features ..............................................................................................................371 21.2Overview .............................................................................................................371 21.3Block Diagram .....................................................................................................371 955 32072A-AVR32-03/09 AT32UC3A3 21.4Product Dependencies ........................................................................................371 21.5Functional Description .........................................................................................372 21.6User Interface ......................................................................................................376 21.7Programming Examples ......................................................................................391 22 Serial Peripheral Interface (SPI) ......................................................... 393 22.1Features ..............................................................................................................393 22.2Overview .............................................................................................................393 22.3Block Diagram .....................................................................................................394 22.4Application Block Diagram ..................................................................................394 22.5I/O Lines Description ...........................................................................................395 22.6Product Dependencies ........................................................................................395 22.7Functional Description .........................................................................................395 22.8User Interface ......................................................................................................406 22.9Module Configuration ..........................................................................................427 23 Two-Wire Slave Interface (TWIS) ........................................................ 428 23.1Features ..............................................................................................................428 23.2Overview .............................................................................................................428 23.3List of Abbreviations ............................................................................................429 23.4Block Diagram .....................................................................................................429 23.5Application Block Diagram ..................................................................................430 23.6I/O Lines Description ...........................................................................................430 23.7Product Dependencies ........................................................................................430 23.8Functional Description .........................................................................................431 23.9User Interface ......................................................................................................440 23.10Module Configuration ........................................................................................456 24 Two-Wire Master Interface (TWIM) ..................................................... 457 24.1Features ..............................................................................................................457 24.2Overview .............................................................................................................457 24.3List of Abbreviations ............................................................................................458 24.4Block Diagram .....................................................................................................459 24.5Application Block Diagram ..................................................................................459 24.6I/O Lines Description ...........................................................................................459 24.7Product Dependencies ........................................................................................460 24.8Functional Description .........................................................................................461 24.9User Interface ......................................................................................................473 956 32072A-AVR32-03/09 AT32UC3A3 24.10Module Configuration ........................................................................................490 25 Synchronous Serial Controller (SSC) ................................................ 491 25.1Features .............................................................................................................491 25.2Overview .............................................................................................................491 25.3Block Diagram .....................................................................................................492 25.4Application Block Diagram ..................................................................................492 25.5I/O Lines Description ...........................................................................................493 25.6Product Dependencies ........................................................................................493 25.7Functional Description .........................................................................................493 25.8SSC Application Examples ..................................................................................505 25.9User Interface ......................................................................................................507 26 Universal Synchronous Asynchronous Receiver Transmitter (USART) 529 26.1Features ..............................................................................................................529 26.2Overview .............................................................................................................529 26.3Block Diagram .....................................................................................................531 26.4Application Block Diagram ..................................................................................532 26.5I/O Lines Description ..........................................................................................533 26.6Product Dependencies ........................................................................................534 26.7Functional Description .........................................................................................535 26.8User Interface ......................................................................................................591 26.9Module Configuration ..........................................................................................619 27 Hi-Speed USB On-The-Go Interface (USBB) ...................................... 620 27.1Features ..............................................................................................................620 27.2Overview .............................................................................................................620 27.3Block Diagram .....................................................................................................621 27.4Application Block Diagram ..................................................................................622 27.5I/O Lines Description ...........................................................................................624 27.6Product Dependencies ........................................................................................625 27.7Functional Description .........................................................................................626 27.8User Interface ......................................................................................................656 27.9Module Configuration ..........................................................................................739 28 Timer/Counter (TC) .............................................................................. 740 28.1Features ..............................................................................................................740 28.2Overview .............................................................................................................740 957 32072A-AVR32-03/09 AT32UC3A3 28.3Block Diagram .....................................................................................................741 28.4I/O Lines Description ...........................................................................................741 28.5Product Dependencies ........................................................................................741 28.6Functional Description .........................................................................................742 28.7User Interface ......................................................................................................757 28.8Module Configuration ..........................................................................................777 29 Analog-to-Digital Converter (ADC) ..................................................... 778 29.1Features ..............................................................................................................778 29.2Overview .............................................................................................................778 29.3Block Diagram .....................................................................................................779 29.4I/O Lines Description ...........................................................................................779 29.5Product Dependencies ........................................................................................779 29.6Functional Description .........................................................................................780 29.7User Interface ......................................................................................................785 29.8Module Configuration ..........................................................................................798 30 HSB Bus Performance Monitor (BUSMON) ....................................... 799 30.1Features ..............................................................................................................799 30.2Overview .............................................................................................................799 30.3Block Diagram .....................................................................................................799 30.4Product Dependencies ........................................................................................800 30.5Functional Description .........................................................................................800 30.6User interface ......................................................................................................801 30.7Module Configuration ..........................................................................................808 31 MultiMedia Card Interface (MCI) ......................................................... 809 31.1Features ..............................................................................................................809 31.2Overview .............................................................................................................809 31.3Block Diagram .....................................................................................................810 31.4I/O Lines Description ...........................................................................................811 31.5Product Dependencies ........................................................................................811 31.6Functional Description .........................................................................................811 31.7User Interface ......................................................................................................829 31.8Module Configuration ..........................................................................................856 32 Advanced Encryption Standard (AES) ............................................... 857 32.1Features ..............................................................................................................857 32.2Overview .............................................................................................................857 958 32072A-AVR32-03/09 AT32UC3A3 32.3Product Dependencies ........................................................................................857 32.4Functional Description .........................................................................................858 32.5User Interface ......................................................................................................864 32.6Module Configuration ..........................................................................................879 33 Audio Bitstream DAC (ABDAC) .......................................................... 880 33.1Features ..............................................................................................................880 33.2Overview .............................................................................................................880 33.3Block Diagram .....................................................................................................881 33.4I/O Lines Description ...........................................................................................881 33.5Product Dependencies ........................................................................................881 33.6Functional Description .........................................................................................882 33.7User Interface ......................................................................................................884 34 Programming and Debugging ............................................................ 892 34.1Overview .............................................................................................................892 34.2Service Access Bus .............................................................................................892 34.3On-Chip Debug (OCD) ........................................................................................894 34.4JTAG and Boundary Scan (JTAG) ......................................................................902 35 Electrical Characteristics .................................................................... 923 35.1Absolute Maximum Ratings* ...............................................................................923 35.2DC Characteristics ..............................................................................................923 35.3Regulator characteristics .....................................................................................925 35.4Power Consumption ............................................................................................925 35.5Clock Characteristics ...........................................................................................927 35.6Crystal Oscillator Characteristis ..........................................................................928 35.7ADC Characteristics ............................................................................................930 35.8USB Transceiver Characteristics .........................................................................931 35.9EBI Timings .........................................................................................................932 35.10JTAG Timings ....................................................................................................938 35.11SPI Characteristics ............................................................................................939 35.12MACB Characteristics .......................................................................................941 35.13Flash Characteristics .........................................................................................943 36 Mechanical Characteristics ................................................................. 944 36.1Thermal Considerations ......................................................................................944 36.2Package Drawings ..............................................................................................945 36.3Soldering Profile ..................................................................................................947 959 32072A-AVR32-03/09 AT32UC3A3 37 Ordering Information ........................................................................... 948 38 Errata ..................................................................................................... 949 38.1Rev. E ..................................................................................................................949 38.2Rev. D .................................................................................................................949 39 Datasheet Revision History ................................................................ 951 39.1Rev. A - 03/09 .....................................................................................................951 960 32072A-AVR32-03/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr32@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, AVR(R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 32072A-AVR32-03/09 |
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